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Basys 3™ FPGA Board Reference Manual

Revised April 8, 2016
This manual applies to the Basys 3 rev. C

Overview
The Basys 3 board is a complete, ready-to-use digital circuit development platform based on the latest Artix®-7
Field Programmable Gate Array (FPGA) from Xilinx®. With its high-capacity FPGA (Xilinx part number XC7A35T-
1CPG236C), low overall cost, and collection of USB, VGA, and other ports, the Basys 3 can host designs ranging
from introductory combinational circuits to complex sequential circuits like embedded processors and controllers.
It includes enough switches, LEDs, and other I/O devices to allow a large number of designs to be completed
without the need for any additional hardware, and enough uncommitted FPGA I/O pins to allow designs to be
expanded using Digilent Pmods or other custom boards and circuits.

The Artix-7 FPGA is optimized for high performance logic, and offers more capacity, higher performance, and more
resources than earlier designs. Artix-7 35T features include:

 33,280 logic cells in 5200 slices (each slice contains four

6-input LUTs and 8 flip-flops)
 1,800 Kbits of fast block RAM
 Five clock management tiles, each with a phase-locked
loop (PLL)
 90 DSP slices
 Internal clock speeds exceeding 450MHz
 On-chip analog-to-digital converter (XADC)

The Basys 3.

The Basys 3 also offers an improved collection of ports and peripherals, including:

 16 user switches  16 user LEDs  5 user pushbuttons

 4-digit 7-segment display  Three Pmod ports  Pmod for XADC signals
 12-bit VGA output  USB-UART Bridge  Serial Flash
 Digilent USB-JTAG port for  USB HID Host for mice, keyboards
FPGA programming and and memory sticks
communication

The Basys 3 works with Xilinx's new high-performance Vivado™ Design Suite. Vivado includes many new tools and
design flows that facilitate and enhance the latest design methods. It runs faster, allows better use of FPGA
resources, and allows designers to focus their time evaluating design alternatives. The System Edition includes an
on-chip logic analyzer, high-level synthesis tool, other cutting-edge tools, and the free WebPACK™ version allows
Basys 3 designs to be created at no additional cost.

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Basys 3™ FPGA Board Reference Manual

16 15 14 13 12 11 10 9

1 8

2 2

3 2

6
4

Figure 1. Basys 3 FPGA board with callouts.

Callout Component Description Callout Component Description

1 Power good LED 9 FPGA configuration reset button
2 Pmod port(s) 10 Programming mode jumper
3 Analog signal Pmod port (XADC) 11 USB host connector
4 Four digit 7-segment display 12 VGA connector
5 Slide switches (16) 13 Shared UART/ JTAG USB port
6 LEDs (16) 14 External power connector
7 Pushbuttons (5) 15 Power Switch
8 FPGA programming done LED 16 Power Select Jumper
Table 1. Basys 3 Callouts and component descriptions.

A growing collection of board support IP, reference designs, and add-on boards are available on the Digilent
website. See the Basys 3 page at www.digilentinc.com for more information.

1 Power Supplies
The Basys 3 board can receive power from the Digilent USB-JTAG port (J4) or from a 5V external power supply.
Jumper JP3 (near the power switch) determines which source is used.

All Basys 3 power supplies can be turned on and off by a single logic-level power switch (SW16). A power-good LED
(LD20), driven by the "power good" output of the LTC3633 supply, indicates that the supplies are turned on and
operating normally. An overview of the Basys 3 power circuit is shown in Fig. 2.

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Basys 3™ FPGA Board Reference Manual

Power
Switch
(SW16) + - VU5V0

JP2 ON/OFF
5V External Type A USB Host
Supply J6 Connector (J2)

Micro-USB VIN2 2A 3.3V

Port (J4) EN2 PGOOD2

VIN1 1A 1.0V
Power Source Select EN1 PGOOD1
IC10: LTC3633 Power On
JP2 LED (LD20)

USB EXTERNAL

VIN PGOOD

EN 300 mA 1.8V
IC11: LTC3621

Figure 2. Basys 3 power circuit.

The USB port can deliver enough power for the vast majority of designs. A few demanding applications, including
any that drive multiple peripheral boards, might require more power than the USB port can provide. Also, some
applications may need to run without being connected to a PC's USB port. In these instances an external power
supply or battery pack can be used.

An external power supply can be used by plugging into the external power header (J6) and setting jumper JP2 to
"EXT". The supply must deliver 4.5VDC to 5.5VDC and at least 1A of current (i.e., at least 5W of power). Many
suitable supplies can be purchased through Digi-Key or other catalog vendors.

An external battery pack can be used by connecting the battery's positive terminal to the "EXT" pin of J6 and the
negative terminal to the "GND" pin of J6. The power provided to USB devices that are connected to Host connector
J2 is not regulated. Therefore, it is necessary to limit the maximum voltage of an external battery pack to 5.5V DC.
The minimum voltage of the battery pack depends on the application; if the USB Host function (J2) is used, at least
4.6V needs to be provided. In other cases, the minimum voltage is 3.6V.

Voltage regulator circuits from Linear Technology create the required 3.3V, 1.8V, and 1.0V supplies from the main
power input. Table 2 provides additional information (typical currents depend strongly on FPGA configuration and
the values provided are typical of medium size/speed designs).

Supply Circuits Device Current (max/typical)

FPGA I/O, USB ports, Clocks,
3.3V IC10: LTC3633 2A/0.1 to 1.5A
Flash, PMODs
1.0V FPGA Core IC10: LTC3633 2A/ 0.2 to 1.3A
1.8V FPGA Auxiliary and Ram IC11: LTC3621 300mA/ 0.05 to 0.15A
Table 2. Basys 3 power supplies.

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Basys 3™ FPGA Board Reference Manual

2 FPGA Configuration
After power-on, the Artix-7 FPGA must be configured (or programmed) before it can perform any functions. You
can configure the FPGA in one of three ways:

1. A PC can use the Digilent USB-JTAG circuitry (portJ4, labeled "PROG") to program the FPGA any time the
power is on.
2. A file stored in the nonvolatile serial (SPI) flash device can be transferred to the FPGA using the SPI port.
3. A programming file can be transferred from a USB memory stick attached to the USB HID port.

Figure 3 shows the different options available for configuring the FPGA. An on-board "mode" jumper (JP1) selects
between the programming modes.

USB-JTAG/UART Port
Micro-AB USB USB
Connector (J4) Controller SPI SPI Quad mode
Port Flash
JTAG
Port
1x6 JTAG
6-pin JTAG Header
Artix-7 Mode (JP1)
Header (J5) JP1
M0
M2 SPI Flash
M1

JTAG
Done
Type A USB Host 2
PIC24 Serial
Connector (J2) Prog USB
Prog. Port

Programming Mode

Figure 3. Basys 3 configuration options.

The FPGA configuration data is stored in files called bitstreams that have the .bit file extension. The Vivado
software from Xilinx can create bitstreams from VHDL, Verilog®, or schematic-based source files.

Bitstreams are stored in SRAM-based memory cells within the FPGA. This data defines the FPGA's logic functions
and circuit connections, and it remains valid until it is erased by removing board power, by pressing the reset
button attached to the PROG input, or by writing a new configuration file using the JTAG port.

An Artix-7 35T bitstream is typically 17,536,096 bits and can take a long time to transfer. The time it takes to
program the Basys 3 can be decreased by compressing the bitstream before programming, and then allowing the
FPGA to decompress the bitsream itself during configuration. Depending on design complexity, compression ratios
of 10x can be achieved. Bitstream compression can be enabled within the Xilinx Tools (Vivado) to occur during
generation. For instructions on how to do this, consult the Xilinx documentation for the toolset being used.

After being successfully programmed, the FPGA will cause the "DONE" LED to illuminate. Pressing the "PROG"
button at any time will reset the configuration memory in the FPGA. After being reset, the FPGA will immediately
attempt to reprogram itself from whatever method has been selected by the programming mode jumper.

The following sections provide greater detail about programming the Basys 3 using the different methods
available.

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