Basys 3™ FPGA Board Reference Manual

ESC F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12

76 05 06 04 0C 03 0B 83 0A 01 09 78 07

`~ 1! 2@ 3# 4$ 5% 6^ 7& 8* 9( 0) -_ =+ BackSpace
0E 16 1E 26 25 2E 36 3D 3E 46 45 4E 55 66
TAB Q W E R T Y U I O P [{ ]} \|
0D 15 1D 24 2D 2C 35 3C 43 44 4D 54 5B 5D
Caps Lock A S D F G H J K L ;: '" Enter
58 1C 1B 23 2B 34 33 3B 42 4B 4C 52 5A

Shift Z X C V B N M ,< >. /? Shift

12 1Z 22 21 2A 32 31 3A 41 49 4A 59

Ctrl Alt Space Alt Ctrl

14 11 29 E0 11 E0 14

Figure 9. Keyboard scan codes.

A host device can also send data to the keyboard. Table 3 shows a list of some common commands a host might
send.

The keyboard can send data to the host only when both the data and clock lines are high (or idle). Because the
host is the bus master, the keyboard must check to see whether the host is sending data before driving the bus. To
facilitate this, the clock line is used as a "clear to send" signal. If the host drives the clock line low, the keyboard
must not send any data until the clock is released. The keyboard sends data to the host in 11-bit words that
contain a '0' start bit, followed by 8-bits of scan code (LSB first), followed by an odd parity bit, and terminated with
a '1' stop bit. The keyboard generates 11 clock transitions (at 20 to 30 KHz) when the data is sent, and data is valid
on the falling edge of the clock.

Command Action
Set Num Lock, Caps Lock, and Scroll Lock LEDs. Keyboard returns FA after receiving ED, then
ED host sends a byte to set LED status: bit 0 sets Scroll Lock, bit 1 sets Num Lock, and bit 2 sets
Caps lock. Bits 3 to 7 are ignored.
EE Echo (test). Keyboard returns EE after receiving EE.
Set scan code repeat rate. Keyboard returns F3 on receiving FA, then host sends second byte
F3
to set the repeat rate.
FE Resend. FE directs keyboard to re-send most recent scan code.
FF Reset. Resets the keyboard.
Table 3. Keyboard commands.

6.3 Mouse
Once entered in stream mode and data reporting has been enabled, the mouse outputs a clock and data signal
when it is moved. Otherwise, these signals remain at logic '1.' Each time the mouse is moved, three 11-bit words
are sent from the mouse to the host device, as shown in Fig. 10. Each of the 11-bit words contains a '0' start bit,
followed by 8 bits of data (LSB first), followed by an odd parity bit, and terminated with a '1' stop bit. Thus, each
data transmission contains 33 bits, where bits 0, 11, and 22 are '0' start bits, and bits 11, 21, and 33 are '1' stop
bits. The three 8-bit data fields contain movement data as shown in the Fig. 10. Data is valid at the falling edge of
the clock, and the clock period is 20 to 30 KHz.

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Basys 3™ FPGA Board Reference Manual

The mouse assumes a relative coordinate system wherein moving the mouse to the right generates a positive
number in the X field, and moving to the left generates a negative number. Likewise, moving the mouse up
generates a positive number in the Y field, and moving down represents a negative number (the XS and YS bits in
the status byte are the sign bits – a '1' indicates a negative number). The magnitude of the X and Y numbers
represent the rate of mouse movement; the larger the number, the faster the mouse is moving (the XV and YV
bits in the status byte are movement overflow indicators – a '1' means overflow has occurred). If the mouse moves
continuously, the 33-bit transmissions are repeated every 50ms or so. The L and R fields in the status byte indicate
Left and Right button presses (a '1' indicates that the button is being pressed).

Mouse status byte X direction byte Y direction byte

1 0 L R 0 1 XS YS XY YY P 1 0 X0 X1 X2 X3 X4 X5 X6 X7 P 1 0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 P 1

Start bit Stop bit Start bit Stop bit Start bit Stop bit
Idle state Idle state

Figure 10. Mouse data format.

The microcontroller also supports Microsoft® IntelliMouse®-type extensions for reporting back a third axis
representing the mouse wheel, as shown in Table 4.

Command Action
Set stream mode. The mouse responds with "acknowledge" (0xFA) then resets its movement
EA
counters and enters stream mode.
Enable data reporting. The mouse responds with "acknowledge" (0xFA) then enables data
F4 reporting and resets its movement counters. This command only affects behavior in stream
mode. Once issued, mouse movement will automatically generate a data packet.
Disable data reporting. The mouse responds with "acknowledge" (0xFA) then disables data
F5
reporting and resets its movement counters.
Set mouse sample rate. The mouse responds with "acknowledge" (0xFA) then reads one more
F3 byte from the host. This byte is then saved as the new sample rate, and a new "acknowledge"
packet is issued.
FE Resend. FE directs mouse to re-send last packet.
FF Reset. The mouse responds with "acknowledge" (0xFA) then enters reset mode.
Table 4. Microsoft Intellimouse-type extensions, commands, and actions.

7 VGA Port
NOTE: A helpful way to understand the way that VGA signals are transmitted is to understand the method of which
CRT (Cathode Ray Tubes) function for displaying images. Although the technology may seem outdated, it is from
this legacy that many of the signal names and timings have originated.

The Basys 3 board uses 14 FPGA signals to create a VGA port with 4-bits per color and the two standard sync
signals (HS – Horizontal Sync, and VS – Vertical Sync). The color signals use resistor-divider circuits that work in
conjunction with the 75 ohm termination resistance of the VGA display to create 16 signal levels each on the red,
green, and blue VGA signals. This circuit, shown in Fig. 11, produces video color signals that proceed in equal
increments between 0V (fully off) and 0.7V (fully on). Using this circuit, 4096 different colors can be displayed, one
for each unique 12-bit pattern. A video controller circuit must be created in the FPGA to drive the sync and color
signals with the correct timing in order to produce a working display system.

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Basys 3™ FPGA Board Reference Manual

Pin 1: Red Pin 5: GND

5 1 Pin 2: Grn Pin 6: Red GND
10 6 Pin 3: Blue Pin 7: Grn GND
Pin 13: HS Pin 8: Blu GND
15 11 Pin 14: VS Pin 10: Sync GND

RED0 4KW
G19
RED1 2KW
H19
RED2 1KW
J19
RED3 510W
N19
GRN0 4KW
J17
GRN1 2KW RED
H17
GRN2 1KW GRN
G17
GRN3 510W BLU
D17
BLU0 4KW
N18
BLU1 2KW
L18 HS
BLU2 1KW
K18 VS
BLU3 510W
J18 HD-DB15

HSYNC 100W
P19
VSYNC 100W
R19
Artix-7

7.1 VGA System Timing

VGA signal timings are specified, published, copyrighted, and sold by the VESA® organization (www.vesa.org). The
following VGA system timing information is provided as an example of how a VGA monitor might be driven in 640
by 480 mode.

NOTE: For more precise information, or for information on other VGA frequencies, refer to documentation
available at the VESA website.

CRT-based VGA displays use amplitude-modulated moving electron beams (or cathode rays) to display information
on a phosphor-coated screen. LCD displays use an array of switches that can impose a voltage across a small
amount of liquid crystal, thereby changing light permittivity through the crystal on a pixel-by-pixel basis. Although
the following description is limited to CRT displays, LCD displays have evolved to use the same signal timings as
CRT displays (so the "signals" discussion below pertains to both CRTs and LCDs). Color CRT displays use three
electron beams (one for red, one for blue, and one for green) to energize the phosphor that coats the inner side of
the display end of a cathode ray tube (see Fig. 12).

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Basys 3™ FPGA Board Reference Manual

Anode (entire screen)

Cathode ray tube

Deflection coils
Grid Electron guns
(Red, Blue, Green)

Cathode ray

R,G,B signals
(to guns)

VGA
cable

High voltage deflection grid gun

supply (>20kV) control control control

Figure 12. Color CRT display.

Electron beams emanate from "electron guns" which are finely-pointed heated cathodes placed in close proximity
to a positively charged annular plate called a "grid." The electrostatic force imposed by the grid pulls rays of
energized electrons from the cathodes, and those rays are fed by the current that flows into the cathodes. These
particle rays are initially accelerated towards the grid, but they soon fall under the influence of the much larger
electrostatic force that results from the entire phosphor-coated display surface of the CRT being charged to 20kV
(or more). The rays are focused to a fine beam as they pass through the center of the grids, and then they
accelerate to impact on the phosphor-coated display surface. The phosphor surface glows brightly at the impact
point, and it continues to glow for several hundred microseconds after the beam is removed. The larger the
current fed into the cathode, the brighter the phosphor will glow.

Between the grid and the display surface, the beam passes through the neck of the CRT where two coils of wire
produce orthogonal electromagnetic fields. Because cathode rays are composed of charged particles (electrons),
they can be deflected by these magnetic fields. Current waveforms are passed through the coils to produce
magnetic fields that interact with the cathode rays and cause them to transverse the display surface in a "raster"
pattern, horizontally from left to right and vertically from top to bottom, as shown in Fig. 13. As the cathode ray
moves over the surface of the display, the current sent to the electron guns can be increased or decreased to
change the brightness of the display at the cathode ray impact point.

Information is only displayed when the beam is moving in the "forward" direction (left to right and top to bottom),
and not during the time the beam is reset back to the left or top edge of the display. Much of the potential display
time is therefore lost in "blanking" periods when the beam is reset and stabilized to begin a new horizontal or
vertical display pass. The size of the beams, the frequency at which the beam can be traced across the display, and
the frequency at which the electron beam can be modulated determine the display resolution.

Modern VGA displays can accommodate different resolutions, and a VGA controller circuit dictates the resolution
by producing timing signals to control the raster patterns. The controller must produce synchronizing pulses at
3.3V (or 5V) to set the frequency at which current flows through the deflection coils, and it must ensure that video
data is applied to the electron guns at the correct time. Raster video displays define a number of "rows" that
corresponds to the number of horizontal passes the cathode makes over the display area, and a number of
"columns" that corresponds to an area on each row that is assigned to one "picture element" or pixel. Typical
displays use from 240 to 1200 rows and from 320 to 1600 columns. The overall size of a display and the number of
rows and columns determines the size of each pixel.

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