International Journal of Intelligent Computing Research (IJICR), Volume 1, Issue 3, June 2010

Hardware Implementation of
BCH Error-Correcting Codes on a FPGA

Laurenţiu Mihai Ionescu Constantin Anton Ion Tutănescu

University of Piteşti University of Piteşti University of Piteşti
[email protected] [email protected] [email protected]

Alin Mazăre Gheorghe Şerban

University of Piteşti University of Piteşti
[email protected] [email protected]

Let
Abstract p(x) = p0 + p1x + p2x2 + … + pn-1xn-1 (1)

Our paper presents the prototyping of a BCH be a code polynomial with coefficients from GF(2).
(Bose, Chaudhuri, and Hocquenghem) encoder and If p(x) has α, α2, … , α2t as its roots, p(x) is divisible
decoder using a Field Programmable Gate Array by the minimal polynomials m1(x), m2(x), … ,m2t-
(FPGA) reconfigurable chip. The solutions 1(x). The generator polynomial g(x) of the t-error-

implemented on FPGA lead to a high calculation correcting BCH of length code words n = 2m - 1 and
rate using parallelization. We implemented the BCH rate codes k/n is the lowest degree polynomial over
code in a 3s400FG456 FPGA. In this GF(2) [2]. Thus, the generator polynomial of the
implementation we used 15 bit-size word code and code must be the least common multiple (LCM) of

g x   LCM m1 x , m2 x ,, m2t x  .

the results show that the circuits work quite well. these minimal polynomials:
(2)

In general, for any positive integer m  3 and

1. Introduction t  n / 2 , there is a binary BCH code with parameters
of code words length n = 2m - 1, number of parity-
Using error correcting control is very important check bits n  k  mt , and minimum distance
d 0  2t  1  d min . The designed distance of the
in modern communication system. BCH codes
(Bose, Chaudhuri, and Hocquenghem) are being
widely used in communication networks, computer code is d0 = 2t + 1.
networks, satellite communication, magnetic and The minimum distance d min could be larger than
optic storage systems. This paper presents the d0. Algorithm for designing BCH codes is:
prototyping of a BCH encoder and decoder using 1. Choose a primitive polynomial of degree m,
FPGA. and construct GF(2m).
BCH codes operate over finite fields or Galois
2. Find the minimal polynomial mi(x) of αi for
fields. BCH codes can be defined by two parameters
i = 1, 2, …, 2t.
that are: length of code words, n, and the number of
errors to be corrected, t. 3. Obtain g(x).
The BCH codes are a class of cycle codes whose 4. Determine k from n - k, which is the degree of
generator polynomial is product of distinct minimal g(x).

  GF 2m  is a root of the primitive polynomial

polynomials corresponding to α, α2, … , α2t, where 5. Find the minimum distance d min  2t  1 .

g(x)[1]. An irreducible polynomial g(x) of degree m Suppose that a code word t(x) is transmitted and
that because of the channel error e(x), and to receive
form of degree n, x n  1 for no n less than 2 m  1. In
is said to be primitive if only if it divides polynomial
the word code is:
r(x) = t(x) + e(x), (3)
fact, every binary primitive polynomial g(x) of
degree m is a factor of x 2 m  1  1 . where e(x) is the error pattern.

Let mi  x  be the minimal polynomial of αi.

If the correction power of code is t, then no more
than t coefficients of e(x) are nonzero. Suppose that

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International Journal of Intelligent Computing Research (IJICR), Volume 1, Issue 3, June 2010

l, 1  l  t , errors actually occur and they happen in microprocessors. Even if FPGA cannot be
programmable while operation, they can be

e x    x j
unknown locations j1, j2, … , jl, that is

0  j  n  1 .
l configured anytime is needed, having a structure
(4)
based on RAM programmable machines, as we see
 1
in Figure 1. On the other hand, they allow parallel
Since α, α2, … , α2t are roots of each transmission structures implementation, with response time less
word codes, t(αi) = 0, for 1  i  2t . Then, than a system with microprocessor.
r(αi) = e(αi), i = 1, 2, …, 2t.
The decoding of received BCH word codes
requires successive computational processed
performed over GF(2m) to be executed. These
processes are the syndrome computations, error-
locator polynomial determination.
The first step in decoding a t-error-correction
BCH codes is to compute the 2t syndrome
components s1, s2,…, s2t. These syndrome
components may be obtained by substituting the
field elements α, α2, … , α2t into the received
polynomial r(x). Thus, the ith component of the

Si = r(αi) = e(αi), 1  i  2t ,
syndrome is
(5)
from which we see that the syndrome S depends

The error-locator polynomial  x  can be:

only on the error polynomial e(x).

 x    0   1 x     l x l if l  t ,
Figure 1. FPGA internal structure - block diagram
(6)
These features are used in our implementation
 x   1  1 x 1   2 x 1   l x 
which is equivalent with: which justifies the use of FPGA. Thus, we desire to
(7) implement an error correction circuit with enough
Let's write    jl for simplicity. Its coefficients
flexibility to can be used, with small changes, to
operate with different values of the communication
and the error-locator number are related by the system parameters such as the message bits number
0  1
following set of equations: or the word ode size.

1  1  2    l
Therefore, we design modularly the entire
hardware implementation, as we will describe in the
 2  1 2   2  3     l 1 l (8) following sections. The change of a parameter, such
……. as message size, goes to addition of new blocks with
 l  1 2  l
same internal structure, addition which is possible
by FPGA reconfigurable feature.
Also, we intend to build a communication system
2. Field Programmable Gates Array with real time response. Thus, when the message is
(FPGA) transmitted from the computer to communication
channel, we need a quick computation of control
Field-Programmable Gate Arrays (FPGAs) have sum.
become one of the key digital circuit implementation Secondly, to receiver, when the data package
media over the last decade [3]. One bit patterns will (word code) is received is needed a fast detection of
produce operational circuits and can be used in errors. All those are possible with the
many areas like the communication systems. implementation of structures which operate in
Our hardware scheme is based on polynomial parallel mode and with small propagation times,
generator for errors detection and correction. close to ASIC’s.
FPGA circuits represent a compromise between
circuits with microprocessor and ASIC (Application
Specific Integrated Circuits) [4].
First, they present flexibility in programming,
called here reconfiguration, which is a feature for

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International Journal of Intelligent Computing Research (IJICR), Volume 1, Issue 3, June 2010

3. Description of errors detection and check sum which is added to the message resulting
correction system the word code. This is the data package which is
transmitted to communication channel.
The system proposed in this paper is based on the To receiver, the entire word code is received and
use of reconfigurable FPGA circuits for hardware is divided to generator polynomial. If the remainder
implementation of error detection and correction of division is 0 then we don’t have error in the
algorithms. Error detection and correction is based message. Else, there are errors in the message and
on the algorithm presented in section 1. To the by a decoder we indentify wrong bits in the message
transmitter it is computed the remainder of division and correct them.
between message polynomial multiply with power The block diagram of the system is presented in
of 2 for check sum polynomial size and the Figure 2.
generator polynomial. This remainder represent

Figure 2. Communication system with FPGA implemented detection and correction errors algorithms

The communication is made between two division. Why we proceed in this way? Because all
computers. The algorithm of error detection and the communication performed at this time are serial
correction run to a FPGA circuit connected to the communications (USB, Ethernet or wireless). When
computer instead to run as a software application in we receive serial data bits, we have already done
computer. Thus, it is obtained a very small response some computations, in same time with the reception,
time, compare with response time of computer and to decrease whole computation time of the check
the computer can configure the FPGA when is sum. We name this computation (which is
desired the change of parameters of communication performed in the same time with serial reception of
system. On both FPGA circuits connected to the the data) serial computation and the hardware
computers, either transmitter computer or receiver module which implements it - serial computation
computer, we have implemented a coder and a module.
decoder to allow a bidirectional communication. Note that the operation which is made to encoder
While a computer transmits the other receive. is illustrated in the expression bellow, for binary

M  2deg S
representation of polynomials:

S
3.1. Transmitter module
G
The FPGA implemented transmitter system
contains first a remainder (control sum) computing where: M is message polynomial, G is generator
circuit, the control sum that will be attached to the polynomial, degS is order of check sum polynomial,
message. The remainder computing circuit is based and S is check sum polynomial.
on hardware implementation of the polynomial To the end of message M reception, the division
division algorithm, with block diagram presented in M/G was performed. Next, the result of the serial
the Figure 3 a). computation must be multiplied with 2 at degS
As we show in [5], serial computing module power and divided to G. All these operations must
allows starting of the division algorithm even when be executed as quickly possible to obtain check sum
first bit is received from computer! Next, each S. This will be added to M which is already
received bit means a step in the division algorithm transmitted to communication channel.
Thus, when the entire message is received from the To execute very fast this computation we built
computer, we have already a partial result from the modules which operate in parallel, to get a small

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International Journal of Intelligent Computing Research (IJICR), Volume 1, Issue 3, June 2010

response time. The parallel computing module by the response time of the parallel module. With
consists of more cells which execute each a task green are represented bits involved in or obtained
from the division algorithm. from parallel computation.

3.2. Receiver module

To receiver module, the system contains the

detection and correction parts. The hardware block
diagram of this system is presented in the Figure 3 b.
The serial computing module is the same as to
the encoder. This executes a division between word
code polynomial (message and check sum) and
generator.
The division is performed using a serial
a) algorithm, as to the encoder, while the data packet is
received from communication channel. After the
division results a remainder. Depending of its value,
the wrong bits (their positions) are identified in data
packet.
The erroneous bits detector is practically a
decoder, with a bit string output with size of data
packet size. It takes the remainder and set high 1
logic output bit which correspond with wrong bit
positions. If the remainder is 0 then all bits are
correct so the output string from detector is 0. Else,
detector convert remainder value in a bit string with
b) 1 to the positions where are wrong bits.
Figure 3. Encoder (a) and decoder (b) circuit The string with wrong bits positions is
transmitted to the errors corrector module. It
The data flow for the encoder is presented in consists in a network of Boolean XOR circuits
Figure 4 a. In the top of this figure the raw string which can invert from original message bits which
received from the computer (only message string M) correspond to 1 position from detector output.
is presented. In bottom side, final string (which is In Figure 4 b, the data flow to the reception is
transmitted to communication channel) is presented. illustrated. With yellow are represented message bits
The two strings are represented in relation with and with green check sum bits. Both the message
time. With yellow are illustrated the bits which will and check sum (word code) are serial processed.
be involved in serial computation. When a message To apply correction is necessary to save the
bit is received from computer it will be transmitted entire message. This is made in a shift/parallel
immediately to communication channel, via a register with the dimension of the message (see
selection circuit (see Figure 3). Figure 3 b).
After entire message is transmitted, follow Each received bit is saved here when is received.
multiplication with 2degS and the final steps in Next, for correction, information from the register
division. Both operations are performed using reaches into a network of XOR gates with the binary
parallel computation module. First, to partial result string provided by the memory with error bit
is appending a number of 0 equal with check sum position.
polynomial order. This is equivalent to polynomial
multiplication of the message polynomial with the
remainder degree. Then the final division is
performed using parallel cells.
To attach the check sum to the message and sent
it to communication channel we use a parallel -
serial register which take parallel output from
parallel computing module and convert it in serial a)
string which is selected to be transmitted by
selection circuit (Figure 3). Here a small delay
appears (with red color in Figure 4) which is given

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International Journal of Intelligent Computing Research (IJICR), Volume 1, Issue 3, June 2010

extension pins. A functional schematics of the

experimental module is presented in Figure 6.

b)
Figure 4. Data flow to the encoder (a) and decoder (b)

The experiments described in this paper refer to

identify and correcting one single bit error, but they
can be extended by storing others remainder/bit
error pair and increasing the remainder degree.

4. Experimental results Figure 6. Experimental system operation diagram

Experimental system is presented in Figure 2 as From the transmitter computer is sent a message.
block diagram. Both the encoder and decoder are This arrives, via RS232 interface, to the FPGA
integrated inside an FPGA chip Xilinx Spartan 3 board. In FPGA is the encoder which computes the
XC3S400. check sum and send it, attached to the message, to
This is a very cheap family of FPGA that can be communication channel. The communication
used in commercial applications. In Figure 5 there between encoder and decoder (FPGA boards) is
are illustrated pictures of the experimental system. made using a two wire serial interface, emulated on
two I/O pins.
To the receiver is taken the word code and then is
computed the error inside message, as we presented
in the previous sections. The corrected message is
transmitted to the receiver computer, via RS232.
The serial interfaces are used only to test encoder
and decoder systems inside a complete
communication system. They can be replaced with
any serial communication environment. To the
evaluation of communication speed, are take into
account only response times from encoder and
decoder, without the propagation time through the
serial interface.
The evaluation of the system presented in this
paper is performed for a message size of 11 bits and
a generator of 4 degree:
Figure 5. Pictures of the experimental system g(x) = x4 + x + 1 (10)

In the top side of the figure we can see the The remainder is 3 degree and is represented as a
computers used as transmitter and receiver and the 4-bits size binary string. Therefore, the size of a
FPGA boards where are implemented the encoder word code is 15 bits.
and decoder. In bottom side of the figure are After the hardware synthesis of the transmitter
illustrated the computer and attached board and two system, the following report was obtained:
boards while communicating using RS 232 interface
Device utilization summary:
with computers and a 2 wire interface as ----------------------------------
communication channel. Selected Device : 3s400fg456-4
The FPGA circuit is integrated inside a Number of Slices: 11 out of 3584 0%
development board (Altium Live Design). The board Number of Slice Flip Flops: 16 out of 7168 0%
Number of 4 input LUTs: 14 out of 7168 0%
already contains a RS232 converter to communicate Number of bonded IOBs: 8 out of 264 3%
with PC and more general purpose Input/Output Number of GCLKs: 1 out of 8 12%

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International Journal of Intelligent Computing Research (IJICR), Volume 1, Issue 3, June 2010

Timing constraint: Default period analysis for Clock 'clk' chip. We implemented the BCH code in a
Clock period: 4.919ns (frequency: 203.293MHz)
3s400FG456 FPGA.
Total number of paths / destination ports: 42 / 14
In this implementation we used 15 bits-size
To the receiver system, it is obtained (after word code and the results show that the circuits
synthesis): work quite well. The FPGA implementation of BCH
codes leads to a high calculation rate using
Device utilization summary: parallelization. So, we reduce the computation time
----------------------------------
Selected Device : 3s400fg456-4
of control sum at transmission and detection and
Number of Slices: 23 out of 3584 0% correction error to receiver.
Number of Slice Flip Flops: 31 out of 7168 0% Our solution can be used for data transmission in
Number of 4 input LUTs: 36 out of 7168 0% real time application. The difference between
Number of bonded IOBs: 18 out of 264 6%
Number of GCLKs: 1 out of 8 12%
Thardware and Tsoftware increases with the size of word
Timing constraint: Default period analysis for Clock 'clk' code. A future research direction is to extend our
Clock period: 4.919ns (frequency: 203.293MHz) system in order to correct more error bits for larger
Total number of paths / destination ports: 57 / 29 word code.
As can be seen from the two reports, the chip 6. References
area occupied in a 3s400FG456 FPGA is very small.
Therefore, this systems can be integrated on the [1] M.Y. Rhee - “Error Correcting Coding Theory”,
same chip with others modules. McGraw-Hill, Singapore, 1989.
Besides the high degree of integration, another [2] S. Lin, and D.J. Costello Jr. - “Error Control Coding”,
major advantage is the decrease of computing time Prentice-Hall, New Jersey, 1983.
over a software solution. [3] J. Rose S.D. Brown, R.J. Francis – “Field
In the Table 1 there are compared the Programmable Gate Arrays”, Kluwer Academic
computation time of the hardware system and the Publishers, 1992.
estimated response time, when the detection and [4] T. Fogarty, J. Miller, and P. Thompson - “Evolving
correction algorithm runs on a computer with a digital logic circuits on Xilinx 6000 family FPGAs,” in
processor which work at 2,8 GHz clock frequency. Soft Computing in Engineering Design and
Manufacturing, P. Chawdhry, R. Roy, and R. Pant (eds.),
Table 1. A comparison between hardware and software Springer: Berlin, 1998, pp. 299–305.
processing at transmitter. [5] C. Anton, L. Ionescu, I. Tutănescu, A. Mazăre, G.
k n vt Thardware Tsoftware Şerban - “FPGA-implemented CRC Algorithm”, Interna-
tional Conference “Applied Electronics”, 9-10 September
11 15 0,73 73,785 ns 80,3 ns
2009, p. 25-30, ISSN 1803-7232, ISBN 978-80-7043-781-
0, IEEE Catalog Number CFP0969A-PRT, University of
To receiver, the computation speed of the system West Bohemia, Pilsen, Czech Republic, 2009.
compared with software implementation is higher,
because to the hardware system a parallel module is
used to correct the error.

Table 2. A comparison between hardware and

software processing at receiver
k n vt Thardware Tsoftware
11 15 0,73 73,785 ns 107,1 ns

5. Conclusion
The usage of error correcting control is very
important in a modern communication system.
The BCH codes are being widely used in
communication networks, computer networks,
satellite communication, magnetic and optical
storage systems.
We have presented in this paper the prototyping
of a BCH encoder and decoder using a Field
Programmable Gate Array (FPGA) reconfigurable

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