Introduction of Microprocessor

A microprocessor is a programmable electronic chip, often referred to as the "brain" of a

computer or other device, that performs arithmetic, logical, and control operations. It's a key
component in most electronic devices, from computers to smartphones, and is essentially a
central processing unit (CPU) on a single chip.
Key Characteristics:
Programmable:
Microprocessors execute instructions stored in memory, allowing them to perform a wide range
of tasks.
Single Chip:
They are fabricated on a single integrated circuit (IC) or chip, making them compact and
efficient.
CPU Function:
They act as the central processing unit, controlling the flow of data and executing instructions.
Versatile:
They are used in various applications, from personal computers to embedded systems in
appliances and vehicles.
How it Works:
Fetch: The microprocessor retrieves instructions from memory.
Decode: It interprets the instructions to understand what needs to be done.
Execute: It performs the operations specified by the instructions, such as arithmetic, logical, or
control tasks.
Key Components within a Microprocessor:
Arithmetic Logic Unit (ALU): Performs mathematical and logical calculations.
Control Unit: Manages the flow of data and instructions.
Registers: Temporary storage locations for data and instructions.

Comparison of 8 bit ,16 bit and 32 bit microprocessors :

8-bit, 16-bit, and 32-bit microprocessors differ primarily in their data processing capabilities and
instruction set architecture. 8-bit processors handle data in 8-bit chunks, 16-bit processors handle
data in 16-bit chunks, and 32-bit processors handle data in 32-bit chunks. This difference directly
impacts performance, memory handling, and the complexity of applications they can support.
 8 bit microprocessor 16 bit microprocessor 32 bit microprocessor
• Data Processing: Process Data Processing: Process • Data Processing: Process
data in 8-bit units (a byte). data in 16-bit units. data in 32-bit units.
• Examples: Intel x86-64,
ARM Cortex-M3/M4/M7.

• Applications: Suitable for Applications: More powerful Applications: Used in

simple, low-power than 8-bit, suitable for modern computers,
applications, such as basic applications requiring more smartphones, and other
control systems, embedded processing power and devices requiring high
systems, and early game memory, such as early performance, large memory,
consoles. personal computers, complex and complex instructions,
embedded systems, and some such as graphics processing,
audio/video applications audio/video editing, and
scientific computing
• Memory: Can typically Memory: Can address larger Memory: Can address much
address a smaller amount of memory spaces (e.g., 1MB). larger memory spaces (e.g.,
memory (e.g., 64KB). 4GB or more
Examples: Intel 8085, 8051 Examples: Intel 8086, 8096. Examples: Intel x86-64,
microcontrollers ARM Cortex-M3/M4/M7

System Bus: This network of wires or electronic pathways is called the 'Bus'.
A system bus is a single computer bus that connects the major components of a computer
system.
It combines the functions of a data bus to carry information, an address bus to determine where it
should be sent, and a control bus to determine its operation.
The technique was developed to reduce costs and improve modularity.
Address Bus:
It is a group of wires or lines that are used to transfer the addresses of Memory or I/O devices.
It is unidirectional.
The width of the address bus corresponds to the maximum addressing capacity of the bus, or the
largest address within memory that the bus can work with.
The addresses are transferred in binary format, with each line of the address bus carrying a single
binary digit.
Therefore the maximum address capacity is equal to two to the power of the number of lines
present (2^lines)
Data Bus:
It is used to transfer data within Microprocessor and Memory/Input or Output devices.
It is bidirectional as Microprocessor requires sending or receiving data.
Each wire is used for the transfer of signals corresponding to a single bit of binary data.
As such, a greater width allows greater amounts of data to be transferred at the same time.
Control Bus:
Microprocessor uses control bus to process data, i.e. what to do with the selected memory
location.
Some control signals are Read, Write and Opcode fetch etc.
Various operations are performed by microprocessor with the help of control bus.
This is a dedicated bus, because all timing signals are generated according to control signal.
Architecture of 8086:

The architecture of the 8086 microprocessor is based on a complex instruction set computer
(CISC) architecture, which means that it supports a wide range of instructions, many of which
can perform multiple operations in a single instruction. The 8086 microprocessor has a 20-bit
address bus, which can address up to 1 MB of memory, and a 16-bit data bus, which can
transfer data between the microprocessor and memory or I/O devices.
The 8086 microprocessor has a segmented memory architecture, which means that memory is
divided into segments that are addressed using both a segment register and an offset. The
segment register points to the start of a segment, while the offset specifies the location of a
specific byte within the segment. This allows the 8086 microprocessor to access large amounts
of memory, while still using a 16-bit data bus.
The 8086 microprocessor has two main execution units: the execution unit (EU) and the bus
interface unit (BIU). The BIU is responsible for fetching instructions from memory and
decoding them, while the EU executes the instructions. The BIU also manages data transfer
between the microprocessor and memory or I/O devices.
The 8086 microprocessor has a rich set of registers, including general-purpose registers,
segment registers, and special registers. The general-purpose registers can be used to store data
and perform arithmetic and logical operations, while the segment registers are used to address
memory segments. The special registers include the flags register, which stores status
information about the result of the previous operation, and the instruction pointer (IP), which
points to the next instruction to be executed.
A Microprocessor is an Integrated Circuit with all the functions of a CPU. However, it cannot
be used stand-alone since unlike a microcontroller it has No memory or peripherals 8086 does
not have a RAM or ROM inside it. However, it has internal registers for storing intermediate
and final results and interfaces with memory located outside it through the System Bus.

In the case of 8086, it is a 16-bit Integer processor in a 40-pin, Dual Inline Packaged IC.

The size of the internal registers (present within the chip) indicates how much information the
processor can operate on at a time (in this case 16-bit registers) and how it moves data around
internally within the chip, sometimes also referred to as the internal data bus.

8086 provides the programmer with 14 internal registers, each of 16 bits or 2 bytes wide. The
main advantage of the 8086 microprocessor is that it supports Pipelining.
Memory segmentation:
• In order to increase execution speed and fetching speed, 8086 segments the memory.
• Its 20-bit address bus can address 1MB of memory, it segments it into 16 64kB segments.
• 8086 works only with four 64KB segments within the whole 1MB memory.
The internal architecture of Intel 8086 is divided into 2 units: The Bus Interface Unit (BIU),
and The Execution Unit (EU). These are explained as following below.

1. The Bus Interface Unit (BIU):

It provides the interface of 8086 to external memory and I/O devices via the System Bus. It
performs various machine cycles such as memory read, I/O read, etc. to transfer data between
Memory and I/O devices
BIU performs the following functions are as follows:
• It generates the 20-bit physical address for memory access.
• It fetches instructions from the memory.
• It transfers data to and from the memory and I/O.
• Maintains the 6-byte pre-fetch instruction queue(supports pipelining).

BIU mainly contains the 4 Segment registers, the Instruction Pointer, a pre-fetch queue, and
an Address Generation Circuit
Instruction Pointer (IP):
• It is a 16-bit register. It holds offset of the next instructions in the Code Segment.
• IP is incremented after every instruction byte is fetched.
• IP gets a new value whenever a branch instruction occurs.
• CS is multiplied by 10H to give the 20-bit physical address of the Code Segment.
• The address of the next instruction is calculated by using the formula CS x 10H + IP.
Example:
CS = 4321H IP = 1000H
then CS x 10H = 43210H + offset = 44210H
Here Offset = Instruction Pointer(IP)
This is the address of the next instruction
Code Segment register: (16 Bit register): CS holds the base address for the Code Segment. All
programs are stored in the Code Segment and accessed via the IP.
Data Segment register: (16 Bit register): DS holds the base address for the Data Segment.

Stack Segment register: (16 Bit register): SS holds the base address for the Stack Segment.

Extra Segment register: (16 Bit register): ES holds the base address for the Extra Segment.
Address Generation Circuit:
• The BIU has a Physical Address Generation Circuit.
• It generates the 20-bit physical address using Segment and Offset addresses using the
formula:
• In Bus Interface Unit (BIU) the circuit shown by the Σ symbol is responsible for the
calculation unit which is used to calculate the physical address of an instruction in memory.
6 Byte Pre-fetch Queue:
• It is a 6-byte queue (FIFO).
• Fetching the next instruction (by BIU from CS) while executing the current instruction is
called pipelining.
• Gets flushed whenever a branch instruction occurs.
• The pre-Fetch queue is of 6-Bytes only because the maximum size of instruction that can
have in 8086 is 6 bytes. Hence to cover up all operands and data fields of maximum size
instruction in 8086 Microprocessor there is a Pre-Fetch queue is 6 Bytes.
• The pre-Fetch queue is connected with the control unit which is responsible for decoding op-
code and operands and telling the execution unit what to do with the help of timing and
control signals.
• The pre-Fetch queue is responsible for pipelining and because of that 8086 microprocessor
is called fetch, decode, execute type microprocessor. Since there are always instructions
present for decoding and execution in this queue the speed of execution in the microprocessor
is gradually increased.
• When there is a 2-byte space in the instruction pre-fetch queue then only the next
instruction will be pushed into the queue otherwise if only a 1-byte space is vacant then
there will not be any allocation in the queue. It will wait for a spacing of 2 bytes in subsequent
queue decoding operations.
• Instruction pre-fetch queue works in a sequential manner so if there is any branch condition
then in that situation pre-fetch queue fails. Hence to avoid chaos instruction queue is flushed
out when any branch or conditional jumps occur.

2.prefetch unit:
The Prefetch Unit in the 8086 microprocessor is a component responsible for fetching
instructions from memory and storing them in a queue. The prefetch unit allows the 8086 to
perform multiple instruction fetches in parallel, improving the overall performance of the
microprocessor.
The prefetch unit consists of a buffer and a program counter that are used to fetch instructions
from memory. The buffer stores the instructions that have been fetched and the program
counter keeps track of the memory location of the next instruction to be fetched. The prefetch
unit fetches several instructions ahead of the current instruction, allowing the 8086 to execute
instructions from the buffer rather than from memory.
This parallel processing of instruction fetches helps to reduce the wait time for memory access,
as the 8086 can continue to execute instructions from the buffer while it waits for memory
access to complete. This results in improved overall performance, as the 8086 is able to
execute more instructions in a given amount of time.
The prefetch unit is an important component of the 8086 microprocessor, as it allows the
microprocessor to work more efficiently and perform more instructions in a given amount of
time. This improved performance helps to ensure that the 8086 remains competitive in its
performance and capabilities, even as technology continues to advance.

The Execution Unit (EU):

The main components of the EU are General purpose registers, the ALU, Special purpose
registers, the Instruction Register and Instruction Decoder, and the Flag/Status Register.
1. Fetches instructions from the Queue in BIU, decodes, and executes arithmetic and logic
operations using the ALU.
2. Sends control signals for internal data transfer operations within the microprocessor.(Control
Unit)
3. Sends request signals to the BIU to access the external module.
4. It operates with respect to T-states (clock cycles) and not machine cycles.

8086 has four 16-bit general purpose registers AX, BX, CX, and DX which store intermediate
values during execution. Each of these has two 8-bit parts (higher and lower).
• AX register: (Combination of AL and AH Registers) : It holds operands and results
during multiplication and division operations. Also an accumulator during String
operations
• BX register: (Combination of BL and BH Registers): It holds the memory address
(offset address) in indirect addressing modes
• CX register: (Combination of CL and CH Registers): It holds the count for instructions
like a loop, rotates, shifts and string operations
• DX register: (Combination of DL and DH Registers): It is used with AX to hold 32-bit values
during multiplication and division

Arithmetic Logic Unit (16-bit): Performs 8 and 16-bit arithmetic and logic operations.
Special purpose registers (16-bit): Special purpose registers are called Offset registers also.
Which points to specific memory locations under each segment.
We can understand the concept of segments as Textbook pages. Suppose there are 10 chapters
in one textbook and each chapter takes exactly 100 pages. So the book will contain 1000 pages.
Now suppose we want to access page number 575 from the book then 500 will be the segment
base address which can be anything in the context of microprocessors like Code, Data, Stack,
and Extra Segment. So 500 will be segment registers that are present in Bus Interface Unit (BIU).
And 500 + 75 is called an offset register through which we can reach on specific page number
under a specific segment.
Hence 500 is the segment base address and 75 is an offset address or (Instruction Pointer, Stack
Pointer, Base Pointer, Source Index, Destination Index) any of the above according to their
segment implementation.
• Stack Pointer: Points to Stack top. Stack is in Stack Segment, used during instructions like
PUSH, POP, CALL, RET etc.
• Base Pointer: BP can hold the offset addresses of any location in the stack segment. It is
used to access random locations of the stack.
• Source Index: It holds offset address in Data Segment during string operations.
• Destination Index: It holds offset address in Extra Segment during string operations.
Instruction Register and Instruction Decoder:
The EU fetches an opcode from the queue into the instruction register. The instruction decoder
decodes it and sends the information to the control circuit for execution.

Flag/Status register (16 bits): It has 9 flags that help change or recognize the state of the
microprocessor.

6 Status flags:
1. Carry flag(CF)
2. Parity flag(PF)
3. Auxiliary carry flag(AF)
4. Zero flag(Z)
5. Sign flag(S)
6. Overflow flag (O)
Status flags are updated after every arithmetic and logic operation.

3 Control flags:
1. Trap flag(TF)
2. Interrupt flag(IF)
3. Direction flag(DF)
These flags can be set or reset using control instructions like CLC, STC, CLD, STD, CLI, STI,
etc. The Control flags are used to control certain operations.

4.Decode unit:
The Decode Unit in the 8086 microprocessor is a component that decodes the instructions that
have been fetched from memory. The decode unit takes the machine code instructions and
translates them into micro-operations that can be executed by the microprocessor's execution
unit.
The Decode Unit works in parallel with the Prefetch Unit, which fetches instructions from
memory and stores them in a queue. The Decode Unit reads the instructions from the queue
and translates them into micro-operations that can be executed by the microprocessor.
The Decode Unit is an important component of the 8086 microprocessor, as it allows the
microprocessor to execute instructions efficiently and accurately. The decode unit ensures that
the microprocessor can execute complex instructions, such as jump instructions and loop
instructions, by translating them into a series of simple micro-operations.
The Decode Unit is responsible for decoding instructions, performing register-to-register
operations, and performing memory-to-register operations. It also decodes conditional jumps,
calls, and returns, and performs data transfers between memory and registers.
The Decode Unit helps to improve the performance of the 8086 microprocessor by allowing it
to execute instructions quickly and accurately. This improved performance helps to ensure that
the 8086 remains competitive in its performance and capabilities, even as technology continues
to advance.

5.control unit :

The Control Unit in the 8086 microprocessor is a component that manages the overall
operation of the microprocessor. The control unit is responsible for controlling the flow of
instructions through the microprocessor and coordinating the activities of the other
components, including the Decode Unit, Execution Unit, and Prefetch Unit.
The Control Unit acts as the central coordinator for the microprocessor, directing the flow of
data and instructions and ensuring that the microprocessor operates correctly. It also monitors
the state of the microprocessor, ensuring that the correct sequence of operations is followed.
The Control Unit is responsible for fetching instructions from memory, decoding them,
executing them, and updating the microprocessor's state. It also handles interrupt requests and
performs system management tasks, such as power management and error handling.
The Control Unit is an essential component of the 8086 microprocessor, as it allows the
microprocessor to operate efficiently and accurately. The control unit ensures that the
microprocessor can execute complex instructions, such as jump instructions and loop
instructions, by coordinating the activities of the other components.
The Control Unit helps to improve the performance of the 8086 microprocessor by managing
the flow of instructions and data through the microprocessor, ensuring that the microprocessor
operates correctly and efficiently. This improved performance helps to ensure that the 8086
remains competitive in its performance and capabilities, even as technology continues to
advance.
The 8086 microprocessor uses three different buses to transfer data and instructions
between the microprocessor and other components in a computer system. These buses
are:

1.Address Bus: The address bus is used to send the memory address of the instruction or data
being read or written. The address bus is 16 bits wide, allowing the 8086 to address up to 64
kilobytes of memory.
2.Data Bus: The data bus is used to transfer data between the microprocessor and memory.
The data bus is 16 bits wide, allowing the 8086 to transfer 16-bit data words at a time.
3.Control Bus: The control bus is used to transfer control signals between the microprocessor
and other components in the computer system. The control bus is used to send signals such as
read, write, and interrupt requests, and to transfer status information between the
microprocessor and other components

Microprocessor - 8086 Pin Configuration:

8086 was the first 16-bit microprocessor available in 40-pin DIP (Dual Inline Package) chip
8086 Pin Diagram
Here is the pin diagram of 8086 microprocessor –
Power supply and frequency signals
It uses 5V DC supply at VCC pin 40, and uses ground at VSS pin 1 and 20 for its operation.
Clock signal
Clock signal is provided through Pin-19. It provides timing to the processor for operations. Its
frequency is different for different versions, i.e. 5MHz, 8MHz and 10MHz.
Address/data bus
AD0-AD15. These are 16 address/data bus. AD0-AD7 carries low order byte data and
AD8AD15 carries higher order byte data. During the first clock cycle, it carries 16-bit address
and after that it carries 16-bit data.
Address/status bus
A16-A19/S3-S6. These are the 4 address/status buses. During the first clock cycle, it carries 4-bit
address and later it carries status signals.
S7/BHE
BHE stands for Bus High Enable. It is available at pin 34 and used to indicate the transfer of data
using data bus D8-D15. This signal is low during the first clock cycle, thereafter it is active.
Read(RD¯¯¯¯¯¯¯¯RD¯)
It is available at pin 32 and is used to read signal for Read operation.
Ready
It is available at pin 22. It is an acknowledgement signal from I/O devices that data is transferred.
It is an active high signal. When it is high, it indicates that the device is ready to transfer data.
When it is low, it indicates wait state.
RESET
It is available at pin 21 and is used to restart the execution. It causes the processor to
immediately terminate its present activity. This signal is active high for the first 4 clock cycles to
RESET the microprocessor.
INTR
It is available at pin 18. It is an interrupt request signal, which is sampled during the last clock
cycle of each instruction to determine if the processor considered this as an interrupt or not.
NMI
It stands for non-maskable interrupt and is available at pin 17. It is an edge triggered input,
which causes an interrupt request to the microprocessor.
TEST¯¯¯¯¯¯¯¯¯¯¯¯¯¯TEST¯
This signal is like wait state and is available at pin 23. When this signal is high, then the
processor has to wait for IDLE state, else the execution continues.
MN/MX¯¯¯¯¯¯¯¯¯¯MX¯
It stands for Minimum/Maximum and is available at pin 33. It indicates what mode the processor
is to operate in; when it is high, it works in the minimum mode and vice-aversa.
INTA
It is an interrupt acknowledgement signal and id available at pin 24. When the microprocessor
receives this signal, it acknowledges the interrupt.
ALE
It stands for address enable latch and is available at pin 25. A positive pulse is generated each
time the processor begins any operation. This signal indicates the availability of a valid address
on the address/data lines.
DEN
It stands for Data Enable and is available at pin 26. It is used to enable Transreceiver 8286. The
transreceiver is a device used to separate data from the address/data bus.
DT/R
It stands for Data Transmit/Receive signal and is available at pin 27. It decides the direction of
data flow through the transreceiver. When it is high, data is transmitted out and vice-a-versa.
M/IO
This signal is used to distinguish between memory and I/O operations. When it is high, it
indicates I/O operation and when it is low indicates the memory operation. It is available at pin
28.
WR
It stands for write signal and is available at pin 29. It is used to write the data into the memory or
the output device depending on the status of M/IO signal.
HLDA
It stands for Hold Acknowledgement signal and is available at pin 30. This signal acknowledges
the HOLD signal.
HOLD
This signal indicates to the processor that external devices are requesting to access the
address/data buses. It is available at pin 31.
QS1 and QS0
These are queue status signals and are available at pin 24 and 25. These signals provide the status
of instruction queue. Their conditions are shown in the following table –

S2 S1 S0 Status

0 0 0 Interrupt acknowledgement

0 0 1 I/O Read

0 1 0 I/O Write

0 1 1 Halt

1 0 0 Opcode fetch

1 0 1 Memory read
 1 1 0 Memory write

1 1 1 Passive

LOCK
When this signal is active, it indicates to the other processors not to ask the CPU to leave the
system bus. It is activated using the LOCK prefix on any instruction and is available at pin 29.
RQ/GT1 and RQ/GT0
These are the Request/Grant signals used by the other processors requesting the CPU to release
the system bus. When the signal is received by CPU, then it sends acknowledgment. RQ/GT0
has a higher priority than RQ/GT1

8284 Clock Generator

8284 clock generator is an IC developed by Intel to provide clock frequency, ready and reset
signal to the 8086/8088 microprocessor. It is an 18 pin chip.
8284 produces the clock signal, synchronizes it with the ready and reset signal and provides it to
the microprocessor.

Functions of 8284

• It provides a stable clock to the processor.

• In the case of a multiprocessor system, it facilitates synchronization of
multiple clock signals.
• Provides resetting to the processor along with the clock signal.
 Reset Logic: −Initially the capacitor is uncharged. −When power is switched on, the RES signal
is at logic 0 (RESET signal is at logic 1). −The capacitor starts charging with time constant
(RC=10Kx10uF). −When the voltage across the capacitor becomes equal to the minimum High
voltage of the 8284 (2V), the RES signal goes to logic 1 (RESET signal goes to logic 0). −If the
Reset button is pressed, the capacitor is discharged through the switch. −When the Button is
released, the capacitor starts charging as before. −The diode is used to short circuit the resistor
during switch off, thus discharge the capacitor fast
Stack & stack memory:

In the 8086 microprocessor, the stack is a region of memory used for

temporary data storage, particularly for return addresses after subroutine calls
and interrupt handling. The Stack Segment (SS) register defines the segment
of memory allocated for the stack, and the Stack Pointer (SP) register keeps
track of the current top of the stack within that segment.

Stack Basics:

• LIFO Structure:
The stack operates on a Last-In, First-Out (LIFO) principle, meaning the last item placed on
the stack is the first one removed.
• Purpose:
It's used to store data temporarily, such as:
• Return addresses when calling subroutines or handling interrupts.
• Local variables within functions.
• Register values to be preserved and restored later.
• Memory Allocation:
The SS register determines the segment, and the SP register points to the top of the stack
within that segment.
Stack Pointer (SP):

• Purpose:
The SP register always points to the top of the stack.
• Decrementing/Incrementing:
When data is pushed onto the stack (using the PUSH instruction), the SP is decremented to
point to the new top of the stack. When data is popped off the stack (using
the POP instruction), the SP is incremented.
• Address Calculation:
The physical memory address of the stack location is calculated by combining the contents of
the SS and SP registers: SS * 16 + SP.
• Example:
If SS = 0x2000 and SP = 0x0010, the top of the stack is at memory address (0x2000 * 16) +
0x0010 = 0x20010.
Push and Pop Instructions:

• PUSH:
The PUSH instruction saves the contents of a register or a memory location onto the stack. The
SP is decremented before the data is written.
• POP:
The POP instruction retrieves data from the top of the stack and places it into a register or
memory location. The SP is incremented after the data is read.
Key Concepts:

• Stack Overflow:
If data is pushed onto the stack beyond the allocated segment, it results in a stack overflow,
potentially corrupting other data or code.