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DDCO Questions 2

The document outlines various tasks related to digital design and computer organization, including the construction and explanation of multiplexers and flip-flops, implementation of Boolean functions, and design of Verilog programs. It also covers basic operational concepts of computers, performance measurement, addressing modes, and instruction execution. Additionally, it includes calculations for processor performance and execution time based on given parameters.

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3 views2 pages

DDCO Questions 2

The document outlines various tasks related to digital design and computer organization, including the construction and explanation of multiplexers and flip-flops, implementation of Boolean functions, and design of Verilog programs. It also covers basic operational concepts of computers, performance measurement, addressing modes, and instruction execution. Additionally, it includes calculations for processor performance and execution time based on given parameters.

Uploaded by

mindyourownbusiness041
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Digital Design and Computer Organization

MODULE-2
1. Construct and explain a Quadruple two-to-one-line multiplexer with a neat diagram.
2. Implement the following Boolean function with 8:1 multiplexer and external gates:
𝐹(𝐴, 𝐵, 𝐶, 𝐷) = ∑(1,3,4,11,12,13,14,15).

3. Implement a full adder with two 4:1 multiplexers.


4. Design Verilog program to implement Different types of multiplexers like 2:1, 4:1 and 8:1.

5. Design Verilog program to implement Different types of Demultiplexers like 1:2, 1:4 and 1:8.

6. Construct a 16:1 multiplexer with two 8:1 and one 2:1 multiplexer. Use block diagrams.

7. An 8 :1 multiplexer has inputs A, B, and C connected to the selection inputs S2, S1, and S0,
respectively. The data inputs I0 through I7 are as follows:
I1= I2 = I7 = 0; I3= I5= 1; I0= I4= D ; and I6= D’.
Determine the Boolean function that the multiplexer implements.
8. What is the drawback of SR Latch? Explain which flipflops were developed to overcome this
drawback and how it is overcome?
9. Derive the characteristic equation for SR, JK, D and T flip flops from their respective truth
tables. Show that the characteristic equation for the complement output of a JK flip-flop is
𝑄(𝑡 + 1) = 𝐽′ 𝑄 ′ + 𝐾𝑄.
10. Illustrate the working of Negative edged D Flip flop with a neat diagram, truth table and circuit
symbol.
11. Design Verilog program for implementing various types of Flip-Flops such as SR, JK and D.

MODULE-3
1. Explain the basic operational concepts of a computer with a neat diagram.
2. Explain the Single-Bus architecture with a neat diagram. List the advantages and disadvantages
of the Single-Bus architectures.
3. State and explain the basic performance equation that is used to measure the performance of a
computer.
4. Explain the factors that affect the performance of a computer.
5. Define Byte addressability and illustrate the Big-endian and Little-endian assignments with
examples.
6. Differentiate between CISC and RISC.

7. List and explain the steps involved in the two major operations of Memory.

8. Demonstrate the application of various condition codes with suitable examples.


9. List the 4 types of operations for which the computer should have capable instructions. Explain
the Basic instruction types.

10. Define addressing mode. List and outline all the generic addressing modes with examples.

11. Illustrate the instruction execution & straight-line sequencing with an example program and
diagram

12. List and explain the steps involved in the two major operations of Memory.
13. Obtain the performance for the following processor.
Clock rate = 900 MHz
No. of instructions executed = 1500
Average no of steps needed / machine instruction = 18
14. Find the total time required to execute the program running in a 1 GHz machine, that contains
1000 instructions. Out of that 25% instructions requires 4 clock cycles,40% instructions require
5 clock cycles and remaining require 3 clock cycles for execution.

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