Scribd
Upload
2 views5 pages

06 Task Performance 1 - ARG

The document presents a Verilog implementation of a 2-bit binary up counter, including the main counter module and a testbench for simulation. It details the functionality of the counter, which resets to 0 on a reset signal and increments on each clock cycle, along with a flowchart explaining the process. The testbench generates a clock signal and displays the count at each rising edge, allowing for verification of the counter's behavior.

Uploaded by

Chalmer Narvaez
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
2 views5 pages

06 Task Performance 1 - ARG

The document presents a Verilog implementation of a 2-bit binary up counter, including the main counter module and a testbench for simulation. It details the functionality of the counter, which resets to 0 on a reset signal and increments on each clock cycle, along with a flowchart explaining the process. The testbench generates a clock signal and displays the count at each rising edge, allowing for verification of the counter's behavior.

Uploaded by

Chalmer Narvaez
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 5

NARVAEZ, Joseph Chalmer P.

BSCpE – 601

2-Bit Binary Up Counter

Verilog Code: 2-Bit Binary Up Counter


IDE: https://www.edaplayground.com/
// 2-bit binary up-counter (from your module)
module binary_up_counter (
input wire clk,
input wire reset,
output reg [1:0] count
);
always @(posedge clk or posedge reset) begin
if (reset)
count <= 2'b00;
else
count <= count + 1;
end
endmodule

// Testbench
module tb_binary_up_counter;
reg clk = 0;
reg reset = 1;
wire [1:0] count;

// Instantiate the counter


binary_up_counter uut (
.clk(clk),
.reset(reset),
.count(count)
);

// Generate a 10 ns clock (100 MHz)


always #5 clk = ~clk;

initial begin
// Dump waveform
$dumpfile("counter.vcd");
$dumpvars(0, tb_binary_up_counter);

// Hold reset high for 20 ns, then release


#20 reset = 0;

// Let it count for a few cycles


#100 $finish;
end

// Optionally print to console every rising edge


always @(posedge clk) begin
$display("Time=%0t | reset=%b | count=%b", $time, reset, count);
end
endmodule

Output:
Pseudocode:

BEGIN
// Initialization (implicit in hardware/reset behavior)
count ← 00

// This block always “runs” on every rising clock edge or if reset is asserted
ON each rising_edge(clk) or rising_edge(reset) DO
IF reset == 1 THEN
count ← 00 // Force counter to 0 when reset is high
ELSE
count ← count + 1 // Increment by one (wraps from 11 → 00)
END IF
END ON
END
Explanation of each step:
1. Initialization:
o When the system first powers up (or when reset is asserted), count is
driven to 00.
2. Sensitivity List (posedge clk or posedge reset):
o On any rising edge of clk, we will update count.
o On any rising edge of reset, we immediately force count = 00, regardless
of clk.
3. Reset Check:
o If reset is detected high, set count = 00.
o Otherwise (i.e., normal clock edge with reset = 0), increment count by 1.
4. Natural Binary Wraparound:
o Since count is a 2-bit register, adding 1 to 2’b11 automatically rolls it over
to 2’b00.
Flowchart:

[Event: posedge clk


or posedge reset]

Is reset == 1?

yes no

count ← 2'b00 count ← count + 1


(clear to 00) (increment)

Wait for posedge clk


or posedge reset
How to read the flowchart:
1. Event Trigger (Top Box)
o The “clocked process” is sensitive to both the rising edge of clk and the
rising edge of reset.
o Whenever either happens, control flows downward into the decision.
2. Decision: Is reset == 1?
o If Yes, we immediately set count = 2’b00 (clear).
o If No, we go to the “increment” action.
3. Actions
o Reset Path: count ← 2’b00.
o Normal Path: count ← count + 1 (2-bit addition, so it wraps from 11 → 00
automatically).
4. Loop Back
o After performing either action, the process waits for the next rising edge of
clk or rising edge of reset.

You might also like