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Physical Design File Formats

The document outlines various file formats used in the physical design flow of integrated circuits, detailing their purposes, key contents, and usage. Formats include LEF for cell information, LIB for timing and power data, GDSII/OASIS for layout representation, and others like DEF, SPEF, and SDC for design implementation and constraints. Each format plays a crucial role in different stages of the design process, ensuring accurate representation and compliance with design specifications.

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2 views4 pages

Physical Design File Formats

The document outlines various file formats used in the physical design flow of integrated circuits, detailing their purposes, key contents, and usage. Formats include LEF for cell information, LIB for timing and power data, GDSII/OASIS for layout representation, and others like DEF, SPEF, and SDC for design implementation and constraints. Each format plays a crucial role in different stages of the design process, ensuring accurate representation and compliance with design specifications.

Uploaded by

santhosh mb
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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File Formats in Physical Design Flow

1. LEF (Library Exchange Format)

- Purpose: Provides abstract information about standard cells and macros for the physical design

process.

- Key Contents:

- Cell dimensions: Height, width.

- Pin locations and directions (input/output/inout).

- Metal layers and routing tracks.

- Design rules: Minimum spacing, site definition, via definitions.

- Does NOT contain timing or power information.

- Usage: Used in floorplanning, placement, and routing.

2. LIB (Liberty File)

- Purpose: Describes the timing, power, and functional behavior of standard cells.

- Key Contents:

- Timing models: Setup/hold times, propagation delays, slew rates.

- Power models: Dynamic and leakage power.

- Logical function: Boolean representation of each cell.

- Contains characterized data for different Process, Voltage, and Temperature (PVT) corners.

- Usage: Used for static timing analysis (STA), synthesis, and power analysis.

3. GDSII/OASIS

- GDSII: Binary file format for representing the physical layout of the chip.

- Contains polygons, layers, and geometric shapes for fabrication.

- OASIS: A more efficient version of GDSII with smaller file sizes.


- Usage: Sent to the foundry for mask generation.

4. DEF (Design Exchange Format)

- Purpose: Represents the physical implementation of the design.

- Key Contents:

- Placement of standard cells, macros, and IO pins.

- Routing information (nets, layers, vias).

- Clock tree details (if available).

- Usage: Used to transfer data between tools during placement and routing.

5. SPEF (Standard Parasitic Exchange Format)

- Purpose: Captures parasitic information of interconnects (resistance, capacitance).

- Key Contents:

- RC network of nets and interconnects.

- Pin-to-pin parasitics for nets.

- Usage: Used in post-layout static timing analysis.

6. SDC (Synopsys Design Constraints)

- Purpose: Specifies design constraints for synthesis and physical design.

- Key Contents:

- Clock definitions, timing constraints, I/O constraints.

- Multicycle paths, false paths, input/output delays.

- Usage: Guides the tool to meet design timing and performance requirements.

7. Verilog (Netlist)

- Purpose: Describes the logical functionality of the design.

- Key Contents:
- List of modules, nets, and instances.

- Connections between standard cells and macros.

- Usage: Acts as the input for synthesis and physical design.

8. TLU+ (Table Lookup Format)

- Purpose: Represents technology-specific RC extraction data.

- Key Contents:

- Resistance and capacitance tables for different layers.

- Usage: Used in parasitic extraction.

9. ITF (Interconnect Technology File)

- Purpose: Contains details about the interconnect layers for RC extraction.

- Key Contents:

- Metal layer specifications, thickness, spacing.

- Dielectric properties.

- Usage: Used during RC extraction (replaced by TLU+ in modern flows).

10. Milkyway

- Purpose: A proprietary database format by Synopsys to store physical design data.

- Usage: Used internally in tools like ICC and IC Compiler II.

11. UPF/CPF (Power Intent Files)

- UPF (Unified Power Format): IEEE standard.

- CPF (Common Power Format): Cadence format.

- Purpose: Defines the power intent of the design.

- Key Contents:

- Power domains, voltage levels.


- Power-gating strategies, isolation cells.

- Usage: Low-power design and verification.

12. STF (Standard Test Format)

- Purpose: Contains data for manufacturing test patterns.

- Usage: Used for testability checks and post-fabrication testing.

13. LVS/DRC Rule Files

- LVS (Layout vs. Schematic): Contains rules for verifying the layout matches the schematic.

- DRC (Design Rule Check): Defines rules for verifying the layout adheres to the process design

rules.

- Usage: Used in signoff checks to ensure manufacturability.

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