Scribd
Upload
3 views1 page

Ut2 Fpga Print

This document outlines the Test II for the UG III Year VI Semester in Programming FPGA using HDLs at GCT, Coimbatore for the academic year 2023-24. It includes two parts: Part A consists of six short answer questions, while Part B contains four detailed questions requiring explanations, examples, and system verilog code implementations. The test covers various topics including state variables, procedural blocks, user-defined types, arrays, FSM design, and sequence detection.

Uploaded by

abishek2003jothi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
3 views1 page

Ut2 Fpga Print

This document outlines the Test II for the UG III Year VI Semester in Programming FPGA using HDLs at GCT, Coimbatore for the academic year 2023-24. It includes two parts: Part A consists of six short answer questions, while Part B contains four detailed questions requiring explanations, examples, and system verilog code implementations. The test covers various topics including state variables, procedural blocks, user-defined types, arrays, FSM design, and sequence detection.

Uploaded by

abishek2003jothi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 1

DEPARTMENT OF ECE, GCT, COIMBATORE-13

AY 2023-24 ODD SEMESTER, UG III YEAR VI SEMESTER – TEST II


Date : 19.06.2024FN 18LPE646Programming FPGA using HDLs VLSI(Honors & Minor Degree) MAX. : 60 Marks
PART A 6 X 2 = 12 Marks
Q No Questions BL CO
1 List the 2 state and 4 state variables.What is the default value of 2 and 4 state variables K1 CO3
2 Provide the syntax of Package .Give its importance. K2 CO3
3 Difference between static and automatic function. K1 CO4
4 What are the different procedural blocks adapted by system verilog?Write the syntax. K2 CO4
5 Distinguish unique case and priority case statement. K1 CO5
6 Write a system verilog code for D latch. K2 CO5

PART B 4 X 12 = 48 Marks
Q No Questions BL CO
1 i) Explain about user defined types and its declaration with examples. (6) K2 CO3
ii) Write the features of unpacked and packed union in system verilog. (6)
2 Discuss about Array in System Verilog declaration and its types with suitable examples. K2 CO4
3 Design a FSM for the given vending machine using system verilog, it accepts only two coins, 5 pointand 10 point. K3 CO5
Whenever total of coins equal to 15 points, then nw_pa signal will gohigh and user will get news paper. It will
not return any coin, if total of points exceeds15 points.
Sr. No. Name of the Direction Width Description
Pin
1 Nw_pa Output 1 News Paper Signal
2 Coin Input 2 Only two Coins,
5 =2’b01
10 =2’b10
0 =2’b00
3 Clk Input 1 Clock Signal
4 Rst Input 1 Reset Signal
4 A sequence detector which will recognize the three-bit sequence 110. Your detector should output a 1 each K3 CO5
time the sequence 110 comes in. The input is a clocked serial bit stream.
i) Draw the state diagram for Moore Machine implementation of this FSM.
Ii) Write a system verilog code implementation of the rising edge detector.

1. 2.
Scrutiny Committee Signature HOD/PECE

You might also like