The Memory System

Fundamental Concepts
 Some basic concepts
• Maximum size of the Main Memory
• byte-addressable
• CPU-Main Memory Connection
P rocessor M em ory
k- bit
addressbus
M AR
n- bit
databus U pto 2 kaddressabl
e
M DR l ocations

W ord l
ength = nbits

C ontroll ines
( R / W , M F C , etc. )
• Memory organization – basic concepts,
semiconductor RAM memories - memory
system considerations – semiconductor
ROM memories - speed, size and cost.
Memory design using decoders.
Some basic concepts(Contd.,)
Measures for the speed of a memory:
memory access time.
memory cycle time.
An important design issue is to provide a
computer system with as large and fast a
memory as possible, within a given cost target.
Several techniques to increase the effective
size and speed of the memory:
Cache memory (to increase the effective
speed).
Virtual memory (to increase the effective
size).
 The Memory System

Semiconductor RAM memories

 Internal organization of memory
chips
• Each memory cell can hold one bit of
information.
• Memory cells are organized in the form of an
array.
• One row is one memory word.
• All cells of a row are connected to a common
line, known as the “word line”.
• Word line is connected to the address decoder.
• Sense/write circuits are connected to the data
input/output lines of the memory chip.
Internal organization of memory
chips
7 7 1 1 0 0
W 0

•
•
•
FF FF
A 0 W 1

•
•
•
A 1 A ddress M emory
• • • • • • cel
ls
decoder • • • • • •
A 2 • • • • • •
A 3

W 1 5
•
•
•

Sense / W rite Sense / W rite Sense / W rite R/ W

circuit circuit circuit
CS

Datainput / outputl
ines: b7 b1 b0
 SRAM Cell
• Two transistor inverters are cross connected to implement a basic
flip-flop.
• The cell is connected to one word line and two bits lines by
transistors T1 and T2
• When word line is at ground level, the transistors are turned off
and the latch retains its state
• Read operation: In order to read state of SRAM cell, the word line
is activated to close switches T1 and T2. Sense/Write circuits at
the bottom monitor the state of b and b’¢
b b

T1 T 2
X Y

W ord l
ine
B itl
ines
 Asynchronous DRAMs
• Static RAMs (SRAMs):
– Consist of circuits that are capable of retaining their
state as long as the power is applied.
– Volatile memories, because their contents are lost
when power is interrupted.
– Access times of static RAMs are in the range of few
nanoseconds.
– However, the cost is usually high.
• Dynamic RAMs (DRAMs):
– Do not retain their state indefinitely.
– Contents must be periodically refreshed.
– Contents may be refreshed while accessing them for
reading.
 Asynchronous DRAMs
RA S

R ow R ow 4 0 9 6 ´ (5 1 2 ´ 8 )
address
latch decoder cel
larray

A2 0 - 9 ¤A 8 - 0 Sense / W rite CS
circuits
R/ W

C olumn
address C ol
umn
decoder
latch

CA S D7 D0
 Asynchronous DRAMs
• A 16 mega bit DRAM chip configured as 2M X 8, Cells
organized in the form of 4k x 4k array.
• 4096 CELLS,Each row can store 512 bytes. 12 bits to
select a row, and 9 bits to select a group in a row. Total
of 21 bits.
• First apply the row address, RAS signal latches the row
address. Then apply the column address, CAS signal
latches the address.
• Timing of the memory unit is controlled by a
specialized unit which generates RAS and CAS signals
 Synchronous DRAMs
R efresh
counter

R ow
address R ow
decoder C el
larray
latch
R ow/ C ol
umn
address
C ol
umn C ol
umn
address R ead/ W rite
decoder circuits& l atch es
counter

Cl
ock
RA S M ode register
CA S and Datainput Dataoutput
register register
R/ W timingcontrol

CS

Data
 Synchronous DRAMs
•Operation is directly synchronized
R efresh
counter with processor clock signal.
•The outputs of the sense circuits are
connected to a latch.
•During a Read operation, the
R ow
address R ow
decoder C el
larray contents of the cells in a row are
latch
loaded onto the latches.
R ow/ C ol
umn
address •During a refresh operation, the
C ol
umn C ol
umn
contents of the cells are refreshed
R ead/ W rite
address
counter decoder circuits& l atch es without changing the contents of
the latches.
•Data held in the latches correspond
to the selected columns are transferred
Cl
ock
RA S
to the output.
M ode register
CA S and Datainput Dataoutput •For a burst mode of operation,
register register
R/ W timingcontrol successive columns are selected using
CS column address counter and clock.
CAS signal need not be generated
externally. A new data is placed during
Data
raising edge of the clock
 Latency, Bandwidth
• Memory latency is the time it takes to
transfer a word of data to or from
memory
• Memory bandwidth is the number of bits
or bytes that can be transferred in one
second.
 Organization of a 2Mx32 memory module
using 512k x 8 static memory chips
•Implement a memory unit of
2 1 - bit
addresses 1 9 - bitinternalch ip address 2M words of 32 bits each.
A
A
0
1 •Use 512kx8 static memory
chips.
A1
A2
9
0
•Each column consists of 4
chips.
•Each chip implements one byte
position.
•A chip is selected by setting its
2 - bit
decoder chip select control line to 1.
•Selected chip places its data
on the data output line, outputs
5 1 2 K ´8
of other chips are in high
memory ch ip
D3 1 -2 4
D2 3 -1 6
D1 5 -8
D7 - 0 impedance state.
5 1 2 K ´ 8 memory ch ip •21 bits to address a 32-bit
word.
1 9 - bit
address
8 - bitdata
input/ output
•High order 2 bits are needed to
select the row, by activating the
C h ipsel
ect
four Chip Select signals.
•19 bits are used to access
 Dynamic memories
Large dynamic memory systems can be
implemented using DRAM chips in a similar
way to static memory systems.
Placing large memory systems directly on
the motherboard will occupy a large
amount of space.
Also, this arrangement is inflexible since the memory system cannot be
expanded easily.
Packaging considerations have led to the
development of larger memory units known
as SIMMs (Single In-line Memory Modules)
and DIMMs (Dual In-line Memory Modules).
Memory modules are an assembly of
memory chips on a small board that plugs
vertically onto a single socket on the
motherboard.
Occupy less space on the motherboard.
Memory System Considerations
• The choice of RAM chip for a given
application depends on :
– Cost
– Speed
– Power Dissipation
– Size of Chip
 Memory controller
Recall that in a dynamic memory chip, to
reduce the number of pins, multiplexed
addresses are used.
Address is divided into two parts:
High-order address bits select a row in the array.
They are provided first, and latched using RAS signal.
Low-order address bits select a column in the row.
They are provided later, and latched using CAS signal.
However, a processor issues all address bits at
the same time.
In order to achieve the multiplexing, memory
controller circuit is inserted between the
processor
and memory.
Memory controller (contd..)
R ow/ C ol
umn
A ddress address

RA S
R/ W
CA S
M emory
R equest control
ler R/ W
Processor M emory
CS
Cl
ock
Cl
ock

Data

19
The Memory System

Read-Only Memories (ROMs)

 Read-Only Memories (ROMs)
SRAM and SDRAM chips are volatile:
Lose the contents when the power is turned off.
Many applications need memory devices to retain
contents after the power is turned off.
For example, computer is turned on, the operating
system must be loaded from the disk into the memory.
Store instructions which would load the OS from the disk.
Need to store these instructions so that they will not be
lost after the power is turned off.
We need to store the instructions into a non-volatile
memory.
Non-volatile memory is read in the same manner as
volatile memory.
Separate writing process is needed to place information
in this memory.
Normal operation involves only reading of data, this type
of memory is called Read-Only memory (ROM).
Read-Only Memories (Contd.,)
Read-Only Memory:
Data are written into a ROM when it is manufactured.
Programmable Read-Only Memory
(PROM):
Allow the data to be loaded by a user.
Process of inserting the data is irreversible.
Storing information specific to a user in a ROM is expensive.

Providing programming capability to a user may be better.

Erasable Programmable Read-Only

Memory (EPROM):
Stored data to be erased and new data to be loaded.
Flexibility, useful during the development phase of digital systems.
Erasable, reprogrammable ROM.
Erasure requires exposing the ROM to UV light.
Read-Only Memories (Contd.,)
Electrically Erasable Programmable Read-Only
Memory (EEPROM):
To erase the contents of EPROMs, they have to be exposed to ultraviolet light.
Physically removed from the circuit.
EEPROMs the contents can be stored and erased electrically.
Flash memory:
Has similar approach to EEPROM.
Read the contents of a single cell, but write the
contents of an entire block of cells.
Flash devices have greater density.
▪ Higher capacity and low storage cost per bit.
Power consumption of flash memory is very low,
making it attractive for use in equipment that is
battery-driven.
Single flash chips are not sufficiently large, so
larger memory modules are implemented using
flash cards and flash drives.
 Speed, Size, and Cost
A big challenge in the design of a computer system is to provide
a sufficiently large memory, with a reasonable speed at an
affordable cost.
Static RAM:
Very fast, but expensive, because a basic SRAM cell has a
complex circuit making it impossible to pack a large number
of cells onto a single chip.
Dynamic RAM:
Simpler basic cell circuit, hence are much less expensive, but
significantly slower than SRAMs.
Magnetic disks:
Storage provided by DRAMs is higher than SRAMs, but is still
less than what is necessary.
Secondary storage such as magnetic disks provide a large
amount
of storage, but is much slower than DRAMs.
 Memory Hierarchy
P rocessor •Fastest access is to the data held in
processor registers. Registers are at
R egisters the top of the memory hierarchy.
•Relatively small amount of memory
Increasing Increasing
Increasing
siz e speed costperbit that can be implemented on the
PrimaryL 1 processor chip. This is processor
cach e
cache.
•Two levels of cache. Level 1 (L1)
cache is on the processor chip.
SecondarLy2 Level 2 (L2) cache is in between
cach e main memory and processor.
•Next level is main memory,
implemented as SIMMs. Much larger,
but much slower than cache memory.
M ain
memory •Next level is magnetic disks. Huge
amount of inexepensive storage.
•Speed of memory access is critical,
the idea is to bring instructions and
M agneticdisk data that will be used in the near
secondary future as close to the processor as
memory
possible.
The Memory System

Cache Memories
• Cache memory – mapping functions –
replacement algorithms, multiple module
memories and interleaving.
• Virtual memory – paging and
segmentation, RAID.
 Cache Memories
Processor is much faster than the main memory.
As a result, the processor has to spend much of its
time waiting while instructions and data are being
fetched from the main memory.
Major obstacle towards achieving good performance.
Speed of the main memory cannot be
increased beyond a certain point.
Cache memory is an architectural arrangement
which makes the main memory appear faster
to the processor than it really is.
Cache memory is based on the property of
computer programs known as “locality of
reference”.
 Locality of Reference
Analysis of programs indicates that many instructions
in localized areas of a program are executed
repeatedly during some period of time, while the
others are accessed relatively less frequently.
These instructions may be the ones in a loop, nested
loop or few procedures calling each other repeatedly.
This is called “locality of reference”.
Temporal locality of reference:
Recently executed instruction is likely to be
executed again very soon.
Spatial locality of reference:
Instructions with addresses close to a recently
instruction are likely To be executed soon.
 Cache memories
Processor C ach e M ain
memory

• Processor issues a Read request, a block of words is

transferred from the main memory to the cache, one
word at a time.
• Subsequent references to the data in this block of
words are found in the cache.
• At any given time, only some blocks in the main
memory are held in the cache. Which blocks in the
main memory are in the cache is determined by a
“mapping function”.
• When the cache is full, and a block of words needs to
be transferred from the main memory, some block of
words in the cache must be replaced. This is
determined by a “replacement algorithm”.
 Cache hit
• Existence of a cache is transparent to the processor.
The processor issues Read and Write requests in the
same manner.
• If the data is in the cache it is called a Read or
Write hit.
• Read hit:
The data is obtained from the cache.

• Write hit:
Cache has a replica of the contents of the main memory.
Contents of the cache and the main memory may be
updated simultaneously. This is the write-through
protocol.
Update the contents of the cache, and mark it as
updated by setting a bit known as the dirty bit or
modified bit. The contents of the main memory are
updated when this block is replaced. This is write-back
 Cache miss
• If the data is not present in the cache, then a Read miss
or Write miss occurs.
• Read miss:
Block of words containing this requested word is transferred
from the memory.
After the block is transferred, the desired word is forwarded
to the processor.
The desired word may also be forwarded to the processor as
soon as it is transferred without waiting for the entire block
to be transferred. This is called load-through or early-
restart.

• Write-miss:
Write-through protocol is used, then the contents of the
main memory are updated directly.
If write-back protocol is used, the block containing the
addressed word is first brought into the cache. The desired
word
 Cache Coherence Problem
• A bit called as “valid bit” is provided for each block.
• If the block contains valid data, then the bit is set to 1,
else it is 0.
• Valid bits are set to 0, when the power is just turned on.
• When a block is loaded into the cache for the first time,
the valid bit is set to 1.
• Data transfers between main memory and disk occur
directly bypassing the cache.
• When the data on a disk changes, the main memory block is
also updated.
• However, if the data is also resident in the cache, then the
valid bit is set to 0.
• What happens if the data in the disk and main memory
changes and the write-back protocol is being used?
• In this case, the data in the cache may also have changed
and is indicated by the dirty bit.
• The copies of the data in the cache, and the main memory
are different. This is called the cache coherence problem.
• One option is to force a write-back before the main
memory is updated from the disk.
 Mapping functions
Mapping functions determine how
memory blocks are placed in the cache.
A simple processor example:
Cache consisting of 128 blocks of 16 words
each.
Total size of cache is 2048 (2K) words.
Main memory is addressable by a 16-bit
address.
Main memory has 64K words.
Main memory has 4K blocks of 16 words each.
 Mapping functions
Mapping functions determine how
memory blocks are placed in the cache.
Three mapping functions:
Direct mapping
Associative mapping
Set-associative mapping.
 Direct mapping
•Block j of the main memory maps to j
modulo 128 of the cache. 0 maps to 0, 129
maps to 1.
M ain
memory Bl
ock 0 •More than one memory block is mapped
C ach e Bl
ock 1 onto the same position in the cache.
tag
Bl
ock 0
•May lead to contention for cache blocks
tag even if the cache is not full.
Bl
ock 1
•Resolve the contention by allowing new
Bl
ock 1 2 7 block to
Bl
ock 1 2 8 replace the old block, leading to a trivial
tag
Bl
ock 1 2 7 Bl
ock 1 2 9
replacement algorithm.
•Memory address is divided into three fields:
- Low order 4 bits determine one of the
16
Bl
ock 2 5 5 words in a block.
Tag Bl
ock W ord
Bl
ock 2 5 6
- When a new block is brought into the
5 7 4
cache,
Bl
ock 2 5 7
M ainmemory address the next 7 bits determine which cache
block this new block is placed in.
- High order 5 bits determine which of the
Bl
ock 4 0 9 5
possible 32 blocks is currently present in
the cache. These are tag bits.
• Block j of the main memory maps to j modulo 128 of the cache. 0
maps to 0, 129 maps to 1.
• More than one memory block is mapped onto the same position in
the cache.
• May lead to contention for cache blocks even if the cache is not
full.
• Resolve the contention by allowing new block to
replace the old block, leading to a trivial replacement algorithm.
• Memory address is divided into three fields:
• - Low order 4 bits determine one of the 16 words in a block.
• - When a new block is brought into the cache, the next 7 bits
determine which cache block this new block is placed in.
• - High order 5 bits determine which of the possible 32 blocks
is currently present in the cache. These are tag bits.
• Simple to implement but not very flexible.
 Associative mapping
•Main memory block can be placed
M ain
into any cache position.
Bl
ock 0
memory
•Memory address is divided into two
Bl
ock 1
tag
C ach e
fields:
Bl
ock 0
- Low order 4 bits identify the word
tag
Bl
ock 1 within a block.
Bl
ock 1 2 7 - High order 12 bits or tag bits
Bl
ock 1 2 8 identify a memory block when it is
tag
Bl
ock 1 2 7 Bl
ock 1 2 9 resident in the cache.
•Flexible, and uses cache space
efficiently.
•Replacement algorithms can be used
T ag W ord
Bl
ock 2 5 5
to replace an existing block in the
1 2 4 Bl
ock 2 5 6
cache when the cache is full.
M ainmemory address Bl
ock 2 5 7 •Cost is higher than direct-mapped
cache because of the need to search
all 128 patterns to determine whether
Bl
ock 4 0 9 5 a given block is in the cache.
 Set-Associative mapping
Blocks of cache are grouped into sets.
Mapping function allows a block of the
C ach e
M ain
main
Bl
ock 0
tag Bl
ock 0
memory memory to reside in any block of a specific
Bl
ock 1 set.
tag Bl
ock 1
Divide the cache into 64 sets, with two
tag Bl
ock 2 blocks per set.
tag Bl
ock 3 Memory block 0, 64, 128 etc. map to block
Bl
ock 6 3
0, and they can occupy either of the two
Bl
ock 6 4 positions.
tag
Bl
ock 1 2 6 Bl
ock 6 5 Memory address is divided into three fields:
tag
Bl
ock 1 2 7
- 6 bit field determines the set number.
- High order 6 bit fields are compared
to the tag fields of the two blocks in a set.
Tag Bl
ock W ord
Bl
ock 1 2 7 Set-associative mapping combination of
5 7 4 Bl
ock 1 2 8 direct and associative mapping.
Bl
ock 1 2 9
Number of blocks per set is a design
M ainmemory address
parameter.
- One extreme is to have all the blocks
in one set, requiring no set bits (fully
Bl
ock 4 0 9 5 associative mapping).
The Memory System

Performance considerations
 Performance considerations
• A key design objective of a computer system is to
achieve the best possible performance at the lowest
possible cost.
– Price/performance ratio is a common measure of success.
• Performance of a processor depends on:
– How fast machine instructions can be brought into the
processor for execution.
– How fast the instructions can be executed.
 Interleaving
Divides the memory system into a number
of memory modules. Each module has its own address buffer
register (ABR) and data buffer register (DBR).
Arranges addressing so that successive
words in the address space are placed in
different modules.
When requests for memory access involve
consecutive addresses, the access will be to
different modules.
Since parallel access to these modules is
possible, the average rate of fetching words
from the Main Memory can be increased.
 Methods of address layouts
k bits m bits
m bits k bits
M odul
e A ddressinmodul
e M M address
A ddressinmodul
e M odul
e M M address

A BR DB R A B R DB R A B R DB R A B R DB R A B R DB R A B R DB R

M odul
e M odul
e M odul e M odul
e M odul
e M odul e
0 i n- 1 0 i 2 k- 1

Consecutive words are placed in a •Consecutive words are located in

module.
High-order k bits of a memory consecutive modules.
address determine the module. •C o n s e c u t i v e a d d r e s s e s c a n b e
Low-order m bits of a memory located in consecutive modules.
address determine the word
within a module. •While transferring a block of data,
When a block of words is several memory modules can be kept
transferred from main memory to busy at the same time.
cache, only one module is busy
at a time.
 Hit Rate and Miss Penalty
• Hit rate
• Miss penalty
• Hit rate can be improved by increasing block size, while
keeping cache size constant
• Block sizes that are neither very small nor very large
give best results.
• Miss penalty can be reduced if load-through approach is
used when loading new blocks into cache.
 Caches on the processor chip
• In high performance processors 2 levels of
caches are normally used.
• Avg access time in a system with 2 levels
of caches is
T ave = h1c1+(1-h1)h2c2+(1-h1)(1-h2)M
 Other Performance
Enhancements
Write buffer
Write-through:
• Each write operation involves writing to the main memory.
• If the processor has to wait for the write operation to be
complete, it slows down the processor.
• Processor does not depend on the results of the write operation.
• Write buffer can be included for temporary storage of write
requests.
• Processor places each write request into the buffer and continues
execution.
• If a subsequent Read request references data which is still in the
write buffer, then this data is referenced in the write buffer.
Write-back:
• Block is written back to the main memory when it is replaced.
• If the processor waits for this write to complete, before reading
the new block, it is slowed down.
• Fast write buffer can hold the block to be written, and the new
block can be read first.
Other Performance Enhancements
(Contd.,)
Prefetching
• New data are brought into the processor when they
are first needed.
• Processor has to wait before the data transfer is
complete.
• Prefetch the data into the cache before they are
actually needed, or a before a Read miss occurs.
• Prefetching can be accomplished through software
by including a special instruction in the machine
language of the processor.
Inclusion of prefetch instructions increases the length
of the programs.
• Prefetching can also be accomplished using
hardware:
Circuitry that attempts to discover patterns in
memory references and then prefetches according
Other Performance Enhancements
(Contd.,)
Lockup-Free Cache
• Prefetching scheme does not work if it stops other
accesses to the cache until the prefetch is
completed.
• A cache of this type is said to be “locked” while it
services a miss.
• Cache structure which supports multiple
outstanding misses is called a lockup free cache.
• Since only one miss can be serviced at a time, a
lockup free cache must include circuits that keep
track of all the outstanding misses.
• Special registers may hold the necessary
information about these misses.
The Memory System

Virtual Memory
 Virtual memories
Recall that an important challenge in the
design of a computer system is to provide a
large, fast memory system at an affordable
cost.
Architectural solutions to increase the
effective speed and size of the memory
system.
Cache memories were developed to
increase the effective speed of the memory
system.
Virtual memory is an architectural solution
50
 Virtual memories (contd..)
Recall that the addressable memory space
depends on the number of address bits in a
computer.
For example, if a computer issues 32-bit addresses, the addressable memory space is
4G bytes.
Physical main memory in a computer is generally
not as large as the entire possible addressable
space.
Physical memory typically ranges from a few hundred megabytes to 1G bytes.
Large programs that cannot fit completely into
the main memory have their parts stored on
secondary storage devices such as magnetic disks.
Pieces of programs must be transferred to the main memory from secondary storage
before they can be executed.

51
 Virtual memories (contd..)
When a new piece of a program is to be
transferred to the main memory, and the
main memory is full, then some other
piece in the main memory must be
replaced.
Recall this is very similar to what we studied in case of cache
memories.
Operating system automatically
transfers data between the main memory
and secondary storage.
Application programmer need not be concerned with this transfer.
Also, application programmer does not need to be aware of the
limitations imposed by the available physical memory.
52
 Virtual memories (contd..)
Techniques that automatically move program and
data between main memory and secondary storage
when they are required for execution are called
virtual-memory techniques.
Programs and processors reference an instruction or
data independent of the size of the main memory.
Processor issues binary addresses for instructions and
data.
These binary addresses are called logical or virtual addresses.
Virtual addresses are translated into physical
addresses by a combination of hardware and
software subsystems.
If virtual address refers to a part of the program that is currently in the main memory, it is
accessed immediately.
If the address refers to a part of the program that is not currently in the main memory, it
is first transferred to the main memory before it can be used.

53
 Virtual memory organization
Processor
•Memory management unit (MMU) translates
virtual addresses into physical addresses.
V irtualaddress •If the desired data or instructions are in the
main memory they are fetched as described
Data M M U previously.
•If the desired data or instructions are not in
Ph ysicaladdress the main memory, they must be transferred
from secondary storage to the main memory.
C ach e •MMU causes the operating system to bring
the data from the secondary storage into the
Data Ph ysicaladdress main memory.

M ain memory

DM A transfer

Disk storage

54
 Address translation
Assume that program and data are
composed of fixed-length units called pages.
A page consists of a block of words that
occupy contiguous locations in the main
memory.
Page is a basic unit of information that is
transferred between secondary storage and
main memory.
Size of a page commonly ranges from 2K to
16K bytes.
Pages should not be too small, because the access time of a secondary
storage device is much larger than the main memory.
Pages should not be too large, else a large portion of the page may not be
used, and it will occupy valuable space in the main memory.

55
 Address translation (contd..)
• Concepts of virtual memory are similar to
the concepts of cache memory.
• Cache memory:
– Introduced to bridge the speed gap between the processor and the
main memory.
– Implemented in hardware.

• Virtual memory:
– Introduced to bridge the speed gap between the main memory and
secondary storage.
– Implemented in part by software.

56
Address translation (contd..)
Each virtual or logical address generated by a
processor is interpreted as a virtual page number
(high-order bits) plus an offset (low-order bits)
that specifies the location of a particular byte
within that page.
Information about the main memory location of
each page is kept in the page table.
Main memory address where the page is stored.
Current status of the page.
Area of the main memory that can hold a page is
called as page frame.
Starting address of the page table is kept in a
page table base register.

57
 Address translation (contd..)
• Virtual page number generated by the
processor is added to the contents of the
page table base register.
– This provides the address of the corresponding entry in the page table.

• The contents of this location in the page

table give the starting address of the
page if the page is currently in the main
memory.

58
 Address translation (contd..)
PTBR holds V irtualaddressfrom processor
the address of Page table base register
the page table. Page table address V irtualpage number O ffset
Virtual address is
interpreted as page
+ number and offset.
PA G E T A B L E
PTBR + virtual
page number provide
the entry of the page This entry has the starting location
in the page table. of the page.

Page table holds information

about each page. This includes
the starting address of the page
in the main memory. C ontrol Page frame
bits inmemory Page frame O ffset

Ph ysicaladdressinmainmemory

59
Address translation (contd..)
Page table entry for a page also includes
some control bits which describe the status
of the page while it is in the main memory.
One bit indicates the validity of the page.
Indicates whether the page is actually loaded into the main memory.
Allows the operating system to invalidate the page without actually
removing it.
One bit indicates whether the page has
been modified during its residency in the
main memory.
This bit determines whether the page should be written back to the disk
when it is removed from the main memory.
Similar to the dirty or modified bit in case of cache memory.

60
 Address translation (contd..)
• Other control bits for various other types
of restrictions that may be imposed.
– For example, a program may only have read permission for a page, but
not write or modify permissions.

61
Address translation (contd..)
Where should the page table be located?
Recall that the page table is used by the MMU
for every read and write access to the memory.
Ideal location for the page table is within the MMU.
Page table is quite large.
MMU is implemented as part of the processor
chip.
Impossible to include a complete page table on
the chip.
Page table is kept in the main memory.
A copy of a small portion of the page table can
be accommodated within the MMU.
Portion consists of page table entries that correspond to the most recently accessed
pages.
62
Address translation (contd..)
A small cache called as Translation
Lookaside Buffer (TLB) is included in the
MMU.
TLB holds page table entries of the most recently accessed pages.
Recall that cache memory holds most
recently accessed blocks from the main
memory.
Operation of the TLB and page table in the main memory is similar to the
operation of the cache and main memory.
Page table entry for a page includes:
Address of the page frame where the page resides in the main memory.
Some control bits.
In addition to the above for each page, TLB
must hold the virtual page number for each
page. 63
 Address translation (contd..)
V irtualaddress from processor

V irtualpage number O ffset Associative-mapped TLB

High-order bits of the virtual address
generated by the processor select the
TL B
virtual page.
V irtualpage
number
C ontrol
bits
Page frame
in memory These bits are compared to the virtual
page numbers in the TLB.
If there is a match, a hit occurs and
the corresponding address of the page
N o
frame is read.
= ?
If there is no match, a miss occurs
Y es
and the page table within the main
M iss
memory must be consulted.
H it
Set-associative mapped TLBs are
found in commercial processors.
Page frame O ffset

Ph ysicaladdress in main memory

64
Address translation (contd..)
How to keep the entries of the TLB
coherent with the contents of the page
table in the main memory?
Operating system may change the contents
of the page table in the main memory.
Simultaneously it must also invalidate the corresponding entries in the TLB.
A control bit is provided in the TLB to
invalidate an entry.
If an entry is invalidated, then the TLB gets
the information for that entry from the
page table.
Follows the same process that it would follow if the entry is not found in
the TLB or if a “miss” occurs.

65
Address translation (contd..)
What happens if a program generates
an access to a page that is not in the
main memory?
In this case, a page fault is said to
occur.
Whole page must be brought into the main memory from the disk,
before the execution can proceed.
Upon detecting a page fault by the
MMU, following actions occur:
MMU asks the operating system to intervene by raising an
exception.
Processing of the active task which caused the page fault is
interrupted.
Control is transferred to the operating system.
Operating system copies the requested page from secondary
storage to the main memory.
Once the page is copied, control is returned to the task which was
interrupted. 66
 Address translation (contd..)
• Servicing of a page fault requires
transferring the requested page from
secondary storage to the main memory.
• This transfer may incur a long delay.
• While the page is being transferred the
operating system may:
– Suspend the execution of the task that caused the page fault.
– Begin execution of another task whose pages are in the main memory.

• Enables efficient use of the processor.

67
 Address translation (contd..)
• How to ensure that the interrupted task
can continue correctly when it resumes
execution?
• There are two possibilities:
– Execution of the interrupted task must continue from the point where
it was interrupted.
– The instruction must be restarted.

• Which specific option is followed depends

on the design of the processor.

68
Address translation (contd..)
When a new page is to be brought into the main
memory from secondary storage, the main
memory may be full.
Some page from the main memory must be replaced with this new page.
How to choose which page to replace?
This is similar to the replacement that occurs when the cache is full.
The principle of locality of reference (?) can also be applied here.
A replacement strategy similar to LRU can be applied.
Since the size of the main memory is relatively
larger compared to cache, a relatively large
amount of programs and data can be held in the
main memory.
Minimizes the frequency of transfers between secondary storage and main memory.

69
Address translation (contd..)
A page may be modified during its
residency in the main memory.
When should the page be written back to
the secondary storage?
Recall that we encountered a similar
problem in the context of cache and main
memory:
Write-through protocol(?)
Write-back protocol(?)
Write-through protocol cannot be used,
since it will incur a long delay each time a
small amount of data is written to the disk.
70