RVS COLLEGE OF ENGINEERING AND TECHNOLOGY, COIMBATORE

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

QUESTION BANK(Reg-2017)
EE8691 -EMBEDDED SYSTEMS
YEAR / SEMESTER: III / VI
UNIT 1
PART A
1. What is In-Circuit Emulator? (Nov/Dec-2019) (Apr/May 2019)
An in-circuit emulator (ICE) is a hardware interface that allows a programmer to change
or debug the software in an embedded system. The ICE is temporarily installed between the
embedded system and an external terminal or personal computer so that the programmer can
observe and alter what takes place in the embedded system, which has no display or
keyboard of its own.

2. What are the major processor selection criteria for an embedded system? (Nov/Dec-2019)
 Performance considerations.
 Power Considerations.
 Peripheral Set.
 Operating Voltages.
 Specialized Processing.
 Digital Signal Processors.
 Price.

3. What are the typical characteristics of the embedded system? (Apr/May 2022) (Apr/May
2018) (Apr/May 2017)
 Sophisticated functionality
 Real time operation
 Low manufacturing cost
 Application dependent processor
 Restricted memory
 Low power consumption

4. What are the functional requirements of the embedded system? (Apr/May 2021) (Nov/Dec
2020) (Apr/May 2018)
 Available system memory
 Available processor speed
 Limit power dissipation

5. What are the steps involved in build process? (Apr/May 2017) (Nov/Dec 2016)
 Requirements
 Specification
 Architecture
 Components
 System Integration
6. Draw the block diagram of embedded systems. (Apr/May 2021) (Nov/Dec 2020) (Nov/Dec
2017) (Nov/Dec 2018)

7. What is the need for a Watch Dog Timer (WDT)? (Apr/May 2022) (Nov/Dec 2020)
(Nov/Dec 2017) (May/June 2016) (Nov/Dec 2018) (Apr/May 2019)
Watch Dog Timer is a timer that resets the processor in case the program gets stuck for
an unexpected length of time.

8. List out the challenges in building embedded systems. (Nov/Dec 2016) (May/June 2016)
 Amount and type of hardware needed
 Clock rate reduction
 Voltage reduction
 Process dead line
 Flexibility and upgrade ability

9. Define branch penalty in a multi stage pipeline processor. (Nov/Dec 2021)

Every processor has cycles of operation, each delay in the cycle will result in a penalty,
as it waits until the branch executes in the ALU or: Branch penalty in pipeline results from
non-zero distance between ALU and IF.

10. Draw the structure of SRAM cell implementation. (Nov/Dec 2021)

11. What are compiler and cross compiler in design of embedded system? (Nov/Dec 2020)
A compiler is a software that translates the computer code written in high-level
programming language to machine language. A cross compiler is a software that can create
executable code for platforms other than the one on which the compiler is running.
 PART B
1. Classify and explain the various types of embedded systems. (7) (Apr/May 2018)
2. i) How is allocation of memory to program segments carried out? Explain. (7) (Apr/May
2019)
ii) Illustrate hardware timer device with its signals, clock inputs and control bits. (6)
(Apr/May 2019)
3. List and explain the hardware units must be present in the Embedded System. (16) (Nov/Dec
2020) (Nov/Dec-2017) (Nov/Dec 2018)
4. Explain the various forms of memory present in an embedded system. (16 ) (Apr/May 2022)
(Nov/Dec-2017) (Nov/Dec 2018)
5. (i) Explain the possible steps involved in build process of embedded control systems. (8)
(Apr/May 2017) (Nov/Dec 2016)
(ii) Discuss about In-Circuit Emulator and watch dog timer. (8) (Apr/May 2022) (Apr/May
2017) (Apr/May 2018)
6. Discuss about the structural units in embedded processor and how a processor is selected an
embedded application. (8/16) (Apr/May 2022) (Nov/Dec 2016) (May/June 2016) (Apr/May
2018) (Apr/May 2019)
(or)
Name the structural units in general purpose processors and explain their functions of each
with block diagram. (Nov/Dec-2019)
7. With a neat diagram explain the working of Direct Memory Access (DMA) (16) (Apr/May
2022) (Apr/May 2021) (Nov/Dec 2020) (Nov/Dec 2016) (Apr/May 2018) (May/June 2016)
(Apr/May 2017)
(or)
What is a DMA? Draw the block diagram of a typical DMA controller showing the bushes
and control signal between processor, memory, DMA controller and I/O devices. Also explain
how data transferred between memory and I/O devices using DMA controller. (Nov/Dec-
2019) (Apr/May 2019)
8. (i) Explain how suitable processor and memory devices are selected for an embedded system
design. (Apr/May 2021) (Nov/Dec 2020)
(ii) Explain the functions of timing and counting devices in embedded system. (Apr/May
2021) (Nov/Dec 2020)

UNIT 2
PART A
1. Compare the key characteristics of RS232 and RS485. (Nov/Dec-2019)
 RS232 is full-duplex, RS485 is half-duplex, and RS422 is full-duplex.
 RS485 and RS232 are only the physical protocol of communication (ie interface
standard)
 RS485 is the differential transmission mode, RS232 is the single-ended transmission
mode, but the communication program does not have much difference.

2. Differentiate synchronous communication from iso-synchronous communication for serial

devices. (Apr/May 2021) (Nov/Dec 2020) (Apr/May 2019)
Synchronous
 Bits in a synchronous data stream must be transferred in sync with a clock signal. The control
signals for the data are derived from a clock signal. Synchronous data transfer systems
usually have an error detection mechanism. If an error is detected the data can be resent.

Asynchronous

Bits in an asynchronous data stream can be transferred at random intervals and the data rate
of the stream is not required to be constant. Asynchronous systems use a start bit to signal the
beginning of a data transmission. A stop bit is used to signal the end of a data transmission.
Asynchronous data transfer systems usually have an error detection mechanism. If an error is
detected the data can be resent.

Isochronous

An isochronous data transfer system combines the features of an asynchronous and

synchronous data transfer system. An isochronous data transfer system sends blocks of data
asynchronously, in other words the data stream can be transferred at random intervals.

3. Define bus. (Apr/May 2018)

Bus is a set of parallel lines which carry signals from one to another unit. Bus enables
inter connections among many units in a simple way. The signals are in specific sequences
according to a method or protocol.

4. Give the limitations of polling technique. (Apr/May 2018)

The polling technique, however, has limitations.
 It is wasteful of the processors time, as it needlessly checks the status of all
devices all the time.
 It is inherently slow, as it checks the status of all I/O devices before it comes back
to check any given one again.
 When fast devices are connected to a system, polling may simply not be fast
enough to satisfy the minimum service requirements. Priority of the device is
determined

5. How can we classify the I/O devices? (Nov/Dec 2017) (Nov/Dec 2018)
 Synchronous serial input and output
 Asynchronous serial UART input and output
 Parallel one bit input and output
 Parallel port input and output
 6. Draw the data frame work of I2C. (Nov/Dec 2021) (Nov/Dec 2017) (Nov/Dec 2018)
(Apr/May 2019)

7. Mention the few serial bus communication protocol. (Apr/May 2017)

 RS 232
 CAN
 I2 C
 SPI

8. List the features of CAN bus. (Apr/May 2022) (Apr/May 2017)

 This is standard bus in distribution network
 It has serial line which is bi directional

9. Mention the features of SPI serial interface. (Nov/Dec 2016)

 SPI has programmable clock rates
 Full-duplex mode
 Crystal clock frequency is 8MHz
 Open drain or totem pole output from master to slave

10. Point out the purpose of device driver. (Nov/Dec 2021) (Apr/May 2022) (Nov/Dec 2020)
(Nov/Dec 2016) (May/June 2016) (Nov/Dec 2019)
Device driver is a software program that allows, computer to communicate with hardware
devices. Eg- USB device driver program to communicate with PC.

11. How SPI differ from other serial interfaces. (May/June 2016)
 SPI can only work with one master device controlling multiple slaves
 SPI is a synchronous interface that uses a dedicated clock signal. The device
considered the 'Master' provides a clock signal used to synchronize data transactions
between the two devices.

12. Draw the frame format of CAN. (Apr/May 2021) (Nov/Dec 2020)
13. Compare handshaking in RS232 and IIC bus standard. (Nov/Dec 2020)

Protocol RS232/UART I2C SPI

Complexity Easy to chain multiple Complex as device

Simple
devices increases

Speed Slowest Faster than UART Fastest

Number of devices Up to 127, but gets Many, but gets

Up to 2 devices
complex complex

Number of wires 1 2 4

Duplex Full Duplex Half Duplex Full Duplex

No. of masters and Multiple slaves and 1 master, multiple

Single to Single
slaves masters slaves

PART B
1. (i) Give the summary of I/O devices in embedded systems. (6) (Apr/May 2018)
(ii) Compare the advantages and disadvantages of data transfer using serial and parallel
port/devices. (6) (Apr/May 2022) (Apr/May 2018)
2. Explain the CAN architecture with neat diagram. (16 ) (Nov/Dec 2020) (Nov/Dec-2017)
(May/June 2016) (Nov/Dec 2018) (Nov/Dec 2019)
3. Explain with all necessary sketches to enable intra communication among peripherals using
I2C BUS. (16) (Apr/May 2022) (Apr/May 2021) (Nov/Dec 2020) (Apr/May 2017)
(Nov/Dec 2016) (May/June 2016) (Apr/May 2018) (Nov/Dec-2017) (Nov/Dec 2018)
(Nov/Dec 2019) (Apr/May 2019)
4. Explain the functionalities of RS232 AND RS485 standard serial interface with neat
diagram. (16) (Nov/Dec 2021) (Apr/May 2022) (Nov/Dec 2020) (Apr/May 2017)
(May/June 2016) (Apr/May 2018)
5. Explain in detail about SPI communication protocol and its interfacing techniques. (16)
(Apr/May 2022) (Apr/May 2021) (Nov/Dec 2020) (May/June 2016) (Nov/Dec 2016)

UNIT 3
PART A
1. What is co-design and why it is important? (Nov/Dec 2019)
Co-design is the act of creating with stakeholders (business or customers) specifically
within the design development process to ensure the results meet their needs and are usable.
(Co-design may also be called participatory design- a term which is used more often within
the design community.)
2. Compare concurrent development model with object oriented model. (Apr/May 2019)
The concurrent development model concurrently executing task process. Sequential
execution leads to a single sequential execution of task and there by leads to poor processor
utilization, when a task involves I/O waiting, sleeping for specified duration etc. If the task is
split in to multiple subtasks, it is possible to tackle the CPU usage effectively, when the
subtask under execution goes to wait or sleep mode by switching the task execution.
However this model requires additional overheads in task scheduling, task synchronization
and communication
The object oriented model is an object based model for modeling system requirements. It
disseminates a complex software requirement into simple well defined pieces called objects.
Object oriented model brings re-usability, maintainability and productivity in system design.
In the object oriented modeling, object is an entity used for representing or modeling a
particular piece of the system. A class represent the state of an object through the member
variables and object behavior through member functions
3. Define and differentiate simulator and emulator in the context of embedded system.
(Apr/May 2018)
A simulator is an environment which models but an emulator is one that replicates the
usage as on the original device or system.
Simulator mimics the activity of something that it is simulating. It "appears"(a lot can go
with this "appears", depending on the context) to be the same as the thing being simulated.

4. Compare data flow and finite state model. (Apr/May 2022) (Apr/May 2018)
Data Flow Graph (DFG) model translates the data processing requirements into data
flow graph. It is a data driven model in which the program execution is determined by data.
Finite State Model (FSM) contains a number of states are finite. In other wards the
system is described using a finite number of possible states.

5. What is mean by DFG? (Nov/Dec 2017) (Nov/Dec 2018) (Nov/Dec 2019)

Data flow graph (DFG) model translates the data processing requirements into data flow
graph. It is a data driven model in which the program execution is determined by data.

6. What is state machine model? (Apr/May 2022) (Nov/Dec 2016) (Apr/May 2017) (Nov/Dec
2017) (Nov/Dec 2018)
State machine model is used for modeling reactive or event driven embedded systems
whose processing behavior are independent on state transitions
7. List the different phases of EDLC. (Apr/May 2017) (Apr/May 2019)
 Need
 Conceptualization
 Analysis
 Design
 Development and testing
 Deployment
 Support
 Upgrades
 Retirement
8. Mention different models used for the development of an embedded system. (May/June
2016)
 Linear or Waterfall Model
 Iterative or Fountain Model
 Prototype Model
 Spiral Model
Computational Models in Embedded Systems
 Data Flow Graph model
 State Machine Model
 Concurrent Process Model
 Sequential Program Model
 Object Oriented Model

9. What are the processes involved in co design? (May/June 2016) (Nov/Dec 2016)
 Selecting the model
 Selecting the architecture
 Selecting the language
 Portioning system requirement in to hardware and software

10. Compare sequential and concurrent program model. (Nov/Dec 2021)

Concurrency is about independent computations that can be executed in an arbitrary order
with the same outcome. The opposite of concurrent is sequential, meaning that sequential
computations depend on being executed step-by-step to produce correct results.

11. Classify the difference between state machine model and sequential model. (Apr/May 2021)
(Nov/Dec 2020)
A Sequential Logic function has a “memory” feature and takes into account past inputs in
order to decide on the output. The Finite State Machine is an abstract mathematical model of
a sequential logic function. It has finite inputs, outputs and number of states.

12. Draw the classic embedded product development life cycle model. (Apr/May 2021)
(Nov/Dec 2020)
13. What are the need for product plan phase? (Nov/Dec 2020)
Product planning is an essential process for companies that create, manufacture and sell
goods. Having a product development plan allows businesses to assess their current
customer demographics, identify markets for expansion and create product development
goals that help them gain, retain and serve their customers.

14. What is Control Data Flow Graph (CDFG)? (Nov/Dec 2020)

A CDFG uses a data flow graph as an element, adding constructs to describe control. In a
basic CDFG, we have two types of nodes: decision nodes and data flow nodes. A data flow
node encapsulates a complete data flow graph to represent a basic block.

PART B
1. What are the issues of hardware software and co-design? (5) (Apr/May 2022) (Apr/May
2018) (Apr/May 2019)
2. With a neat diagram explain the synchronous data flow graph model. (Apr/May 2021)
(Nov/Dec 2020) (Apr/May 2019)
3. Explain typical co-design process and the issues with hardware software and co-design.
(Apr/May 2021) (Nov/Dec 2020) (Nov/Dec-2019)
4. Explain the common computation models and illustrate the purpose of each. (13) (Apr/May
2018)
5. Enumerate state machine model for the seat belt alarm system. (16) (Apr/May 2022)
(Nov/Dec-2017) (Nov/Dec 2018)
6. (i) Write detailed notes on software and hardware interface techniques. (8) (Apr/May 2017)
(ii)Explain about sequential program model for the development of embedded platform. (8)
(Apr/May 2022) (Nov/Dec 2021) (Apr/May 2017)
7. Illustrate with functional description about different phases of Embedded Design Life Cycle
model. (16) (Apr/May 2022) (May/June 2016) (Nov/Dec 2016) (Apr/May 2018)
(Nov/Dec-2017) (Apr/May 2017) (Nov/Dec 2018) (Nov/Dec 2019) (Nov/Dec 2020)
8. With a suitable example, explain about the state machine model of a Automatic Chocolate
Vending Machine (ACVM) (16) (May/June 2016) (Nov/Dec 2016)
9. Design a concurrent model for the Seat Belt Warning System. (Apr/May 2022)
10. Design an object oriented model for ATM machine and explain its working with
necessary diagrams. (Apr/May 2022)

UNIT 4
PART A
1. What is RTOS? Name any two RTOS. (Nov/Dec 2019)
A real-time operating system (RTOS) is an operating system (OS) intended to serve real-
time applications that process data as it comes in, typically without buffer delays. Processing
time requirements (including any OS delay) are measured in tenths of seconds or shorter
increments of time. A real-time system is a time bound system which has well defined fixed
time constraints. Processing must be done within the defined constraints or the system will
fail. They either are event driven or time sharing.
 Examples for real time operating systems (RTOS) are VxWorks, µcos, Qnx, Rtlinux,
window embedded etc
2. Mention the different state of threads. (Apr/May 2019)
A thread can be in one of the following states:
 NEW. A thread that has not yet started is in this state.
 RUNNABLE. A thread executing in the Java virtual machine is in this state.
 BLOCKED. A thread that is blocked waiting for a monitor lock is in this state.
 WAITING.
 TIMED_WAITING.
 TERMINATED.

3. What is cause and effect of dead lock condition in RTOS? (Nov/Dec 2020) (Apr/May 2019)
Deadlock is a situation where a set of processes are blocked because each process is
holding a resource and waiting for another resource acquired by some other process. Hold
and Wait: A process is holding at least one resource and waiting for resources.

4. Define task and task state. (Apr/May 2022) (Apr/May 2018)

A task is a program that is within a process. It has the following states:
 Ready
 Running
 Blocked
 Idle
5. Compare user threads and kernel threads. (Apr/May 2018)
User threads -are supported above the kernel and are implemented by a thread library at the
user level
Kernel threads -are supported directly by the operating system.
User threads -Thread creation & scheduling are done in the user space, without kernel
intervention. Therefore they are fast to create and manage
Kernel threads -Thread creation, scheduling and management are done by the operating
system. Therefore they are slower to create & manage compared to user threads

6. Define semaphore signaling with syntax. (Nov/Dec 2017) (Nov/Dec 2016)

Semaphore is a sleep and wakeup based mutual exclusion for shared resources.
Semaphore is a system resource and the process which wants to access the shared resource
can first acquire this system object to indicate the other processes which wants the shared
resource that the shared resource is currently acquired by it.

Syntax
int sem_init(sem_t *sem, int pshared, unsigned int value);
#include <semaphore.h>
sem_t sem;
int pshared;
int ret;
int value;
/* initialize a private semaphore */
 pshared = 0;
value = 1;
ret = sem_init(&sem, pshared, value);

7. What do you understand by real-time scheduling? (Nov/Dec 2017) (Nov/Dec 2016)

The process scheduling in real-time is the activity of the process manager that handles
the removal of the running process from the CPU and the selection of another process on the
basis of a particular strategy. Process scheduling is an essential part of Multiprogramming
operating systems.

8. Define multithreading. (Apr/May 2017)

Multithreading is the ability of a program or an operating system process to manage its
use by more than one user at a time and to even manage multiple requests by the same user
without having to have multiple copies of the programming running in the computer.

9. What are the functions of RTOS? (Apr/May 2017) (Nov/Dec 2016)

The primary function of the real time operating system is to manage certain system
resources, such as the CPU, memory, and time.

10. Compare preemptive and non preemptive scheduling. (Apr/May 2021) (Nov/Dec 2020)
(Apr/May 2022) (Nov/Dec 2016) (May/June 2016) (Nov/Dec 2019)
In Preemptive Scheduling every task in the ready queue gets a chance to execute. When
and how often each process get a chance to execute is dependent on the types of preemptive
scheduling algorithm used for scheduling the process.
Types
 Shortest Remaining Time Scheduling
 Round Robin Scheduling
 Priority Based Scheduling
In Preemptive Scheduling the currently executing task/ process is allowed to run until it
terminates or enters the wait state for an I/O or system resource.
Types
 First Come First Served Scheduling
 Last Come Last Served Scheduling
 Shortest Job first Scheduling
 Priority Based Scheduling

11. Define thread and process. (May/June 2016)

A process is a program that performs a specific function.
A thread otherwise called a lightweight process (LWP) is a basic unit of CPU utilization,
it comprises of a thread id, a program counter, a register set and a stack. It shares with other
threads belonging to the same process its code section, data section, and operating system
resources such as open files and signals.

12. What is mean by priority inversion? (Nov/Dec 2021)

Priority inversion is a bug that occurs when a high priority task is indirectly preempted by
a low priority task. For example, the low priority task holds a mutex that the high priority
task must wait for to continue executing.
13. Consider the task list shown in the table. Determine the average waiting time using priority
scheduling. (Nov/Dec 2021)
Task No Execution Time Priority
T1 300 5
T2 125 3
T3 400 2
T4 150 12
T5 100 15

14. Justify the advantages of mail boxes in RTOS. (Apr/May 2021) (Nov/Dec 2020)
A mailbox is simply a storage location, big enough to hold a single variable of type
ADDR, access to which is controlled so that it may be safely utilized by multiple tasks. One
task can write to a mailbox. It is then full, and no task can send to it until a task does a read
on the mailbox or the mailbox is reset.
15. What are count if semaphore in real time operating system? (Nov/Dec 2020)
A counting semaphore is a semaphore that has multiple values of the counter. The value
can range over an unrestricted domain. It is a structure, which comprises a variable, known as
a semaphore variable that can take more than two values and a list of task or entity, which is
nothing but the process or the thread.
16. Why is inter process communication using message is advantage? (Nov/Dec 2020)
Inter process communication allows one application to manage another and enables
glitch-free data sharing. Inter process communication helps send messages efficiently
between processes.

PART B
1. i) Explain any two mechanisms for inter-task/inter process communication in RTOS µC/OS-
II. (8) (Nov/Dec 2019)
ii) Write RT Linux program to display the message “welcome” once in every seconds. (5)
(Nov/Dec 2019)
2. Explain briefly the problem of priority inversion and inheritance and mechanism to prevent
the same. (13) (Nov/Dec 2021) (Nov/Dec 2019)
3. (i)Summarize the system level and task service functions of microcontroller/OS. (6)
(Apr/May 2018)
(ii) Draw the microkernel architecture and explain the basic function of RTOS kernel. (6)
(Apr/May 2018)
4. Explain Task, Process and Thread with their types and examples. (16 ) (Nov/Dec-2017)
(Nov/Dec 2018) (Apr/May 2019)
5. Describe rate monotonic scheduling with examples. (16) (Nov/Dec-2017) (Nov/Dec 2018)
(Apr/May 2019)
6. Explain in detail about the inter process communication and context switching. (16)
(Apr/May 2022) (Apr/May 2017) (Apr/May 2018) (Nov/Dec 2016)
7. Explain in detail the features and scheduling algorithm used in microcontroller/OS-2 RTOS.
(16) (Apr/May 2017)
8. Explain how the interrupt routines are handled by RTOS and illustrate the features of µC/ OS
II RTOS and VxWorks. (16) (Nov/Dec 2016) (May/June 2016)
9. Explain the terminologies Semaphores, Mail box, Pipes Shared memory in RTOS. (16 )
(Apr/May 2022) (Nov/Dec 2020) (May/June 2016) (Apr/May 2018) (Apr/May 2019)

UNIT 5
PART A
1. Differentiate between hard and soft real time systems. (Nov/Dec 2019)
The key difference between hard and soft real time system is that, a hard-real time
system is a system in which a single failure to meet the deadline may lead to a
complete system failure while a soft real time system is a system in which one or more
failures to meet the deadline is not considered as complete system.

2. What is smart card? (Nov/Dec 2019)

A smart card, chip card, or integrated circuit card (ICC) is a physical electronic
authorization device, used to control access to a resource. Smart cards can provide personal
identification, authentication, data storage, and application processing.

3. State any three features that are required in the software used in automotive applications.
(Apr/May 2019)
A complete Software Requirement Specifications must be:
 Clear.
 Correct.
 Consistent.
 Coherent.
 Comprehensible.
 Modifiable.
 Verifiable.
 Prioritized.

4. Why is critical Tasks given high priority in comparison to ordinary tasks during embedded
automobile application development? (Apr/May 2019)
In automobile application development, critical tasks are tasks on the longest path. These
tasks are considered critical because there is no slack time (zero float) and they are generally
considered to determine the total duration of a project. The tasks on the feeder path which
has some slack are considered non-critical tasks. It is believed that delaying work on critical
tasks damages the project time line. So, project managers tend to focus on ensuring minimal
delays on the critical path. In planning, efforts are also made to move tasks away from the
longest path and into feeder path to crash lead-times. And, in execution, faced with a choice,
priority is given to the needs of the critical tasks even at the cost of delays on the feeder path.

5. List any four applications of microcontroller operating system MUCOS. (Apr/May 2018)
 Consumer Electronics Products: Toys, Cameras, Robots, Washing Machine,
Microwave Ovens etc.
 Instrumentation and Process Control: Oscilloscopes, Multi-meter, Leakage
Current Tester, Data Acquisition and Control etc.
  Medical Instruments
 Communication
 Multimedia Application
 Automobile

6. Classify Electronic Control Unit (ECU) and its uses. (Apr/May 2022) (Apr/May 2018)
 High Speed Electronic Control Unit (HPECU)
 Low Speed Electronic Control Unit (LPECU)

7. Mention any four real time embedded processor based applications. (Nov/Dec 2017)
(Apr/May 2017) (Nov/Dec 2016) (May/June 2016) (Nov/Dec 2016)
 Automatic Chocolate Vending Machine
 Washing machine
 Smart Card System Application
 Data compressor
 Digital Still Camera
 Automobile
 Telephone Answering Machine
 Video Accelerator

8. What are the basic requirements while designing embedded systems? (Nov/Dec 2017)
(Nov/Dec 2016)
 Available system memory
 Available processor speed
 Limit power dissipation

9. Draw the system components in the smart card. (Apr/May 2017)

10. What are the events involved in smart card application? (Nov/Dec 2016) (May/June 2016)
 Task-Reset
 Task- Read port
 Task-Password
 Task-Application
11. List any six, key players of the automotive embedded market. (Apr/May 2022)
Key players operating in the global embedded system for automotive market include
Robert Bosch GmbH, Continental AG, Denso Corporation, Panasonic Corporation, Delphi
Technologies, Infineon Technologies AG, and NXP Semiconductors.

12. Distinguish between CAN and LIN automotive communication buses. (Nov/Dec 2021)
LIN and CAN don't compete with each other, but instead complement one another. On
the one hand, CAN serves high-speed, error-sensitive needs and operates on a 5-V
differential bus. LIN, however, serves low-speed, low-bandwidth requirements on a 12-V
single-wire bus.

13. Draw the building blocks of a digital camera. (Nov/Dec 2021)

14. Mention the importance of input interface and output interface in washing machine.
(Apr/May 2021) (Nov/Dec 2020)
The main purpose of the I/O interfaces is to transmit and receive data; however, the
portion designated as an I/O interface may contain additional resources, such as voltage
translators, registers, impedances, and buffers.
The inputs of washing machine are water, clothes, detergent, electricity and the output is
the washed and cleaned clothes.

17. State the role of interfacing I/O circuit in smart card. (Apr/May 2021) (Nov/Dec 2020)
The I/O contact on a smart card is used as an input (reception mode) to receive data from
the terminal or as an output (transmission mode) to transmit data to the terminal.

18. Give 2 reasons for use of firmware for implementation of embedded systems. (Nov/Dec
2020)
Embedded firmware is used to control the limited, set functions of hardware devices and
systems of greater complexity but still gives more appliance-like usage instead of a series of
terminal commands. Embedded firmware functions are activated by external controls or
external actions of the hardware.

PART B
1. i) What are the key factors to be considered for selecting an RTOS for embedded
applications? (Nov/Dec 2019)
ii) Describe any four major areas os embedded system applications. (Nov/Dec 2019)
2. Design the architectural hardware and software units needed in Smart Card. (13/16)
(Apr/May 2022) (Nov/Dec 2021) (Apr/May 2021) (Nov/Dec 2020) (Apr/May 2018)
(Nov/Dec-2017) (Apr/May 2017) (Nov/Dec 2016) (May/June 2016) (Nov/Dec 2018)
(Nov/Dec 2019) (Apr/May 2019)
3. Identify and explain the hardware units needed in each of the system
(a) Camera (7)
(b) Automatic Chocolate Vending Machine (6) (Nov/Dec 2021) (Nov/Dec 2020) (Apr/May
2018)
4. Design and discuss an embedded system solution for a typical automotive system. Your
answer must include design and development of necessary hardware’s and software for the
automotive system to incorporate efficient fuel management systems, vehicle performance
monitoring systems, vehicle tracking and navigation systems (PART C) (15) (Apr/May
2021) (Nov/Dec 2020) (Apr/May 2018)
5. Brief about the case study on adaptive cruise control in an automobile with class diagram.
(16) (Nov/Dec-2017) (Nov/Dec 2018) (Nov/Dec 2019)
6. With suitable diagram explain in detail about the concept of Washing Machine application.
(16) (Apr/May 2022) (Nov/Dec 2021) (Nov/Dec 2020) (Nov/Dec 2016) (May/June 2016)
(Nov/Dec 2018) (Nov/Dec 2019) (Apr/May 2019)
7. Write the requirements, Input, Output, Hardware Architecture and Software components for
designing a digital camera. (Nov/Dec 2020)