COMSATS University Islamabad (CUI), Lahore Campus Department of

Electrical & Computer Engineering

EEE241 – Digital Logic Design

Lab Manual for Fall 2024

Lab Resource Persons

Ma’am Zainab Akhtar

Theory Resource Persons

Dr. Zaid Ahmed
Presented by Group No 2

Sr. # Name Registration Number

1 Muhammad Munaeem FA23-BSE-126

FA23-BSE-088
2 Mubeen Ahmad

3 Muhammad Hassan FA23-BSE-117

FA23-BSE-205
4 Hadeeq

|EEE 241 | Digital Logic Design Lab Manual

 ii
Preface
Digital Logic Design is among the core courses of Electrical Engineering presenting basic tools for the design
of digital circuits. It serves as a building block in many disciplines that utilize and manipulate digital information
such as microprocessor-based systems, computer organizations and architecture, digital systems design, digital
control and digital communications etc.
This document has been prepared to serve as a laboratory manual for EEE 241 Digital Logic Design course for
electrical engineering students at CIIT Lahore. The manual consists of a set of experiments designed to allow
students to build, and verify digital circuits and systems. This set of experiments cover relevant topics prescribed
in the syllabus and are designed to reinforce the theoretical concepts taught in the classroom with practical
experience in the lab. By the end of the course, students are expected to have a good understanding of digital
logic design and its implementation using ICs for basic logic gates and simple circuits.

Acknowledgement
Contribution of the following faculty members is highly appreciated:
 Engr. Syed Junaid Akhtar
 Engr. Wajeeha Khan
 Engr. Sara Sajid
 Engr. Abdul Moeed

|EEE 241 | Digital Logic Design Lab Manual ii

  Engr. Hasnain Kashif
 Engr. Arslan Khalid
 Engr. Nesruminallah

 Engr. Arfa Tariq

 Engr. Sarmad Hassan

Books
Text Books

1. Digital Design, 5th Edition by Morris Mano & Michael D. Ciletti

Reference Books

1. Introduction to Logic Design, 2nd Edition by Alan B. Marcovitz

2. Thomas L. Floyd, Digital Fundamentals (7th Edition)
Learning Outcomes
• To get hands on experience of implementation of logic circuits using logic ICs, trainer and
breadboards. • To get familiar with the process of digital logic design (Combinational &
Sequential logic)
• To be able to design digital logic circuit in application software.
• To be able to analyze the experimental results and to compare them with the theoretical
knowledge.
• Ability to implement the Boolean functions using basic as well as universal gates.
• Ability to translate real-world problem into logic equations and logic diagrams.

Theory CLOs:

1. CLO1: Comprehend the working with different number systems, Boolean algebra and mapping methods
using standard mathematical rules. (PLO1-C2)
2. CLO2: Analyze the working of combinational and sequential logic circuits using digital logic principles
and Boolean algebra. (PLO2-C4)
3. CLO3: Plan and design the combinational and sequential logic circuits using digital logic principles,
Boolean algebra and mapping methods. (PLO3-C5)

Lab CLOs:

4. CLO4: To analyze and design the combinational and sequential logic circuits using software and
hardware platforms. (PLO3-C5)
5. CLO5: Follow the software and hardware tools to reproduce the response of the digital logic circuits
using software and hardware platforms. (PLO5-P3)
6. CLO6: To explain and write effective lab reports of experiments performed during lab (PLO10-A3)

|EEE 241 | Digital Logic Design Lab Manual iii

 7. CLO7: To demonstrate the working of a digital logic circuit designed individually and by the teamwork
using software and hardware platforms. (PLO9-A3)
CLOs – PLOs Mapping

Lab CLOs – Lab Experiment Mapping

Grading Policy
The final marks for lab would comprise of Lab Assessment (25%), Lab S1 (10%), Lab S2 (15 %) and Lab
Terminal (50%).

S-I 0.5*(S-I Exam result) + 0.5* (average of lab evaluation of Lab 1-4)
S-II 0.5*(S-II Exam result) + 0.5*[ (average of lab evaluation of Lab 5-8) * 1.5]
Terminal 0.1*[(OEP marks out of 25)*2] +0.4*(Terminal Exam result out of 50) +0.25*[(average of
lab evaluation of Lab 9-12) *5] + 0.10*[(average of lab evaluation of Lab 5-8) *5] + 0.15*[(average
of lab evaluation of Lab 1-4) *5]

Lab Assignment Marks:

• Lab Assignment 1 marks = Lab report marks from experiment 1-3. • Lab Assignment 2 marks =
Lab report marks from experiment 4-6.
• Lab Assignment 3 marks = Lab report marks from experiment 7-9.
• Lab Assignment 4 marks = Lab report marks from experiment 10-14.

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 The minimum pass marks for both lab and theory shall be 50%. Students obtaining less than 50% marks
(in either theory or lab, or both) shall be deemed to have failed in the course. The final marks would be
computed with 75% weight to theory and 25% to lab final marks.
List of Equipment
IC 7400 (NAND Gate), IC 7402 (NOR Gate), IC 7404 (NOT Gate), IC 7408 (AND Gate), IC 7432 (OR Gate),
IC 7447 (BCD to 7seg), IC 7486 (X-OR Gate), IC 74138 (De-multiplexer), IC 74148 (Encoder), IC 7420 (4
Input NAND GATE), IC 7474 (D Flip Flop), IC 7476 (J-K Flip Flop), IC 74147 (10 to 4 Line Encoder), IC
74139 (2 Line to 4 Decoder), IC 74153 (Dual Multiplexer 1 of 4), IC 74157 (quadruple 1 of 2 Data selector),
IC 7485 (4-Bit Comparator), IC 7495 (4-Bit Shift Register), 7483 (4-Bit Adder), Trainer Board

Software Resources
Proteus Professional 6.9

Lab Instructions
• This lab activity comprises of three parts: Pre-lab, Lab Tasks, Post Lab Tasks, Lab Report and
Conclusion and Viva session.
• The students should perform and demonstrate each lab task separately for step-wise evaluation.
• Only those tasks that are completed during the allocated lab time will be credited to the students.
• Students are however encouraged to practice on their own in spare time for enhancing their skills.

Lab Report Instructions

All questions should be answered precisely to get maximum credit. Lab report must ensure following items:
• Lab Objectives
• Methodology
• Conclusion

Laboratory Regulations and Safety Rules

The following Regulations and Safety Rules must be observed in all concerned laboratory location.
1) It is the duty of all concerned who use any electrical laboratory to take all reasonable steps to safeguard
the HEALTH and SAFETY of themselves and all other users and visitors.
2) Be sure that all equipment is properly working before using them for laboratory exercises. Any defective
equipment must be reported immediately to the Lab. Instructors or Lab. Technical Staff.
3) Students are allowed to use only the equipment provided in the experiment manual.
4) Power supply terminals connected to any circuit are only energized with the presence of the Instructor
Lab. Staff.
5) Avoid any part of your body to be connected to the energized circuit and ground.
6) Switch off the equipment and disconnect the power supplies from the circuit before leaving the
laboratory.

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 7) Observe cleanliness and proper laboratory housekeeping of the equipment and other related accessories.
8) Make sure that the last connection to be made in your circuit is the power supply and first thing to be
disconnected is also the power supply.
9) Equipment should not be removed, transferred to any location without permission from the laboratory
staff.
10) Students are not allowed to use any equipment without proper orientation and actual hands on
equipment operation.
11) Smoking and drinking in the laboratory are not permitted.
All these rules and regulations are necessary precaution in Electronic Laboratory to safeguard the students,
laboratory staff, the equipment and other laboratory users.

|EEE 241 | Digital Logic Design Lab Manual vi

 Table of Contents
Revision History i

Preface ii

Acknowledgement ii

Books iii

Learning Outcomes iii

CLOs – PLOs Mapping iv

Lab CLOs – Lab Experiment Mapping iv

Grading Policy iv

List of Equipment v

Software Resources v

Lab Instructions v

Lab Report Instructions v

Laboratory Regulations and Safety Rules v

Table of Contents vii

LAB # 1: To Identify the Responses of Different Logic Gates using Hardware and Software Platforms 11

Objectives 11

Pre Lab 11

Part A -Familiarize yourself with Logic Gates 11

In- Lab 12

Post LAB: 21

LAB # 2: To Explain the Universality of NAND and NOR GATES in Order to Design Other Logic Gates 23

Objectives 23

Pre-Lab: 23

In-Lab 23

Post-Lab: 28

LAB # 3: To Show the output of simplified Boolean Expression by following the k-map, using Hardware and

Software Platforms 30

Objectives 30

Pre-Lab 30

Part 1 -Introduction to simplify the Boolean Expression 30

In-Lab 31

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i
 Post-Lab
34
LAB # 4: To Show the Behaviour of Binary Adder/Subtractor and reproduce its circuit using Universal Gates 36

Objectives 36
Pre-Lab 36
Part 1 -Familiarize yourself with Half Adder & Full Adder 36
In-Lab 37
Post-Lab: 43
LAB # 5: To Follow the Steps of BCD to Excess 3 Code Conversion and Reproduce the Results using Dedicated IC
45
Objectives 45
Pre Lab 45
Part 1 -Familiarize yourself with BDC to Excess-3 45
Part 2 -Familiarize yourself with Excess-3 to BCD 45
In Lab 45
Post Lab 45
LAB # 6: To Follow the Steps of Binary to Gray Code Conversion and Reproduce the Results using Logic Gates 49
Objectives 49
Pre Lab 49
In-Lab 49
Post Lab: 53

LAB: 7 To Show the Response of a Multiplexer/Demultiplexer and to Reproduce Adder/Subtractor using

Multiplexer 55
Objectives 55
Pre Lab 55
Part 1 -Familiarize yourself with Multiplexers 55
Part 2 -Familiarize yourself with Demultiplexers 55
In lab 55
Post Lab: 63
LAB # 8: To Show the response of Binary Comparator(s) using hardware and software tools and to Reproduce
the Comparator using dedicated IC 65
Objectives 65
Pre Lab 65
Part 1 -Familiarize yourself with Comparators 65
In Lab: 65

Post Lab: 68

LAB # 9: To Show the response of an Encoder/Decoder and to Reproduce the binary converters using basic logic
gates 70

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ii
 Objectives 70
Pre Lab 70
Part 1 - To realize a decoder circuit using basic gates and to verify IC 74LS139 70
Part 2 - To set up and test a 7-segment static display system to display numbers 0 to 9 70
In Lab 70
Post Lab:
77
LAB # 10: To Identify the Response of Sequential Circuit(s) using Hardware and Software Platforms 79

Objectives 79
Pre Lab 79
In Lab 79
Post Lab: 83
LAB # 11: To show the Response of Shift Registers using 7495 IC and Reproduce the shift registers using D-Flip-
Flops 85
Objectives 86
Pre Lab 86
In Lab 86
Post Lab
87
LAB # 12: To Reproduce a Synchronous Sequence Detector using hardware and software tools 89

Objectives 89
Pre Lab 89
In Lab 89
Post Lab
89
LAB # 13: To Show the Response of Ring and Johnson Counter using 7495 IC 94

Objectives 94
Pre Lab 94
In Lab 94
Post Lab
95
LAB # 14: To Reproduce the Asynchronous Counters using hardware and software tools 97

Objectives 97
Pre Lab 97
Part 1 -Familiarize yourself with Asynchronous Counter: 97
Part 2 -Familiarize yourself with Synchronous Counter: 97
In Lab: 97

Post Lab 103

|EEE 241 | Digital Logic Design Lab Manual ix

LAB # 1: To Identify the Responses of Different Logic Gates using Hardware and
Software Platforms
Objectives

∙ To identify the basic Boolean functions of logic gates

∙ To identify various ICs used in proteus software and to perform basic functionality of
logic gates

Pre Lab

Part A -Familiarize yourself with Logic Gates

The basic logic gates are the building blocks of more complex logic circuits. These logic gates
perform the basic Boolean functions, such as AND, OR, NAND, NOR, Inversion, ExclusiveOR,
Exclusive-NOR. The circuit symbols are shown below with their Boolean functions, and truth
Tables. It can be depicted from the given symbols that each gate has one or two binary inputs, A
and B, and one binary output, C. The small circle on the output of the circuit symbols designates
the logic complement. The AND, OR, NAND, and NOR gates can be extended to have more
than two inputs. A gate can be extended to have multiple inputs if the binary operation it
represents is commutative and associative.

These basic logic gates are implemented as small-scale integrated circuits (SSICs) or as part of
more complex medium scale (MSI) or very large-scale (VLSI) integrated circuits. Digital IC
gates are classified not only by their logic operation, but also the specific logic-circuit family to
which they belong. Each logic family has its own basic electronic circuit upon which more
complex digital circuits and functions are developed. The following logic families are the most
frequently used.

∙ TTL Transistor-transistor logic

∙ ECL Emitter-coupled logic
∙ MOS Metal-oxide semiconductor
∙ CMOS Complementary metal-oxide semiconductor

TTL and ECL are based upon bipolar transistors. TTL has a well-established popularity among
logic families. ECL is used only in systems requiring high-speed operation. MOS and CMOS,
are based on field effect transistors. They are widely used in large scale integrated circuits
because of their high component density and relatively low power consumption. CMOS logic
consumes far less power than MOS logic. There are various commercial integrated circuit chips
available. TTL ICs are usually distinguished by numerical designation as the 5400 and 7400
series.

Read and understand pin configuration and list the truth tables of AND, OR, NOT, NAND,

|EEE 241 | Digital Logic Design Lab Manual i

NOR and XOR gates.

In- Lab

Lab Tasks-Part-A
Study and verify the truth table of logic gates

Lab Task 1:
0 1 1
IC 7400 NAND gate

1 0 1

1 1 0
Fig:
1.1
0 0 1

Table:
1.1
Inputs Output

Lab Task 2: A B
IC 7408 AND gate

0 0 0

0 1 0

Fig: 1.2
1 0 0
Inputs Output

A B 1 1 1

0 0 Table: 1.2

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Lab Task 3:
A

IC 7404 NOT gate

0 1

1 0

Fig: 1.3
Table:
1.3
Inputs Output

Lab Task 4: A B

IC 7402 NOR gate

0 0 1

0 1 0

1 0 0
Fig: 1.4

1 1 0

Lab Task 5: Table: 1.4

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 Inputs Output
IC 7432 OR gate

A B

0 0 0
Fig: 1.5
Input Output 0 1 1
Table: 1.5

1 1 1 1 0 1

Lab Task 6:

IC 7486 XOR gate

Fig: 1.6

Part B -Familiarize yourself with PROTEUS

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 Inputs Output

A B

0 0 0
Table: 1.6

0 1 1

Proteus is a software for microprocessor simulation, schematic

capture, and printed circuit board (PCB) design. It is developed
1 0 1
by Labcenter Electronics.

ISIS Schematic Capture - a tool for entering designs.

1 1 0
PROSPICE Mixed mode SPICE simulation - industry
standard SPICE3F5 simulator combined with a digital
simulator.

ARES PCB Layout - PCB design system with automatic component placer, rip-up and retry auto-router
and interactive design rule checking.

VSM - Virtual System Modelling lets co-simulate embedded software for popular micro controllers
alongside hardware design.

System Benefits

Integrated package with common user interface and fully context sensitive help. But we only use
the ISIS Schematic Capture

In Lab:

Lab Tasks-Part-B

Right click on the ISIS icon present on desktop and then open it.

Fig: 1.7

The window below will be shown

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 Fig: 1.8

Lab Task 1:

Implementation of AND gate on Proteus

A B

0 0 0

0 1 0
Fig: 1.9
1 0 0

1 1 1

Take the components From Library by pressing Table: 1.7 the

tab “Library”
Inputs Output

Fig: 1.10

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Search the Components by names and then click OK to adding them in Devices Panel

Fig: 1.11
Connect the components and save the design by specific name

Fig: 1.12

Press the “start” button to execute the design and verify the results

Fig: 1.13
Repeat the same procedure for the followings Gates.

Lab Task 2:

Implementation of OR gate on Proteus

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 Inputs Output

A B

Fig: 1.14
0 0 0

0 1 1

1 0 1

1 1 1

Table: 1

Fig: 1.15 Lab

Task 3:

Implementation of NOT gate on Proteus

Lab Task 4:

|EEE 241 | Digital Logic Design Lab Manual v

Implementation of NAND gate on Proteus

Inputs Output

A B

0 0 1

0 1 1

1 0 1

1 1 0

Lab Task 5:

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 Inputs Output

A B

0 0 O

0 1 1

1 0 1

1 1 0

Implementation of XOR gate on Proteus

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|EEE 241 | Digital Logic Design Lab Manual x
Post Lab:

Draw the schematic for following logic circuit in Proteus and fill in the table. Answer the
questions at the end.

A B C D F1 F2

0 0 0 0 0 0

0 0 0 1 1 1

0 0 1 0 1 0

0 0 1 1 1 1

0 1 0 0 1 1

0 1 0 1 0 1

0 1 1 0 1 1

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0 1 1 1 0 1

1 0 0 0 1 0

1 0 0 1 1 1

1 0 1 0 1 0

1 0 1 1 1 1

1 1 0 0 1 0

1 1 0 1 1 1

1 1 1 0 1 0

1 1 1 1 1 1

Table: 1.12

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 Post LAB:
Design XOR and XNOR circuits using AND, NOT and OR gates.

XOR:

XNOR:

|EEE 241 | Digital Logic Design Lab Manual 14

 Rubric for Lab Assessment

The student performance for the assigned task during the lab session was:

Excellent The student completed assigned tasks without any help from the 4
instructor and showed the results appropriately.

Good The student completed assigned tasks with minimal help from 3
the instructor and showed the results appropriately.

Average The student could not complete all assigned tasks and showed 2
partial results.

Worst The student did not complete assigned tasks. 1

|EEE 241 | Digital Logic Design Lab Manual 15

 Instructor Signature: _______________________ Date: ____________________

LAB # 2: To Explain the Universality of NAND and NOR

GATES in Order to Design Other Logic Gates
Objectives

∙ To construct various logic gates using NAND gates

∙ To construct various logic gates using NOR gates

Pre-Lab:

Background theory:
Digital circuits are more frequently constructed with NAND or NOR gates than with AND and OR
gates. NAND and NOR gates are easier to fabricate with electronic components and are the basic
gates used in all IC digital logic families. Because of the prominence of NAND and NOR gates in

|EEE 241 | Digital Logic Design Lab Manual 16

the design of digital circuits, rules and procedures have been developed for conversion from
Boolean function given in terms of AND, OR, and NOT into equivalent NAND and NOR logic
diagram.

Read and understand the universal gates also list the truth tables of AND, OR, NOT, NAND, NOR
and XOR gates.

In-Lab

Part 1 - Implementing any logic expression by using only NAND gates

If we can show that the logical operations AND, OR, and NOT can be implemented with NAND
gates, then it can be safely assumed that any Boolean function can be implemented with NAND
gates. Figure-1 below shows such implementation: -

Procedure

✔ Insert the IC on the trainer’s breadboard.

✔ Use any one or more of the NAND gates of the IC for this experiment.

✔ Any one or more Logic Switches of the trainer (S1 to S9) can be used for input to the NAND gate.

✔ For output indication, connect the output pin of the circuit to any one of the LEDs of the trainer (L0 to
L15).
Lab Tasks-Part-1
Lab Task 1:

Verification of AND function

✔ Connect the circuit as per figure 1(a) above.

✔ Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.

|EEE 241 | Digital Logic Design Lab Manual 17

✔ By setting the switches to 1 and 0, verify that the output of the circuit conforms to that of an AND

Lab Task 2

Verification of OR function

✔ Connect the circuit as per Figure 1(b).

✔ Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.

✔ By setting the switches to 1 and 0, verify that the output of the circuit conforms to that of an OR gate. Record
your observation in the table below
A B output
0 0 0
0 1 0
1 0 0
1 1 1

gate. Recor

|EEE 241 | Digital Logic Design Lab Manual 18

 Inputs Outputs

A B

0 0 0

0 1 1

|EEE 241 | Digital Logic Design Lab Manual 19

 1 0 1

1 1 1

Table: 2.2

Lab task 3

Verification of NOT function

✔ Connect the circuit as per Figure 1 (c)

✔ Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.

✔ By setting the switch to 1 and 0, verify that the output of the circuit conforms to that of a NOT gate. Record

your observation in the table belo

Output
Input

|EEE 241 | Digital Logic Design Lab Manual 20

 A

0 1

1 0

Table: 2.3
Part 2 - Implementing any logic expression by using only NOR gates
NOR function is the dual of the NAND function, hence all procedure and rules for NOR logic form a
dual of the corresponding procedures and rules developed for the NAND logic. Figure
2.1 below shows how NOR gates can be used to create AND, OR, and INVERTER gates.

Procedure

✔ Insert IC on the trainer’s bread board.

✔ Use any one or more of the NOR gates of the IC for this experiment.

✔ Any one or more Logic Switches of the trainer (S2 to S9) can be used for input to the NOR gate.

✔ For output indication, connect the output pin of the circuit to any one of the LEDs of the trainer (L0 to
L15).

Lab Tasks-Part-2
Lab Task 1:

Verification of AND function

✔ Connect the circuit as per Figure 1 (a)

✔ Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.
✔ By setting the switches to 1 and 0, verify that the output of the circuit conforms to that of an AND
gate. Record your observation in the table below

|EEE 241 | Digital Logic Design Lab Manual 21

 Input Outputs

0 0 0

0 1 0

1 0 0

1 1 1

Lab task 2:

Verification of OR function

✔ Connect the circuit as per Figure 1 (b)

✔ Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.
✔ By setting the switches to 1 and 0, verify that the output of the circuit conforms to that of an OR gate.
Record your observation in the table below

|EEE 241 | Digital Logic Design Lab Manual 22

 Input Outputs

0 0 0

0 1 1

1 0 1

1 1 1

Lab task 3

Verification of NOT function

✔ Connect the circuit as per Figure 1 (c)

✔ Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.

Inputs A Outputs
A’
0 1
1 0

✔ By setting the switch to 1 and 0, verify that the output of the circuit conforms to that of an
NOT gate. Record your observation in the table below

|EEE 241 | Digital Logic Design Lab Manual 23

Post-Lab:
1- Design NOR, XOR and XNOR gate Using NAND gate only.

NOR Gate:

XOR GATE:

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 XNOR Gate:

2- Design NAND, XOR and XNOR gate Using NOR gate only.

NAND Gate:

XOR GATE:

|EEE 241 | Digital Logic Design Lab Manual 25

XNOR GATE:

Rubric for Lab Assessment

|EEE 241 | Digital Logic Design Lab Manual 26

 The student performance for the assigned task during the lab session was:
The student completed assigned tasks without any help from the
Excellent 4
instructor and showed the results appropriately.
The student completed assigned tasks with minimal help from the
Good 3
instructor and showed the results appropriately.
The student could not complete all assigned tasks and showed
Average 2
partial results.

Worst The student did not complete assigned tasks. 1

Instructor Signature: Date:

|EEE 241 | Digital Logic Design Lab Manual 27

 LAB # 3: To Show the output of simplified Boolean Expression by
following the k-map, using Hardware and Software Platforms
Objectives
Part 1

• To display the Boolean expression in its simplified form using Karnaugh map

• To display the results of simplified Boolean expression using hardware and software
platforms

• To show simplified Boolean expression using universal gates Pre-Lab

Part 1 -Introduction to simplify the Boolean Expression

Canonical Forms (Normal Forms): Any Boolean function can be written in disjunctive normal form
(sum of min-terms) or conjunctive normal form (product of max-terms).

A Boolean function can be represented by a Karnaugh map in which each cell corresponds to a
minterm. The cells are arranged in such a way that any two immediately adjacent cells correspond
to two minterms of distance 1. There is more than one way to construct a map with this property.

Karnaugh Maps
For a function of two variables, say, 𝑓 (𝑥, 𝑦),

For a function of three variables, say, 𝑓(𝑥, 𝑦, 𝑧)

For a function of four variable 𝑓(𝑤, 𝑥, 𝑦, 𝑧)

|EEE 241 | Digital Logic Design Lab Manual 28

Read and understand the methods for simplification of Boolean function. List a truth table,
derive its Boolean expression and use K-Map for simplification of the derived Boolean
expression.

In-Lab Lab

Tasks-Part-1

Lab Task 1:
Realization of Boolean expression:

TRUTH TABLE

INPUTS OUTPUT

A B C D Y
0 0 0 0 0

0 0 0 1 0

0 0 1 0 1

0 0 1 1 0

0 1 0 0 0

0 1 0 1 0

0 1 1 0 1

0 1 1 1 0

1 0 0 0 1

1 0 0 1 1

1 0 1 0 1

1 0 1 1 1

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 1 1 0 0 0

1 1 0 1 0

1 1 1 0 1

1 1 1 1 0
Table: 3.1
Y= A'B'CD' + A'BCD' + AB'C'D' + AB'C'D + AB'CD' + AB'CD + ABCD'

CD AB

1 1 1 1

𝑌 = 𝐴𝐵′ + 𝐶 𝐷'

Lab Task 2:

For the given truth table simplify the Boolean expression by using K-Map

Truth Table

Inputs Output
A B C D Y
0 0 0 0 1
0 0 0 1 1
0 0 1 0 0
0 0 1 1 0
0 1 0 0 1
0 1 0 1 1
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1

|EEE 241 | Digital Logic Design Lab Manual 30

 1 1 1 0 0
1 1 1 1 1
Table: 3.2
Karnaugh Maps:

Simplified Boolean Expression:

Part 2 –Boolean Expression using Basic gates

Lab Tasks-Part-2
Lab Task 1:
Implement the following simplified function by using basic gates as mention in Task 1 Part 1

𝑌 = 𝐴𝐵′ + 𝐶 𝐷'

|EEE 241 | Digital Logic Design Lab Manual 31

 Fig: 3.1
Lab Task 2:

Implement the Task 2 of Part 1 by using basic gate

Part 3 –Boolean Expression using Universal gates (NAND & NOR)

A universal gate is a gate which can implement any Boolean function without need to use any
other gate type. The NAND and NOR gates are universal gates. In practice, this is advantageous
since NAND and NOR gates are economical and easier to fabricate and are the basic gates used
in all IC digital logic families.
In-Lab Data (Hardware Implementation) Part
1:
Task 1:
Y= AB'CD' + A'BCD' + AB'C'D' + AB'C'D + AB'CD' + AB'CD + ABCD' Simplified
Boolean Expression:
AB'+CD'
Truth Table for Hardware Testing:
Expected Observed
A B C D
Y Y
0 0 0 0 0 0
0 0 0 1 0 0
0 0 1 0 1 1
0 0 1 1 0 0
0 1 1 0 1 1
1 0 0 0 1 1
1 0 1 0 1 1
1 1 1 1 0 0

Part 2:
Task 1:

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Task 2:

Post-Lab
Implement the Task 2 of Part 1 by using universal gates (NAND & NOR).

Post-Lab Data (Universal Gate Implementation) Truth

Table for NAND Gate Implementation:
Expected Y (NAND)
A B C D Observed Y (NAND)

0 0 0 0 0 0
0 0 1 0 1 1
1 0 1 1 1 1
1 1 1 0 1 1

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Truth Table for NOR Gate Implementation:
A B C D Expected Y (NOR) Observed Y (NOR)
0 0 0 1 0 0
0 1 1 1 0 0
1 0 1 0 1 1

Rubric for Lab Assessment

The student performance for the assigned task during the lab session was:
The student completed assigned tasks without any help from the
Excellent 4
instructor and showed the results appropriately.
The student completed assigned tasks with minimal help from the
Good 3
instructor and showed the results appropriately.

|EEE 241 | Digital Logic Design Lab Manual 34

 The student could not complete all assigned tasks and showed
Average 2
partial results.

Worst The student did not complete assigned tasks. 1

Instructor Signature: Date:

|EEE 241 | Digital Logic Design Lab Manual 35

 LAB # 4: To Show the Behaviour of Binary Adder/Subtractor and
reproduce its circuit using Universal Gates
Objectives
• To identify basic functionality of a Binary Adder using logic gates
• To identify basic functionality of a Binary Subtractor using logic gates
• To design a binary adder using universal gates (NAND, NOR)
• To design a binary subtractor using universal gates (NAND, NOR)

Pre-Lab

Part 1 -Familiarize yourself with Half Adder & Full Adder

Half Adder

A combinational logic circuit that performs the addition of two data bits, A and B, is called a
half-adder. Addition will result in two output bits; one of which is the sum bit, S, and the other
is the carry bit, C. The Boolean functions describing the half-adder are:

S =A B

C =AB

Full Adder

The half-adder does not take the carry bit from its previous stage into account. This carry bit
from its previous stage is called carry-in bit. A combinational logic circuit that adds two data
bits, A and B, and a carry-in bit, Cin, is called a full-adder. The Boolean functions describing the
full-adder are:

S = (x y) Cin

C = xy + Cin (x y)

Half Subtractor

Subtracting a single-bit binary value B from another A (i.e. A-B) produces a difference bit D and
a borrow out bit B-out. This operation is called half subtraction and the circuit to realize it is
called a half subtractor. The Boolean functions describing the half-Subtractor are:

S =A B

C = A’ B
Full Subtractor

|EEE 241 | Digital Logic Design Lab Manual 36

Subtracting two single-bit binary values, B, Cin from a single-bit value A produces a difference
bit D and a borrow out Br bit. This is called full subtraction. The Boolean functions describing
the full-subtractor are:

D = (x ⊕ y) ⊕ Cin

Br= A’B + A’(Cin) + B(Cin)

In-Lab

Lab Tasks-Part-1

Lab Task 1
Implement half adder by using basic gates and verify the results

Fig: 4.1

Truth Table

OUTPUTS
INPUTS
Observed Values

A B S C

0 0

0 1

1 0

1 1

Table: 4.1
Lab Task 2:

|EEE 241 | Digital Logic Design Lab Manual 37

Implement half adder by using NAND gates and verify the results

Fig: 4.2

Truth Table

OUTPUTS
INPUTS
Observed Values

A B S C

0 0

0 1

1 0

1 1

Table: 4.2
Lab Task 3

Implement full adder by using basic gates and verify the results

|EEE 241 | Digital Logic Design Lab Manual 38

 Fig: 4.3

Truth Table

Table: 4.3

Lab Task 4

Implement full adder by using NAND gates and verify the results

Fig: 4.4
Truth Table

|EEE 241 | Digital Logic Design Lab Manual 39

 Table: 4.4

Lab Tasks-Part-2
Lab Task 1

Implement half subtractor by using basic gates and verify the results

Fig: 4.5

Truth Table

OUTPUTS
INPUTS
Observed Values

A B D Br

|EEE 241 | Digital Logic Design Lab Manual 40

 0 0

0 1

1 0

1 1

Table: 4.5

Lab Task 2:

Implement half subtractor by using NAND gates and verify the

results

Fig: 4.6

Truth Table :

Table: 4.6

Lab Task 3:

Implement full subtractor by using basic gates and verify the results

|EEE 241 | Digital Logic Design Lab Manual 41

 Fig. 4.7

Truth Table:

Table: 4.7

Lab Task 4

Implement full subtractor by using NAND gates and verify the results

|EEE 241 | Digital Logic Design Lab Manual 42

 Fig: 4.8

Truth Table

Table: 4.8

Post-Lab:

Design half adder, full adder, half subtractor and full subtractor using NOR gates.

|EEE 241 | Digital Logic Design Lab Manual 43

Half Adder

Full Adder

Half Subtractor

|EEE 241 | Digital Logic Design Lab Manual 44

Full Subtractor

|EEE 241 | Digital Logic Design Lab Manual 45

 |EEE 241 | Digital Logic Design Lab Manual 43
Rubric for Lab Assessment

The student performance for the assigned task during the lab session was:
The student completed assigned tasks without any help from the
Excellent 4
instructor and showed the results appropriately.
The student completed assigned tasks with minimal help from the
Good 3
instructor and showed the results appropriately.
The student could not complete all assigned tasks and showed
Average 2
partial results.

Worst The student did not complete assigned tasks. 1

Instructor Signature: Date:

 LAB # 5: To Follow the Steps of BCD to Excess 3 Code Conversion
and Reproduce the Results using Dedicated IC
Objectives
• To understand and respond to the steps required to transform a four bit BCD to Excess
3 code conversion.
• To reproduce the steps required to transform Excess 3 code to BCD using IC 7483

Pre Lab

Part 1 -Familiarize yourself with BDC to Excess-3

Code converter is a combinational circuit that translates the input code word into a new
corresponding word. The excess-3 code digit is obtained by adding three to the corresponding
BCD digit. To Construct a BCD-to-excess-3-code converter with a 4-bit adder feed BCD-code to
the 4-bit adder as the first operand and then feed constant 3 as the second operand.

Part 2 -Familiarize yourself with Excess-3 to BCD

To make the above mention circuit work as a excess-3 to BCD converter, we feed excess-3 code
as the first operand and then feed 2's complement of 3 as the second operand. The output is the
BCD code.

In Lab

Lab Tasks-Part-1
Lab Task 1

Use the following circuit to verify the result

Fig. 5.1

|EEE 241 | Digital Logic Design Lab Manual 47

Truth Table

Table: 5.1

Lab Tasks-Part-2
Lab Task 2:

Using the following circuit and verify the result

|EEE 241 | Digital Logic Design Lab Manual 48
 Fig: 5.2

Truth Table

|EEE 241 | Digital Logic Design Lab Manual 49

 Table: 5.2

Post Lab

Design Excess-3 to BCD converter using NAND Gates.

|EEE 241 | Digital Logic Design Lab Manual 50

 Rubric for Lab Assessment

The student performance for the assigned task during the lab session was:
The student completed assigned tasks without any help from the
Excellent 4
instructor and showed the results appropriately.
The student completed assigned tasks with minimal help from the
Good 3
instructor and showed the results appropriately.
The student could not complete all assigned tasks and showed
Average 2
partial results.

Worst The student did not complete assigned tasks. 1

Instructor Signature: Date:

|EEE 241 | Digital Logic Design Lab Manual 51

 LAB # 6: To Follow the Steps of Binary to Gray Code Conversion and
Reproduce the Results using Logic Gates
Objectives
• To understand and respond to the steps required to transform a four bit BCD to
Gray code conversion
• To reproduce the steps required to transform Gray code to BCD using IC 7483

Pre Lab

Lab Tasks-Part-1
Binary Code to Gray Code Conversion

Boolean Expressions:

G3=B3; G2=B3 B2
G1=B1 B2; G0=B1 B0

Lab Tasks-Part-2
|EEE 241 | Digital Logic Design Lab Manual 52
Gray Code to Binary Code Conversion

Boolean Expressions:

B3=G3; B2=G3 ⊕ G2
B1=G3 ⊕ G2 ⊕ G1; B0=G3 ⊕ G2 ⊕ G1 ⊕ G0

|EEE 241 | Digital Logic Design Lab Manual 53

In Lab:

Lab Task 1:

Use following circuit to verify the results

Realization using XOR gates

Fig: 6.1

Truth Table

Binary Gray

Inputs Observed Output

B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1

|EEE 241 | Digital Logic Design Lab Manual 54

 0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
Table: 6.1 Lab Task 2:

Realization using NAND gates

Fig: 6.2

|EEE 241 | Digital Logic Design Lab Manual 55

|EEE 241 | Digital Logic Design Lab Manual 56
Lab Task 3:

Use following circuit to verify the results

Realization using XOR gates

Fig: 6.3
Truth Table

Gray Binary

Inputs Observed Output

G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0
0 0 0 1
0 0 1 1
0 0 1 0
0 1 1 0
0 1 1 1
0 1 0 1
0 1 0 0
1 1 0 0
1 1 0 1
1 1 1 1
1 1 1 0
1 0 1 0
1 0 1 1
1 0 0 1
1 0 0 0
Table: 6.2
Lab Task 4:
Realization using NAND gates

|EEE 241 | Digital Logic Design Lab Manual 57

 Fig: 6.4
Post Lab:

1. Design grey code to binary code converter using NOR gates.

|EEE 241 | Digital Logic Design Lab Manual 58

2. Design binary code to grey code converter using NOR gates.

Rubric for Lab Assessment

The student performance for the assigned task during the lab session was:
The student completed assigned tasks without any help from the
Excellent 4
instructor and showed the results appropriately.

|EEE 241 | Digital Logic Design Lab Manual 59

 The student completed assigned tasks with minimal help from the
Good 3
instructor and showed the results appropriately.
The student could not complete all assigned tasks and showed
Average 2
partial results.

Worst The student did not complete assigned tasks. 1

Instructor Signature: Date:

|EEE 241 | Digital Logic Design Lab Manual 60

 LAB: 7 To Show the Response of a Multiplexer/Demultiplexer and to
Reproduce Adder/Subtractor using Multiplexer
Objectives
• To explain the basic functionality and working of multiplexer using logic gates
• To explain the basic functionality and working of demultiplexer using logic gates
• To display the results of various applications of multiplexer using hardware and
software platforms

Pre Lab

Part 1 -Familiarize yourself with Multiplexers

Multiplexers are very useful components in digital systems. They transfer a large number of
information units over a smaller number of channels, (usually one channel) under the control of
selection signals. Multiplexer means many to one. A multiplexer is a circuit with many inputs but
only one output. By using control signals (select lines) we can select any input to the output.
Multiplexer is also called as data selector because the output bit depends on the input data bit that
is selected. The general multiplexer circuit has 2n input signals, n control/select signals and 1
output signal.

Part 2 -Familiarize yourself with Demultiplexers

De-multiplexers perform the opposite function of multiplexers. They transfer a small number of
information units over a larger number of channels under the control of selection signals. The
general de-multiplexer circuit has 1 input signal, n control/select signals and 2 n output signals.
De-multiplexer circuit can also be realized using a decoder circuit with enable.

In lab

Lab Tasks-Part-1 Lab

Task 1:

4:1 Multiplexer

Output Y= E’S1’S0’I0 + E’S1’S0I1 + E’S1S0’I2 + E’S1S0I3

Realization using NAND Gates

|EEE 241 | Digital Logic Design Lab Manual 61

Lab Task 2: Truth Table

|EEE 241 | Digital Logic Design Lab Manual 62

 F ig: 7.1
Enable
Select Inputs Input Inputs Outputs

S1 S0 E I0 I1 I2 I3 Y
X X 1 X X X X
0 0 0 0 X X X
0 0 0 1 X X X
0 1 0 X 0 X X
0 1 0 X 1 X X
1 0 0 X X 0 X
1 0 0 X X 1 X
1 1 0 X X X 0
1 1 0 X X X 1
Table: 7.1 Lab Task 3:

Verify IC 74153 MUX (Dual 4:1 Multiplexer)

|EEE 241 | Digital Logic Design Lab Manual 63

 Fig: 7.2 Table: 7.2

Tasks-Part-2 Lab
Task 1:

Realization using NAND Gates

|EEE 241 | Digital Logic Design Lab Manual 64

 Fig: 7.3

Lab Task 2:

Truth Table

|EEE 241 | Digital Logic Design Lab Manual 65

 Enable Data
Select Inputs Outputs
Input Input

E D S1 S0 Y3 Y2 Y1 Y0

1 0 X X

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1
Table: 7.3
Lab Task 3:

Verify IC 74139 DEMUX

Fig: 7.4

|EEE 241 | Digital Logic Design Lab Manual 66

Truth Table

Inputs Outputs

Ea S1 S0 Y3 Y2 Y1 Y0

1 X X

0 0 0

0 0 1

0 1 0

0 1 1
Table: 7.4

|EEE 241 | Digital Logic Design Lab Manual 67

Part 3 – Applications of Multiplexers:
To set up a Half/Full Adder and Half/Full Subtractor using IC 74153.

Lab Tasks-Part-3
Lab Task 1: Half Adder using MUX:

Design:

SUM CARRY

I0 I1 I0 I1
0 1 0 1
2 3 2 3
A A’ 0 A
Circuit Diagram:

Fig: 7.5
Truth Table:

Table: 7.5

|EEE 241 | Digital Logic Design Lab Manual 68

|EEE 241 | Digital Logic Design Lab Manual 69
Lab Task 2: Full Adder using MUX:

Design:

SUM

I0 I1 I2 I3
0 1 2 3
4 5 6 7
A A’ A’ A
CARRY

I0 I1 I2 I3
0 1 2 3
4 5 6 7
0 A A 1
Circuit Diagram:

Fig: 7.6

|EEE 241 | Digital Logic Design Lab Manual 70

Truth Table:

Table: 7.6
Lab Task 3: Half Subtractor using MUX:

Design:

DIFFERENCE BORROW
I0 I1 I0 I1

|EEE 241 | Digital Logic Design Lab Manual 71

 0 1 0 1
2 3 2 3
A A’ 0 A’

Circuit Diagram:

Fig: 7.7

Truth Table:

|EEE 241 | Digital Logic Design Lab Manual 72

 Table: 7.7

Lab Task 4: Full Subtractor using MUX:

Design:

Circuit Diagram:

|EEE 241 | Digital Logic Design Lab Manual 73

 Fig: 7.8
Truth Table:

Table: 7.8

|EEE 241 | Digital Logic Design Lab Manual 74

|EEE 241 | Digital Logic Design Lab Manual 75
Post Lab:
Design Half Adder and full Adder using MUX without using IC74153 (using basic gates only).

Rubric for Lab Assessment

The student performance for the assigned task during the lab session was:
The student completed assigned tasks without any help from the
Excellent 4
instructor and showed the results appropriately.
The student completed assigned tasks with minimal help from the
Good 3
instructor and showed the results appropriately.
The student could not complete all assigned tasks and showed
Average 2
partial results.

|EEE 241 | Digital Logic Design Lab Manual 76

 Worst The student did not complete assigned tasks. 1

Instructor Signature: Date:

|EEE 241 | Digital Logic Design Lab Manual 77

 LAB # 8: To Show the response of Binary Comparator(s) using
hardware and software tools and to Reproduce the Comparator using
dedicated IC
Objectives
• To compare two input signals using logic gates
• To analyze the working of 4-bit magnitude comparator’s IC 7485

Pre Lab

Part 1 -Familiarize yourself with Comparators

Magnitude Comparator is a logical circuit, which compares two signals A and B and
generates three logical outputs, whether A > B, A = B, or A < B. IC 7485 is a high speed 4-
bit magnitude comparator, which compares two 4-bit words. The A = B Input must be held
high for proper compare operation.

In Lab:

Lab Tasks-Part-1

Lab Task 1: 1-Bit Comparator

Design:

Circuit Diagram:

Fig: 8.1
Truth Table:

|EEE 241 | Digital Logic Design Lab Manual 78

 Table: 8.1

Lab Task 2: 2-Bit Comparator

Design:

Circuit Diagram:

|EEE 241 | Digital Logic Design Lab Manual 79

 Fig: 8.2

Truth Table:

|EEE 241 | Digital Logic Design Lab Manual 80

 Table: 8.2

Lab Tasks-Part-2
Lab Task 1: 4-Bit Comparator
Circuit Diagram:

Fig: 8.3
Truth Table:

|EEE 241 | Digital Logic Design Lab Manual 81

 Table: 8.3

Rubric for Lab Assessment

The student performance for the assigned task during the lab session was:
The student completed assigned tasks without any help from the
Excellent 4
instructor and showed the results appropriately.
The student completed assigned tasks with minimal help from the
Good 3
instructor and showed the results appropriately.

|EEE 241 | Digital Logic Design Lab Manual 82

 The student could not complete all assigned tasks and showed
Average 2
partial results.

Worst The student did not complete assigned tasks. 1

Instructor Signature: Date:

|EEE 241 | Digital Logic Design Lab Manual 83

 LAB # 9: To Show the response of an Encoder/Decoder and to
Reproduce the binary converters using basic logic gates
Objectives
Part 1

• To explain the basic functionality and working of Encoder using logic gates
• To explain the basic functionality and working of decoder using logic gates
• To display the results of various applications of encoder using hardware and
software platforms
• To display the results of various applications of decoder using hardware and
software platforms

Pre Lab

Part 1 - To realize a decoder circuit using basic gates and to verify IC

74LS139 Decoder
A decoder is a combinational circuit that connects the binary information from ‘n’ input lines to
a maximum of 2n unique output lines. Decoder is also called a min-term generator/max-term
generator. A min-term generator is constructed using AND and NOT gates. The appropriate
output is indicated by logic 1 (positive logic). Max-term generator is constructed using NAND
gates. The appropriate output is indicated by logic 0 (Negative logic).

The IC 74139 accepts two binary inputs and when enable provides 4 individual active low outputs. The
device has 2 enable inputs (Two active low).

Part 2 - To set up and test a 7-segment static display system to display

numbers 0 to 9
The Light Emitting Diode (LED) finds its place in many applications in these modern electronic
fields. One of them is the Seven Segment Display. Seven-segment displays contain the
arrangement of the LEDs in “Eight” (8) passion, and a Dot (.) with a common electrode, lead
(Anode or Cathode). The purpose of arranging it in that passion is that we can make any number
out of that by switching ON and OFF the particular LED's. Here is the block diagram of the Seven
Segment LED arrangement.

The Light Emitting Diode (LED), finds its place in many applications in this modern electronic fields.
One of them is the Seven Segment Display. Seven-segment displays contain the arrangement of the
LEDs in “Eight” (8) passion, and a Dot (.) with a common electrode, lead (Anode or Cathode). The

|EEE 241 | Digital Logic Design Lab Manual 84

purpose of arranging it in that passion is that we can make any number out of that by switching ON and
OFF the particular LED's. Here is the block diagram of the Seven Segment LED arrangement.

LED’s are basically of two types- Common Cathode (CC) -All the 8 anode legs uses only one
cathode, which is common. Common Anode (CA)-The common leg for the entire cathode is of
Anode type.

A decoder is a combinational circuit that connects the binary information from ‘n’ input lines to
a maximum of 2n unique output lines. The IC7447 is a BCD to 7-segment pattern converter. The
IC7447 takes the Binary Coded Decimal (BCD) as the input and outputs the relevant 7 segment
code.

Part 3 - To set up a circuit of Decimal-to-BCD Encoder using IC 74147 and to

design and set up a circuit of Hexadecimal-to-Binary Encoder
Encoder

An encoder performs a function that is the opposite of decoder. It receives one or more signals
in an encoded format and output a code that can be processed by another logic circuit. One of
the advantages of encoding data, or more often data addresses in computers, is that it reduces
the number of required bits to represent data or addresses. For example, if a memory has 16
different locations, in order to access these 16 different locations, 16 lines (bits) are required if
the addressing signals are in 1 out of n format. However, if we code the 16 different addresses
into a binary format, then only 4 lines (bits) are required. Such a reduction improves the speed
of information processing in digital systems.
In Lab:

Lab Tasks-Part-1
2:4 DECODER (MIN TERM GENERATOR):
Truth Table:

|EEE 241 | Digital Logic Design Lab Manual 85

 Table: 9.1 Boolean

Expressions:

Circuit Diagram:

Fig: 9.1

2:4 DECODER (MAX TERM GENERATOR):

TRUTH TABLE:

Table: 9.2
CIRCUIT DIAGRAM:

|EEE 241 | Digital Logic Design Lab Manual 86

 Fig: 9.2

Lab Tasks-Part-2:
CIRCUIT DIAGRAM:

Fig: 9.3
TRUTH TABLE:

Decimal
Output Logic Levels from IC 7447 to 7-
segments number
BCD Inputs display
D C B A a b c d e f g
0 0 0 0 0 0 0 0 0 0 1
0 0 0 1 1 0 0 1 1 1 1
0 0 1 0 0 0 1 0 0 1 0
0 0 1 1 0 0 0 0 1 1 0
0 1 0 0 1 0 0 1 1 0 0
0 1 0 1 0 1 0 0 1 0 0

|EEE 241 | Digital Logic Design Lab Manual 87

 0 1 1 0 1 1 0 0 0 0 0
0 1 1 1 0 0 0 1 1 1 1
1 0 0 0 0 0 0 0 0 0 0
1 0 0 1 0 0 0 1 1 0 0
Table: 9.3

Lab Tasks-Part-3:

DECIMAL-TO BCD ENCODER USING IC 74147.

TRUTH TABLE

Table: 9.4
CIRCUIT DIAGRAM:

Fig: 9.4

|EEE 241 | Digital Logic Design Lab Manual 88

Octal to Binary Converter:

Fig: 9.5
Truth Table:

Table: 9.5

HEXADECIMAL TO BINARY ENCODER

|EEE 241 | Digital Logic Design Lab Manual 89

 Fig: 9.6
TRUTH TABLE

Table: 9.6

|EEE 241 | Digital Logic Design Lab Manual 90

In-Lab:
Lab Tasks-Part 1: DECODER (MIN TERM GENERATOR):

DECODER (MAX TERM GENERATOR):

Lab Tasks-Part 2:

|EEE 241 | Digital Logic Design Lab Manual 91

Lab Task Part 3: DECIMAL-TO BCD ENCODER USING IC 74147.

HEXADECIMAL TO BINARY ENCODER

|EEE 241 | Digital Logic Design Lab Manual 92

 Rubric for Lab Assessment

The student performance for the assigned task during the lab session was:
The student completed assigned tasks without any help from the
Excellent 4
instructor and showed the results appropriately.
The student completed assigned tasks with minimal help from the
Good 3
instructor and showed the results appropriately.
The student could not complete all assigned tasks and showed
Average 2
partial results.

Worst The student did not complete assigned tasks. 1

Instructor Signature: Date:

|EEE 241 | Digital Logic Design Lab Manual 93

 LAB # 10: To Identify the Response of Sequential Circuit(s) using
Hardware and Software Platforms
Objectives
• To describe the basic functions of sequential circuits
• To differentiate between various types of Flip Flops
• To identify various ICs used to perform basic functionality of various Flip Flops

Pre Lab

Truth Table verification of FF and conversion of one FF to another

Logic circuits that incorporate memory cells are called sequential logic circuits; their output
depends not only upon the present value of the input but also upon the previous values.
Sequential logic circuits often require a timing generator (a clock) for their operation. The latch
(flip-flop) is a basic bi-stable memory element widely used in sequential logic circuits. Usually
there are two outputs, Q and its complementary value. Some of the most widely used latches
are listed below.

SR LATCH
S-R latch consists of two cross-coupled NOR gates. An S-R flip-flop can also be design using
cross-coupled NAND gates as shown. The truth tables of the circuits are shown below. A
clocked S-R flip-flop has an additional clock input so that the S and R inputs are active only
when the clock is high. When the clock goes low, the state of flip-flop is latched and cannot
change until the clock goes high again. Therefore, the clocked S-R flip-flop is also called
“enabled” S-R flip-flop. A D latch combines the S and R inputs of an S-R latch into one input
by adding an inverter. When the clock is high, the output follows the D input, and when the
clock goes low, the state is latched.

In Lab Lab
Task 1:
S-R LATCH:

LOGIC DIAGRAM SYMBOL

Fig: 10.1

|EEE 241 | Digital Logic Design Lab Manual 94

TRUTH TABLE

Table: 10.1

Lab Task 2:
SR FLIP FLOP:

|EEE 241 | Digital Logic Design Lab Manual 95

 Fig: 10.2

TRUTH TABLE

Table: 10.2

Lab Task 3:
CONVERSION OF SR-FLIP FLOP TO T-FLIP FLOP (Toggle)
LOGIC DIAGRAM SYMBOL

|EEE 241 | Digital Logic Design Lab Manual 96

 Fig: 10.3
T FLIP FLOP USING IC 7476 TRUTH TABLE

Table: 10.3

Lab Task 4:

CONVERSION OF SR-FLIP FLOP TO D-FLIP FLOP

|EEE 241 | Digital Logic Design Lab Manual 97

 LOGIC DIAGRAM SYMBOL

Fig:10.4

D FLIP FLOP USING IC 7476 TRUTH TABLE

CLOCK D Q+ Q’
0 X
1 0
1 1

Table: 10.4

|EEE 241 | Digital Logic Design Lab Manual 98

|EEE 241 | Digital Logic Design Lab Manual 99
Lab Task 5:

CONVERSION OF SR-FLIP FLOP TO JK-FLIP FLOP

Logic Diagram Truth Table

Fig: 10.5 Table: 10.5

Logic Diagram Truth Table

Table: 10.6

|EEE 241 | Digital Logic Design Lab Manual 10

0
Lab Task 6:

JK Master Slave FLIP FLOP

Fig: 10.6

|EEE 241 | Digital Logic Design Lab Manual 10

1
Truth Table

Table: 10.7

Post Lab:
Differentiate between different types of FLIP FLOPS.

|EEE 241 | Digital Logic Design Lab Manual 10

2
 Rubric for Lab Assessment

The student performance for the assigned task during the lab session was:
The student completed assigned tasks without any help from the
Excellent 4
instructor and showed the results appropriately.
The student completed assigned tasks with minimal help from the
Good 3
instructor and showed the results appropriately.
The student could not complete all assigned tasks and showed
Average 2
partial results.

Worst The student did not complete assigned tasks. 1

Instructor Signature: Date:

|EEE 241 | Digital Logic Design Lab Manual 10

3
 LAB # 11: To show the Response of Shift Registers using 7495 IC and
Reproduce the shift registers using D-Flip-Flops

Objectives
1. To explain the working of a shift register using 7495 IC
2. To differentiate between the different types of shift register

Pre Lab
In digital circuits, a shift register is a cascade of flip flops, sharing the same clock, in which the
output of each flip-flop is connected to the "data" input of the next flip-flop in the chain, resulting
in a circuit that shifts by one position the "bit array" stored in it, shifting in the data present at its
input and shifting out the last bit in the array, at each transition of the clock input.

More generally, a shift register may be multidimensional, such that it’s "data in" and stage outputs
are themselves bit arrays: this is implemented simply by running several shift registers of the
same bit-length in parallel.

Shift registers can have both parallel and serial inputs and outputs. These are often configured as
'serial-in, parallel-out' (SIPO) or as 'parallel-in, serial-out' (PISO). There are also types that have
both serial and parallel input and types with serial and parallel output. There are also
'bidirectional' shift registers which allow shifting in both directions: L→R or R→L. The serial input
and last output of a shift register can also be connected to create a 'circular shift register'.

In Lab
1. Check all the components for their working
2. Insert the appropriate IC into the IC base
3. Make connections as shown in the circuit diagram
4. Verify the Truth Table and observe the outputs

Fig: 11.1
Lab Task 1:
SERIAL IN SERIAL OUT (SISO) (Right Shift)

|EEE 241 | Digital Logic Design Lab Manual 10

4
 Serial
Shift
i/p QA QB QC QD
Pulses
Data
- -
0 t1
1 t2
0 t3
1 t4
X t5
X t6
X t7
X t8
Table: 11.1
Lab Task 2:
SERIAL IN PARALLEL OUT (SIPO)

Serial Shift
QA QB QC QD
i/p data Pulses
- -
0 t1
1 t2
0 t3
1 t4
Table: 11.2

Lab Task 3:
PARALLEL IN PARALLEL OUT (PIPO)

Clock
Shift
Input QA QB QC QD
Pulses
Terminal
- -
CLK2 t1
Table: 11.3
Lab Task 4
PARALLEL IN SERIAL OUT (PISO)

Clock
Shift
Input QA QB QC QD
Pulses
Terminal
- -

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 CLK2 t1
CLK2 t2
0 t3

1 t4
X t5
Table: 11.4

Post Lab:

1. Design shift registers using basic gates.

2. Differentiate between different types of shift registers.

Rubric for Lab Assessment

The student performance for the assigned task during the lab session was:
The student completed assigned tasks without any help from the
Excellent 4
instructor and showed the results appropriately.

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 The student completed assigned tasks with minimal help from the
Good 3
instructor and showed the results appropriately.
The student could not complete all assigned tasks and showed
Average 2
partial results.

Worst The student did not complete assigned tasks. 1

Instructor Signature: Date:

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 LAB # 12: To Reproduce a Synchronous Sequence Detector using
hardware and software tools
Objectives
To analyze working principle of a sequence detector

Pre Lab
A sequence detector is a sequential logic circuit that can be used to detect whether a given
sequence of bits has been received or not by a receiver. Consider, for example, a single-input
single-output sequence detector. Let the sequence to be detected be 101. Repetition is allowed in
this sequence. This means that, the circuit will give an output of I when it detects first the
sequence 101 in a series of incoming bits. Let the next two bits after the first 101 be 01. We find
that the circuit will read this as 101 and output another 1. This is because we have given
permission for repetition, and the circuit will consider the last 1 in the first 101 as a valid first 1
in the next sequence of 101.

In Lab
Procedure
1. Draw the state diagram of the state machine below and show it to the lab instructor.

2. Fill the state table.

3. Assign State numbers

4. Find simplified Expressions (State Equations) for the flip-flops

5. Draw the circuit diagram using NAND GATES ONLY for the state machine

State Diagram
State Table

Present State Next State

QA QB QC Y DA DB DC
0 0 0 0 0
0 0 0 1 1
0 0 1 0 2
0 0 1 1 3
0 1 0 0 4
0 1 0 1 5
0 1 1 0 6

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 0 1 1 1 7
1 0 0 0 8
1 0 0 1 9
1
1 0 1 1 11
1 1 0 0 12
1 1 0 1 13
1 1 1 0 14
1 1 1 1 15
Table: 12.1
For For

Q CY QCY

Q AQ B 00 01 11 10 Q AQ B 00 01 11 10

00 00

01 01

11 11

10 10

For
QCY

Q AQ B 00 01 11 10

00

01

11

10

Table: 12.2
State Equations
DA = DB =
DC =

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Circuit Diagram

D Q

CLK

D Q

CLK

D Q

CLK

Fig: 12.1
Implementation
Connect the circuit according to your design and check for the following input
sequence.

Table: 12.3

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Post Lab:
Design a sequence detector which to detect 110101.
Rubric for Lab Assessment

The student performance for the assigned task during the lab session was:
The student completed assigned tasks without any help from the
Excellent 4
instructor and showed the results appropriately.
The student completed assigned tasks with minimal help from the
Good 3
instructor and showed the results appropriately.
The student could not complete all assigned tasks and showed
Average 2
partial results.

Worst The student did not complete assigned tasks. 1

Instructor Signature: Date:

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 LAB # 13: To Show the Response of Ring and Johnson Counter using
7495 IC
Objectives
• To explain the working of ring and Johnson counter using flip flops
• To display the results of ring and Johnson counter using hardware and software
platforms

Pre Lab

Part 1 -Familiarize yourself with Ring Counter:

Ring counter is a basic register with direct feedback such that the contents of the register simply
circulate around the register when the clock is running. Here the last output that is QD in a shift register
is connected back to the serial input.

Part 2 -Familiarize yourself with Johnson Counter:

A basic ring counter can be slightly modified to produce another type of shift register
counter called Johnson counter. Here complement of last output is connected back to
the not gate input and not gate output is connected back to serial input. A four bit
Johnson counter gives 8 state output.

In Lab Lab

Task-1

Circuit Diagram:

Fig: 13.1
Truth Table:
Clock
QA QB QC QD
pulses
0
1

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 2
3
4
5
6
7
8

Table: 13.1
Lab Task-2:
Circuit Diagram :

Fig: 13.1
Truth Table :
Clock Q Q Q Q
Pulses A B C D
0
1
2
3
4
5
6
7
8
Table: 13.1
Post Lab:

1. Differentiate between Ring couner and Johnson Counter.

2. Design ring counter using basic gates

Rubric for Lab Assessment

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 The student performance for the assigned task during the lab session was:
The student completed assigned tasks without any help from the
Excellent 4
instructor and showed the results appropriately.
The student completed assigned tasks with minimal help from the
Good 3
instructor and showed the results appropriately.
The student could not complete all assigned tasks and showed
Average 2
partial results.

Worst The student did not complete assigned tasks. 1

Instructor Signature: Date:

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 LAB # 14: To Reproduce the Asynchronous Counters using hardware
and software tools
Objectives
• To analyze the working principle of a Synchronous counter using flip flops
• To analyze the working principle of asynchronous counter using flip flops
• To design synchronous and asynchronous counter using flip flops

Pre Lab

Part 1 -Familiarize yourself with Asynchronous Counter:

A counter in which each flip-flop is triggered by the output goes to previous flip-flop. As all the
flip-flops do not change state simultaneously spike occur at the output. To avoid this, strobe pulse
is required. Because of the propagation delay the operating speed of asynchronous counter is low.
Asynchronous counter are easy and simple to construct.

Part 2 -Familiarize yourself with Synchronous Counter:

A counter in which each flip-flop is triggered by the output goes to previous flip-flop. As all the
flip-flops do not change states simultaneously in asynchronous counter, spike occur at the output.
To avoid this, strobe pulse is required. Because of the propagation delay the operating speed of
asynchronous counter is low. This problem can be solved by triggering all the flip-flops in
synchronous with the clock signal and such counters are called synchronous counters.

In Lab:

Mod 8 up counter
Circuit Diagram

Fig: 14.1
TRUTH TABLE

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 Table: 14.1

Mod_ 6 up counter
Circuit Diagram:

Fig: 14.2
TRUTH TABLE

Table: 14.2

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Mod_ 8 down counter
Circuit Diagram:

Fig: 14.3
TRUTH TABLE

Table: 14.3
Mod_ 6 down counter
Circuit Diagram:

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 Fig: 14.4
TRUTH TABLE

Table: 14.4
PROCEDURE:
1) Check all the components for their working.

2) Insert the appropriate IC into the IC base.

3) Make connections as shown in the circuit diagram.

4) Verify the Truth Table and observe the outputs.

Mod_ 5 counter

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 Table: 14.5

Table: 14.6

Table: 14.7

Circuit Diagram:

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Mod_ 8 counter:

Table: 14.8

Table: 14.8

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 Table: 14.9
Circuit Diagram:

Post Lab:

Differentiate between synchronous counter and asynchronous Counter.

Rubric for Lab Assessment

The student performance for the assigned task during the lab session was:
The student completed assigned tasks without any help from the
Excellent 4
instructor and showed the results appropriately.
The student completed assigned tasks with minimal help from the
Good 3
instructor and showed the results appropriately.
The student could not complete all assigned tasks and showed
Average 2
partial results.

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 Worst The student did not complete assigned tasks. 1

Instructor Signature: Date:

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