MODULE 3: MEMORY

SYSTEM
Dr Shreema Shetty
Dept CSE
SCEM

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BASIC CONCEPTS
• Maximum size of memory that can be used in any computer is determined by
addressing mode.

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• If MAR is k-bits long the

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→ memory may contain upto 2K addressable-locations

• If MDR is n-bits long, then → n-bits of data are transferred between the
memory and processor.

• The data-transfer takes place over the processor-bus (Figure 8.1).

• The processor-bus has 1) Address-Line 2) Data-line & 3) Control-Line

(R/W‟, MFC – Memory Function Completed)

Dr Shreema Shetty
Dept CSE
SCEM4
• The Control-Line is used for coordinating data-transfer.

• The processor reads the data from the memory by → loading the address of the
required memory-location into MAR and → setting the R/W‟ line to 1.

• The memory responds by → placing the data from the addressed-location onto
the data-lines and → confirms this action by asserting MFC signal.

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• Upon receipt of MFC signal, the processor loads the data from the data-lines into
MDR.

• The processor writes the data into the memory-location by → loading the
address of this location into MAR & → setting the R/W‟ line to 0.

• Memory Access Time: It is the time that elapses between → initiation of an

operation & → completion of that operation.

• Memory Cycle Time: It is the minimum time delay that required between the
initiation of the two successive memory-operations.

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RAM (Random Access Memory)

• In RAM, any location can be accessed for a Read/Write-operation in fixed

amount of time.

Cache Memory: It is a small, fast memory that is inserted between → larger

slower main-memory and

→ processor.

● It holds the currently active segments of a program and their data

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Virtual Memory
● The address generated by the processor is referred to as a virtual/logical
address.
● The virtual-address-space is mapped onto the physical-memory where data
are actually stored.
● The mapping-function is implemented by MMU. (MMU = memory
management unit).
● Only the active portion of the address-space is mapped into locations in the
physical-memory. The remaining virtual-addresses are mapped onto the bulk
storage devices such as magnetic disk.

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As the active portion of the virtual-address-space changes during program
execution, the MMU

→ changes the mapping-function &

→ transfers the data between disk and memory.

During every memory-cycle, MMU determines whether the addressed-page is in

the memory. If the page is in the memory. Then, the proper word is accessed and
execution proceeds. Otherwise, a page containing desired word is transferred
from disk to memory.

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• Memory can be classified as follows:

1) RAM which can be further classified as follows: i) Static RAM ii) Dynamic RAM
(DRAM) which can be further classified as synchronous & asynchronous DRAM.

2) ROM which can be further classified as follows: i) PROM ii) EPROM iii)
EEPROM & iv) Flash Memory which can be further classified as Flash Cards &
Flash Drives

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SEMI CONDUCTOR RAM MEMORIES
INTERNAL ORGANIZATION OF MEMORY-CHIPS
• Memory-cells are organized in the form of array (Figure 5.2).
• Each cell is capable of storing 1-bit of information.
• Each row of cells forms a memory-word.
• All cells of a row are connected to a common line called as Word-Line.
• The cells in each column are connected to Sense/Write circuit by 2-bit-lines.
• The Sense/Write circuits are connected to data-input or output lines of the chip.
• During a write-operation, the sense/write circuit → receive input information & → store input info
in the cells of the selected word.

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• The data-input and data-output of each Sense/Write circuit are connected to a
single bidirectional data-line.

• Data-line can be connected to a data-bus of the computer.

• Following 2 control lines are also used: 1) R/W’ Specifies the required operation.
2) CS’ Chip Select input selects a given chip in the multi-chip memory-system.

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STATIC RAM (OR MEMORY)

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• Two inverters are cross connected to form a latch .

• The latch is connected to 2-bit-lines by transistors T1 and T2.

• The transistors act as switches that can be opened/closed under the control of
the word-line.

• When the word-line is at ground level, the transistors are turned off and the latch
retain its state.

Dr Shreema Shetty
Dept CSE
SCEM 15
Read Operation

• To read the state of the cell, the word-line is activated to close switches T1 and
T2.

• If the cell is in state 1, the signal on bit-line b is high and the signal on the bit-line
b‟ is low.

• Thus, b and b‟ are complement of each other.

• Sense/Write circuit → monitors the state of b & b‟ and → sets the output
accordingly.

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Write Operation

• The state of the cell is set by

→ placing the appropriate value on bit-line b and its complement on b‟ and

→ then activating the word-line. This forces the cell into the corresponding state.

• The required signal on the bit-lines is generated by Sense/Write circuit.

Dr Shreema Shetty
Dept CSE
SCEM 17
CMOS Cell

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• Transistor pairs (T3, T5) and (T4, T6) form the inverters in the latch (Figure 8.5).
• In state 1, the voltage at point X is high by having T5, T6 ON and T4, T5 are
OFF.
• Thus, T1 and T2 returned ON (Closed), bit-line b and b‟ will have high and low
signals respectively.
• Advantages: 1) It has low power consumption „.‟ the current flows in the cell only
when the cell is active. 2) Static RAM‟s can be accessed quickly. It access time is
few nanoseconds.
• Disadvantage: SRAMs are said to be volatile memories „.‟ their contents are lost
when power is interrupted.

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ASYNCHRONOUS DRAM
• Less expensive RAMs can be implemented if simple cells are used.

• Such cells cannot retain their state indefinitely. Hence they are called Dynamic
RAM (DRAM).

• The information stored in a dynamic memory-cell in the form of a charge on a

capacitor.

• This charge can be maintained only for tens of milliseconds.

• The contents must be periodically refreshed by restoring this capacitor charge to

its full value.

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• In order to store information in the cell, the transistor T is turned „ON‟ (Figure
8.6).
• The appropriate voltage is applied to the bit-line which charges the capacitor.
• After the transistor is turned off, the capacitor begins to discharge.
• Hence, info. stored in cell can be retrieved correctly before threshold value of
capacitor drops down.
• During a read-operation, → transistor is turned „ON‟ → a sense amplifier
detects whether the charge on the capacitor is above the threshold value. If
(charge on capacitor) > (threshold value) Bit-line will have logic value “1‟. If
(charge on capacitor) < (threshold value) Bit-line will set to logic value “0”.

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ASYNCHRONOUS DRAM DESCRIPTION

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• The 4 bit cells in each row are divided into 512 groups of 8 (Figure 5.7).

• 21 bit address is needed to access a byte in the memory.

21 bit is divided as follows:

1) 12 address bits are needed to select a row. i.e. A8-0 → specifies row-address
of a byte.

2) 9 bits are needed to specify a group of 8 bits in the selected row. i.e. A20-9 →
specifies column-address of a byte.

Dr Shreema Shetty
Dept CSE
24
SCEM
• During Read/Write-operation,

→ row-address is applied first.

→ row-address is loaded into row-latch in response to a signal pulse on RAS’

input of chip. (RAS = Row-address Strobe CAS = Column-address Strobe)

• When a Read-operation is initiated, all cells on the selected row are read and
refreshed.

• Shortly after the row-address is loaded, the column-address is → applied to the

address pins & → loaded into CAS’.

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• The information in the latch is decoded.
• The appropriate group of 8 Sense/Write circuits is selected. R/W’=1(read-operation)
Output values of selected circuits are transferred to data-lines D0-D7.
R/W’=0(write-operation) Information on D0-D7 are transferred to the selected circuits.
• RAS‟ & CAS‟ are active-low so that they cause latching of address when they
change from high to low.
• To ensure that the contents of DRAMs are maintained, each row of cells is accessed
periodically.
• A special memory-circuit provides the necessary control signals RAS‟ & CAS‟ that
govern the timing.
• The processor must take into account the delay in the response of the memory.

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Fast Page Mode

● Transferring the bytes in sequential order is achieved by applying the

consecutive sequence of column-address under the control of successive
CAS‟ signals.
● This scheme allows transferring a block of data at a faster rate. The block of
transfer capability is called as fast page mode.

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SYNCHRONOUS DRAM
• The operations are directly synchronized with clock signal (Figure 8.8).
• The address and data connections are buffered by means of registers.
• The output of each sense amplifier is connected to a latch.
• A Read-operation causes the contents of all cells in the selected row to be
loaded in these latches.
• Data held in latches that correspond to selected columns are transferred into
data-output register.
• Thus, data becoming available on the data-output pins.

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SYNCHRONOUS DRAM

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• First, the row-address is latched under control of RAS‟ signal (Figure 8.9).

• The memory typically takes 2 or 3 clock cycles to activate the selected row.

• Then, the column-address is latched under the control of CAS‟ signal.

• After a delay of one clock cycle, the first set of data bits is placed on the
data-lines. • SDRAM automatically increments column-address to access next 3
sets of bits in the selected row.

Dr Shreema Shetty
Dept CSE
SCEM
31
LATENCY & BANDWIDTH
• A good indication of performance is given by 2 parameters: 1) Latency 2) Bandwidth.
Latency
• It refers to the amount of time it takes to transfer a word of data to or from the memory.
• For a transfer of single word, the latency provides the complete indication of memory
performance.
• For a block transfer, the latency denotes the time it takes to transfer the first word of
data.
Bandwidth
• It is defined as the number of bits or bytes that can be transferred in one second.
• Bandwidth mainly depends on 1) The speed of access to the stored data & 2) The
number of bits that can be accessed in parallel.

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DOUBLE DATA RATE SDRAM (DDR-SDRAM)
• The standard SDRAM performs all actions on the rising edge of the clock signal.
• The DDR-SDRAM transfer data on both the edges (loading edge, trailing edge). •
The Bandwidth of DDR-SDRAM is doubled for long burst transfer.
• To make it possible to access the data at high rate, the cell array is organized
into two banks.
• Each bank can be accessed separately.
• Consecutive words of a given block are stored in different banks.
• Such interleaving of words allows simultaneous access to two words.
• The two words are transferred on successive edge of the clock.
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STRUCTURE OF LARGER MEMORIES
Dynamic Memory System
• The physical implementation is done in the form of memory-modules.
• If a large memory is built by placing DRAM chips directly on the Motherboard,
then it will occupy large amount of space on the board.
• These packaging consideration have led to the development of larger memory
units known as SIMM‟s & DIMM‟s. 1) SIMM Single Inline memory-module 2)
DIMM Dual Inline memory-module
• SIMM/DIMM consists of many memory-chips on small board that plugs into a
socket on motherboard.

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MEMORY-SYSTEM CONSIDERATION
MEMORY CONTROLLER

• To reduce the number of pins, the dynamic memory-chips use

multiplexed-address inputs.

• The address is divided into 2 parts:

1) High Order Address Bit Select a row in cell array. It is provided first and
latched into memory-chips under the control of RAS‟ signal.

2) Low Order Address Bit Selects a column. They are provided on same address
pins and latched using CAS‟ signals.

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Memory controller

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Memory controller
• The Multiplexing of address bit is usually done by Memory Controller Circuit.

• The Controller accepts a complete address & R/W‟ signal from the processor.

• A Request signal indicates a memory access operation is needed.

• Then, the Controller → forwards the row & column portions of the address to the
memory. → generates RAS‟ & CAS‟ signals & → sends R/W‟ & CS‟ signals to the
memory.

Dr Shreema Shetty
Dept CSE
SCEM
37
RAMBUS MEMORY
• The usage of wide bus is expensive.

• Rambus developed the implementation of narrow bus.

• Rambus technology is a fast signaling method used to transfer information between

chips.

• The signals consist of much smaller voltage swings around a reference voltage Vref.

• The reference voltage is about 2V.

• The two logical values are represented by 0.3V swings above and below Vref.

• This type of signaling is generally is known as Differential Signalling.

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RAMBUS MEMORY
• Rambus provides a complete specification for design of communication called as
Rambus Channel.
• Rambus memory has a clock frequency of 400 MHz.
• The data are transmitted on both the edges of clock so that effective
data-transfer rate is 800MHZ.
• Circuitry needed to interface to Rambus channel is included on chip. Such chips
are called RDRAM. (RDRAM = Rambus DRAMs).
• Rambus channel has: 1) 9 Data-lines (1st-8th line ->Transfer the data, 9th
line->Parity checking). 2) Control-Line & 3) Power line.

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RAMBUS MEMORY
• A two channel rambus has 18 data-lines which has no separate Address-Lines.

• Communication between processor and RDRAM modules is carried out by

means of packets transmitted on the data-lines.

• There are 3 types of packets: 1) Request 2) Acknowledge & 3) Data

Dr Shreema Shetty
Dept CSE
SCEM
40
READ ONLY MEMORY (ROM)
• Both SRAM and DRAM chips are volatile, i.e. They lose the stored information if power is
turned off.

• Many application requires non-volatile memory which retains the stored information if power is
turned off.

• For ex: OS software has to be loaded from disk to memory i.e. it requires non-volatile memory.

• Non-volatile memory is used in embedded system.

• Since the normal operation involves only reading of stored data, a memory of this type is called
ROM. At Logic value ‘0’ Transistor(T) is connected to the ground point (P). Transistor switch is
closed & voltage on bit-line nearly drops to zero (Figure 11). At Logic value ‘1’ Transistor switch
is open. The bit-line remains at high voltage.

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• To read the state of the cell, the word-line is activated.
• A Sense circuit at the end of the bit-line generates the proper output value

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TYPES OF ROM

• Different types of non-volatile memory are

1) PROM

2) EPROM

3) EEPROM &

4) Flash Memory (Flash Cards & Flash Drives)

Dr Shreema Shetty
Dept CSE
SCEM 43
PROM (PROGRAMMABLE ROM)

• PROM allows the data to be loaded by the user.

• Programmability is achieved by inserting a „fuse‟ at point P in a ROM cell.

• Before PROM is programmed, the memory contains all 0‟s.

• User can insert 1‟s at required location by burning-out fuse using high
current-pulse.

• This process is irreversible.

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• Advantages: 1) It provides flexibility.

2) It is faster.

3) It is less expensive because they can be programmed directly by the user.

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EPROM (ERASABLE REPROGRAMMABLE ROM)

• EPROM allows → stored data to be erased and → new data to be loaded.

• In cell, a connection to ground is always made at „P‟ and a special transistor is

used.

• The transistor has the ability to function as → a normal transistor or → a

disabled transistor that is always turned “off”.

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• Transistor can be programmed to behave as a permanently open switch, by injecting
charge into it.

• Erasure requires dissipating the charges trapped in the transistor of memory-cells.

This can be done by exposing the chip to ultra-violet light.

• Advantages: 1) It provides flexibility during the development-phase of digital-system.

2) It is capable of retaining the stored information for a long time.

• Disadvantages: 1) The chip must be physically removed from the circuit for
reprogramming. 2) The entire contents need to be erased by UV light.

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EEPROM (ELECTRICALLY ERASABLE ROM)

• Advantages: 1) It can be both programmed and erased electrically. 2) It allows

the erasing of all cell contents selectively.

• Disadvantage: It requires different voltage for erasing, writing and reading the
stored data.

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FLASH MEMORY
• In EEPROM, it is possible to read & write the contents of a single cell.
• In Flash device, it is possible to read contents of a single cell & write entire
contents of a block.
• Prior to writing, the previous contents of the block are erased. Eg. In MP3 player,
the flash memory stores the data that represents sound.
• Single flash chips cannot provide sufficient storage capacity for
embedded-system.
• Advantages: 1) Flash drives have greater density which leads to higher capacity
& low cost per bit. 2) It requires single power supply voltage & consumes less
power.

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• There are 2 methods for implementing larger memory: 1) Flash Cards & 2) Flash
Drives .

1) Flash Cards One way of constructing larger module is to mount flash-chips on

a small card. Such flash-card have standard interface. The card is simply
plugged into a conveniently accessible slot. Memory-size of the card can be 8, 32
or 64MB. Eg: A minute of music can be stored in 1MB of memory. Hence 64MB
flash cards can store an hour of music.

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2) Flash Drives

Larger flash memory can be developed by replacing the hard disk-drive. The
flash drives are designed to fully emulate the hard disk.

The flash drives are solid state electronic devices that have no movable parts.

Advantages: 1) They have shorter seek & access time which results in faster
response. 2) They have low power consumption. .‟. they are attractive for battery
driven application. 3) They are insensitive to vibration.

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Disadvantages:

1) The capacity of flash drive (<1GB) is less than hard disk (>1GB).

2) It leads to higher cost per bit.

3) Flash memory will weaken after it has been written a number of times (typically
at least 1 million times).

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53
• The main-memory can be built with DRAM (Figure 8.14)
• Thus, SRAM‟s are used in smaller units where speed is of essence.
• The Cache-memory is of 2 types: 1) Primary/Processor Cache (Level1 or L1
cache) It is always located on the processor-chip. 2) Secondary Cache (Level2 or
L2 cache) It is placed between the primary-cache and the rest of the memory.
• The memory is implemented using the dynamic components (SIMM, RIMM,
DIMM).
• The access time for main-memory is about 10 times longer than the access time
for L1 cache.

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Memory Hierarchy

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CACHE MEMORIES

• The effectiveness of cache mechanism is based on the property of „Locality of

Reference’. Locality of Reference

• Many instructions in the localized areas of program are executed repeatedly

during some time period

• Remainder of the program is accessed relatively infrequently

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• There are 2 types:
1) Temporal The recently executed instructions are likely to be executed again
very soon.
2) Spatial Instructions in close proximity to recently executed instruction are also
likely to be executed soon.
• If active segment of program is placed in cache-memory, then total execution
time can be reduced.
• Block refers to the set of contiguous address locations of some size.
• The cache-line is used to refer to the cache-block.

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Cache-memory

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• The Cache-memory stores a reasonable number of blocks at a given time.
• This number of blocks is small compared to the total number of blocks available
in main-memory.
• Correspondence b/w main-memory-block & cache-memory-block is specified by
mapping-function.
Write-Through Protocol :Here the cache-location and the main-memory-locations
are updated simultaneously.
Write-Back Protocol
This technique is to → update only the cache-location & → mark the
cache-location with associated flag bit called Dirty/Modified Bit. The word in
memory will be updated later, when the marked-block is removed from cache.

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During Read-operation
• If the requested-word currently not exists in the cache, then read-miss will occur.
• To overcome the read miss, Load–through/Early restart protocol is used.
Load–Through Protocol
The block of words that contains the requested-word is copied from the memory
into cache.
After entire block is loaded into cache, the requested-word is forwarded to
processor.

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During Write-operation

• If the requested-word not exists in the cache, then write-miss will occur.

1) If Write Through Protocol is used, the information is written directly into

main-memory.

2) If Write Back Protocol is used, → then block containing the addressed word is
first brought into the cache & → then the desired word in the cache is over-written
with the new information.

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MAPPING-FUNCTION
• Here we discuss about 3 different mapping-function:

1) Direct Mapping

2) Associative Mapping

3) Set-Associative Mapping

Dr Shreema Shetty
Dept CSE
SCEM 62
DIRECT MAPPING
• The block-j of the main-memory maps onto block-j modulo-128 of the cache (Figure
8.16).
• When the memory-blocks 0, 128, & 256 are loaded into cache, the block is stored in
cache-block 0.Similarly, memory-blocks 1, 129, 257 are stored in cache-block 1.
• The contention may arise when
1) When the cache is full.
2) When more than one memory-block is mapped onto a given cache-block position.
• The contention is resolved by allowing the new blocks to overwrite the currently
resident-block.
• Memory-address determines placement of block in the cache.
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• The memory-address is divided into 3 fields:
1) Low Order 4 bit field : Selects one of 16 words in a block.
2) 7 bit cache-block field : 7-bits determine the cache-position in which new block must
be stored.
3) 5 bit Tag field : 5-bits memory-address of block is stored in 5 tag-bits associated
with cache-location.
• As execution proceeds, 5-bit tag field of memory-address is compared with tag-bits
associated with cache-location.
If they match, then the desired word is in that block of the cache. Otherwise, the block
containing required word must be first read from the memory. And then the word must
be loaded into the cache.

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ASSOCIATIVE MAPPING
• The memory-block can be placed into any cache-block position. (Figure
8.17).
• 12 tag-bits will identify a memory-block when it is resolved in the cache.
• Tag-bits of an address received from processor are compared to the tag-bits
of each block of cache.
• This comparison is done to see if the desired block is present.

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• It gives complete freedom in choosing the cache-location.

• A new block that has to be brought into the cache has to replace an existing
block if the cache is full.

• The memory has to determine whether a given block is in the cache.

• Advantage: It is more flexible than direct mapping technique.

• Disadvantage: Its cost is high.

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SET-ASSOCIATIVE MAPPING
• It is the combination of direct and associative mapping. (Figure 8.18).

• The blocks of the cache are grouped into sets.

• The mapping allows a block of the main-memory to reside in any block of the
specified set.

• The cache has 2 blocks per set, so the memory-blocks 0, 64, 128........ 4032
maps into cache set „0‟.

• The cache can occupy either of the two block position within the set.

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6 bit set field

Determines which set of cache contains the desired block.

6 bit tag field

The tag field of the address is compared to the tags of the two blocks of the set.

This comparison is done to check if the desired block is present.

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71
• The cache which contains 1 block per set is called direct mapping.

• A cache that has „k‟ blocks per set is called as “k-way set associative cache‟.

• Each block contains a control-bit called a valid-bit.

• The Valid-bit indicates that whether the block contains valid-data.

• The dirty bit indicates that whether the block has been modified during its cache
residency.

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Valid-bit=0 When power is initially applied to system.
Valid-bit=1 When the block is loaded from main-memory at first time.
• If the main-memory-block is updated by a source & if the block in the source is
already exists in the cache, then the valid-bit will be cleared to “0‟.
• If Processor & DMA uses the same copies of data then it is called as Cache
Coherence Problem.
• Advantages:
1) Contention problem of direct mapping is solved by having few choices for block
placement.
2) The hardware cost is decreased by reducing the size of associative search.

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REPLACEMENT ALGORITHM
• In direct mapping method, the position of each block is pre-determined and there is no need
of replacement strategy.
• In associative & set associative method,The block position is not pre-determined.If the
cache is full and if new blocks are brought into the cache,then the cache-controller must
decide which of the old blocks has to be replaced.
• When a block is to be overwritten, the block with longest time w/o being referenced is
over-written.
• This block is called Least recently Used (LRU) block & the technique is called LRU
algorithm.
• The cache-controller tracks the references to all blocks with the help of block-counter.
• Advantage: Performance of LRU is improved by randomness in deciding which block is to
be over- written.

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Eg:
Consider 4 blocks/set in set associative cache.
2 bit counter can be used for each block.
When a ‘hit’ occurs, then block counter=0; The counter with values originally lower
than the referenced one are incremented by 1 & all others remain unchanged.
When a ‘miss’ occurs & if the set is full, the blocks with the counter value 3 is
removed, the new block is put in its place & its counter is set to “0‟ and other block
counters are incremented by 1.

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PERFORMANCE CONSIDERATION
• Two key factors in the commercial success are 1) performance & 2) cost.
• In other words, the best possible performance at low cost.
• A common measure of success is called the Pricel Performance ratio.
• Performance depends on → how fast the machine instructions are brought to
the processor & → how fast the machine instructions are executed.
• To achieve parallelism, interleaving is used.
• Parallelism means both the slow and fast units are accessed in the same
manner.

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VIRTUAL MEMORY
• It refers to a technique that automatically move program/data blocks into the
main-memory when they are required for execution (Figure 8.24).
• The address generated by the processor is referred to as a virtual/logical
address.
• The virtual-address is translated into physical-address by MMU (Memory
Management Unit).
• During every memory-cycle, MMU determines whether the addressed-word is in
the memory. If the word is in memory. Then, the word is accessed and execution
proceeds.
Otherwise, a page containing desired word is transferred from disk to memory.
• Using DMA scheme, transfer of data between disk and memory is performed.
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VIRTUAL MEMORY ADDRESS TRANSLATION
• All programs and data are composed of fixed length units called Pages (Figure 8.25).

The Page consists of a block-of-words. The words occupy contiguous locations in the
memory.

The pages are commonly range from 2K to 16K bytes in length.

• Cache Bridge speed-up the gap between main-memory and secondary-storage.

• Each virtual-address contains

1) Virtual Page number (Low order bit) and

2) Offset (High order bit).

Virtual Page number + Offset specifies the location of a particular word within a page.

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• Control-bits in Page-table: The Control-bits is used to

1) Specify the status of the page while it is in memory.

2) Indicate the validity of the page.

3) Indicate whether the page has been modified during its stay in the memory.

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TRANSLATION LOOKASIDE BUFFER (TLB)

• The Page-table information is used by MMU for every read/write access (Figure 8.26).

• The Page-table is placed in the memory but a copy of small portion of the page-table is
located within MMU. This small portion is called TLB (Translation LookAside Buffer).

TLB consists of the page-table entries that corresponds to the most recently accessed
pages.

TLB also contains the virtual-address of the entry.

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• When OS changes contents of page-table, the control-bit will invalidate
corresponding entry in TLB.

• Given a virtual-address, the MMU looks in TLB for the referenced-page.

If page-table entry for this page is found in TLB, the physical-address is obtained
immediately.

Otherwise, the required entry is obtained from the page-table & TLB is updated.

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Page Faults
• Page-fault occurs when a program generates an access request to a page that is
not in memory.
• When MMU detects a page-fault, the MMU asks the OS to generate an interrupt.
• The OS
→ suspends the execution of the task that caused the page-fault and
→ begins execution of another task whose pages are in memory.

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• When the task resumes the interrupted instruction must continue from the point of
interruption.
• If a new page is brought from disk when memory is full, disk must replace one of the
resident pages.
In this case, LRU algorithm is used to remove the least referenced page from memory.
• A modified page has to be written back to the disk before it is removed from the
memory.
In this case, Write–Through Protocol is used.

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MEMORY MANAGEMENT REQUIREMENTS
• Management routines are part of the Operating-system.
• Assembling the OS routine into virtual-address-space is called System Space.
• The virtual space in which the user application programs reside is called the User
Space.
• Each user space has a separate page-table.
• MMU uses the page-table to determine the address of the table to be used in the
translation process.

Dr Shreema Shetty
Dept CSE
SCEM 87
• The process has two stages:

1) User State: In this state, the processor executes the user-program.

2) Supervisor State: In this state, the processor executes the OS routines.

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Privileged Instruction

• In user state, the machine instructions cannot be executed.

• Hence a user-program is prevented from accessing the page-table of
system-spaces.
• The control-bits in each entry can be set to control the access privileges granted to
each program.
i.e. One program may be allowed to read/write a given page.
While the other programs may be given only read access.

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