ECE 3103

Digital Electronics
Sequential Logic Circuits

Course Teacher
Dr Rafia Nishat Toma
Associate Professor
ECE Discipline,
Khulna University
Syllabus (Section A)
• Information & Digital Systems
✓ Introduction to digital systems, number systems, weighted and non-weighted
codes, code conversion, binary addition and subtraction, 2‟s complement method.
• Boolean Algebra
✓ Digital logic, Boolean algebra, Boolean function, canonical forms, Karnaugh
maps, minimization of Boolean functions, logic gates and their truth tables, design
methodologies,
• Combinational Logic Circuits
✓ Combinational logic circuit design, arithmetic and data handling logic
circuits, decoder, encoder, multiplexer, demultiplexer.
• Sequential Logic Circuits
✓ SR, JK, T, and D flip-flops, master-slave JK flip-flop, timing diagrams of
different flip-flops, edge-triggered and level triggered timing diagrams, counters, registers,
memory, finite state machine, asynchronous & synchronous sequential systems, reliable
design and fault diagnosis.
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 Outline

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• Frequency Division and Counting
• Asynchronous Counters
• Propagation Delay in Asynchronous Counters
• Synchronous Counters
• Decoding a Counter
• Ring Counter
• Johnson Counter

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❑ Frequency Division and Counting:
• Refer to Figure 1(a), each flip-flop has its J and K inputs at the 1 level, so that it will
change states (toggle) whenever the signal on its CLOCK input goes from HIGH to
LOW. The clock pulses are applied only to the CLK input of flip-flop Q0.
• The output Q0 is connected to the CLK input of flip-flop of Q1, and output Q1 is
connected to the CLK input of flip-flop of Q2. The waveforms in Figure
1(b) show how the flip-flops change states as the pulses are applied. The
following important points to be noted:
(1) Flip-flop Q0 toggles on the negative-going transition of each input clock
pulse.. Thus, the Q0 output waveform has a frequency that is exactly one-half of
the clock pulse frequency.

(2) Flip-flop Q1 toggles each time the Q0 output goes from HIGH to LOW. The
Q1 waveform has a frequency equal to exactly one-half the frequency of Q0
output and therefore one-fourth of the clock frequency.

(3) Flip-flop- Q2 toggles each time the Q1 output goes from HIGH to LOW.
Thus, the Q2 waveform has one-half the frequency of Q1 and therefore one-
eighth of the clock frequency.
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❑ Frequency Division and Counting:

Figure 1. MOD-8 (3-bit) binary UP counter. (a) Logic diagram using J-K flip-flop; (b) waveforms. 5
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❑ Frequency Division and Counting:
• As described above, each flip-flop divides the frequency of its input by 2.
Thus, if were to add a fourth flip-flop to the chain, it would have a frequency
equal to one-sixteenth of the clock frequency, and so on.
• Using the appropriate number of flip-flops, this circuit could divide a
frequency by only power of 2. Specifically, using N flip-flops would produce an
output frequency from the last flip-flop which is equal to 1/2N of the input
frequency.
• This Application of flip-flops is referred to as frequency division.
❑ Counting Operation:
• In addition to functioning as a frequency divider, the circuit of Figure 1 also
operates as a binary counter. This can be demonstrated by examining the
sequence of states of the flip-flops after the occurrence of each clock pulse.
• Figure 2 presents the results in a State Table. Let the Q2Q1Q0 values
represent a binary number where Q2 is the 22 position, Q1 is in the 21 position, and Q0
is in the 20 position.
• The first eight Q2Q1Q0 states in the table should be recognized as the binary
counting sequence from 000 to 111.

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❑ Counting Operation:
• After the first NGT, the FFs are in the 001 state (Q2 = 0, Q1 = 0, Q0 = 1),
which represents 0012 (equivalent to decimal 1); after the second NGT, the
FFs represent 0102, which is equivalent to 210; after three pulses, 0112 = 310 and so
on, until after seven pulses, 1112 = 710.

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Figure 2. State diagram of the MOD-8 binary UP counter.
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❑ Counting Operation:
• On the eight NGT, the FFs return to the 000 state, and the binary sequence
repeats itself for successive pulses. Thus, for the first seven input pulses, the
circuit functions as a binary counter in which the states of the FFs represent a
binary number equivalent to the number of pulses that have occurred.
• This counter can count as high as 1112 = 710 before it returns to 000.

❑ State Transition Diagram:

• Another way to show how the states of the FFs change with each applied
clock pulse is to use a state transition diagram, as illustrated in Figure 3.
Each circle represents one possible state as indicated by the binary number
inside the circle.
• The arrows connecting one circle to another show how one state changes to
another as a clock pulse is applied. By looking at a particular state circle, we can
see which state precedes it and which state follows it.
• For example, looking at the 000 state, we see that this state is reached
whenever the counter is in the 111 state and a clock pulse is applied.

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❑ State Transition Diagram:

Figure 3. State diagram of a MOD-8 binary UP counter.

❑ MOD Number:
• The counter of Figure 1 has 23 = 8 different states (000 through 111). It would be referred to
as a MOD-8 counter, where the MOD number indicates the number of states in the
counting sequence. If a fourth FF were added, the sequence of states would count in binary
from 0000 to 1111, a total of 16 states. This would be called a MOD-16 counter. In general,
if N flip-flops are connected in the arrangement of Figure 1, the counter will have 2N
different states, and so it is a MOD-2N counter. It would be capable of counting up to 2N – 1
before returning to its 0 state. 9
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❑ Asynchronous (Ripple) Counters:
• Figure 4 shows a four-bit binary counter circuit. Recall the following points concerning its
operation:
(1) The clock pulses are applied only to the CLK input of flip-flop A. This flip-flop
A will toggle each time the clock pulses make a negative transition. Note that, J = K = 1
for all FFs.

(2) The normal output of flip-flop A acts as the CLK input for flip-flop B, and so flip-flop
B will toggle each time the A output goes from 1 to 0. Similarly, flip-flop C will toggle
when B goes from 1 to 0, and flip-flop D will toggle when C goes from 1 to 0.

(3) FF outputs D, C, B, and A represent a four-bit binary number with D as the MSB.
Let’s assume that all FFs have been cleared to the “0”state. The waveforms in Figure 4
show that a binary counting sequence from 0000 to 1111 is followed as clock pulses are
continuously applied.

(4) After the NGT of the fifteenth clock pulse has occurred, the counter FFs are in the
1111 condition. After one complete cycle the counter has recycled back to 0000, from
where it will begin a new counting cycle as subsequent clock pulses are applied.

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❑ Asynchronous (Ripple) UP Counters:

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Figure 4. MOD-16 (4-bit) asynchronous UP counter.
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❑ Asynchronous Down Counter:
• All of the counters we have looked at so far have counted upward from zero; that is, they
were up counters. It is a relatively simple matter to construct asynchronous (ripple)
down counters, which will count downward from a maximum count to a zero.

• Before looking at the circuit for a ripple down counter, let us examine the count-down
sequence for a three-bit down counter:

• A, B, and C represent the FF states as the counter goes through its sequence. It can be
seen that, the A flip-flop (LSB) change states (toggles) at each step in the sequence just as it
does in the up counter. The B flip-flop changes states each time A goes from LOW to
HIGH; C changes states each time B goes from LOW to HIGH.

• Thus, in a down counter each FF, except the first, must toggle when the preceding
FF goes from LOW to HIGH. If the FFs have CLK inputs that respond to negative
transitions (HIGH to LOW), then an inverter can be placed in front of each CLK
input; however, the same effect can be accomplished by driving each FF CLK input
from the inverted output of the preceding FF. Figure 8(a) illustrates the logic
diagram of a MOD-8 asynchronous (ripple) down counter and Figure 8(b) shows the
waveforms.

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❑ Asynchronous Down Counter:

Figure 5. MOD-8 asynchronous down counter. (a) Logic diagram; (b) waveforms; (c) state diagram.
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❑ Asynchronous Down Counter:
• The input pulses are applied to the A flip-flop. The 𝐀 output serves as the
CLK input for the B flip-flop; The 𝐁 output serves as the CLK input for the C
flip-flop. The state transition diagram shows the sequence as shown in Figure
8(c).
❑ Propagation Delay in Asynchronous Counters:
• Ripple counters are the simplest type of binary counters, since they require the
components to produce a given counting operation. They do, however,
have one major drawback, which is caused by their basic principle of
operation: each flip-flop is triggered by the transition at the output of the
preceding FF.
• Because of the inherent propagation delay time (tpd) of each FF, the 2nd FF will
not respond until a time tpd after the 1st FF receives an active clock
transition; the 3rd FF will not respond until a time equal to 2tpd after that
clock transition; and so on.
• In other words, the propagation delays of the FFs accumulate so that the N-th FF
cannot change states until a time equal to Ntpd after the clock transition
occurs where the waveforms for a 3-bit ripple counter are shown.

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❑ Asynchronous (Ripple) Counters:
• This type of counter arrangement is called an asynchronous counter because FFs do not change
states in exact synchronism with the applied clock pulses; only flip-flop A responds to the
clock pulses. FF B must wait for FF A to change states before it can toggle; FF C must wait
for FF B, and so on.
• This type of counter is also referred to as a ripple counter due to the way the FFs respond one
after another in a kind of rippling effect.

❑ Asynchronous Counters with MOD numbers < 2N:

• The basic asynchronous counter of Figure 4 is limited to MOD numbers that are equal to 2N,
where N is the number of FFs. This value is actually the maximum MOD number that can
be obtained using N flip-flops.
• The basic counter can be modified to produce MOD numbers less than 2N by allowing the
counter to skip states that are normally part of the counting sequence. One of the most
common methods for doing this is illustrated in Figure 5, where a three-bit counter is shown.
• Disregarding the NAND gate for a moment, we can see that the counter is a MOD-8 binary
counter which will count in sequence from 000 to 111.

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❑ Asynchronous Counters with MOD numbers < 2N:

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Figure 6. MOD-6 (000 to 101) asynchronous UP counter.
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❑ Asynchronous Counters with MOD numbers < 2N:

(a) (b)
Figure 7. (a) Counting sequence of the MOD-6 counter; (b) state transition diagram.

✓ State Transition Diagram:-

• Figure 7(b) is the state transition diagram for the MOD-6 counter of Figure 7 showing
how FFs C, B, A change states as pulses are applied to the CLK input of the flip-flop A.
Recall that each circle represents one of the possible counter states and that the arrows
indicate how one state changes to another in response to an input clock pulse. The dotted
lines indicate the temporary nature of the 110 state. Note that, there is no arrow into the 111 state
because the counter can never advance to that state.
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❑ Asynchronous Counters with MOD numbers < 2N:

• The presence of the NAND gate will alter the sequence as follows:
(1) The NAND is connected to the asynchronous CLEAR inputs of each FF. As long as
the NAND output is HIGH, it will have no effect on the counter. When it goes
LOW, however, it will clear all of the FFs so that the counter immediately goes to the
000 state.
(2) The inputs of the NAND gate are the outputs of the B and C flip-flops, and so the
NAND output will go LOW whenever B = C = 1. This condition will occur when
the counter goes from the 101 state on the NGT of input pulse 6. The LOW at the NAND
output will immediately clear the counter to the 000 state. Once the FFs have been
cleared, the NAND output goes back HIGH, since the B = C = 1 condition no longer exists.
(3) The counting sequence is shown in Figure 8(a).

• Although the counter doesn’t go to the 110 state, it remains there for only a few nanoseconds
before it recycles to 000. Thus, we can essentially say that this counter counts from 000 to 101
and then recycles to 000.

• It essentially skips 110 and 111 so that it goes through only six different states; thus, it is a MOD-
6 counter (000 to 101).

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❑ Asynchronous Counters with MOD numbers < 2N:
✓ Changing the MOD Number:-
• The counter of Figure 5 is a MOD-6 counter because of the choice of inputs to the
NAND gate. Any desired MOD number can be obtained by changing these inputs.
For example, ignoring the very temporary excursion into the 111 state, the counter
would count from 000 through 110 and then recycle back to 000, resulting in a MOD-
7 counter (the inputs of the NAND gate will be A, B, and C i.e., when A = B =
C then the output of the NAND gate will go LOW and clear the values stored in the
flip-flops (Figure 8).

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Figure 8. MOD-7 asynchronous UP counter.
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❑ Propagation Delay in Asynchronous Counters:

Figure 9. Effects of propagation delays in a 3-bit ripple counter.

• The first set of waveforms in Figure 9(a) shows a situation where an input pulse occurs
every 1000 ns and it is assumed that the A flip-flop output toggles 50 ns after the NGT of each
input pulse. As a result, when the fourth input NGT occurs, the C output goes HIGH after a
delay of 150 ns.
• The waveforms of Figure 9(b) shows what happens if the input pulses occur once every 100
ns. Again, each FF output responds 50 ns after the 1-to-0 transition at its CLK input.
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❑ Propagation Delay in Asynchronous Counters:
• Of particular interest is the situation after the falling edge of the fourth input
pulse, where C output does not go HIGH until 150 ns later, which is the same
time that the A output goes HIGH in response to the fifth input pulse. In other
words, C = 1, B = A = 0 (count of 100) never appears, because the input
frequency is too HIGH.
• Problems such as this can be avoided if the period between input pulses is
made longer than the total propagation delay of the counter. That is, for proper
counter operation we need ~

𝑻𝒄𝒍𝒐𝒄𝒌 ≥ 𝑵 × 𝒕𝒑𝒅 (𝟏)

• The maximum frequency that can be used is given by ~
𝟏
𝒇𝒎𝒂𝒙 = 𝑵×𝒕𝒑𝒅 (𝟐)

• Clearly, as the number of FFs in the ripple counter increases, the total
propagation delay increases and fmax decreases. Thus, asynchronous counters are not
useful at very high frequencies, especially for large number of bits. Another
problem caused by propagation delays in asynchronous counters occurs when the
counter outputs are decoded.
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❑ Synchronous (Parallel) Counters:
• The limitations of ripple counters can be overcome with the use of parallel or
synchronous counters in which all of the FFs are triggered simultaneously by the
clock input pulses.
• Since the input pulses are applied to all the FFs, some means must be used to
control when a FF is to toggle and when it is to remain unaffected by a clock
pulse. This is accomplished by using the J and K inputs and is illustrated in
Figure 10 for a 4-bit, MOD-16, synchronous counter.
• If we compare the circuit arrangement for this synchronous counter with its
asynchronous counter part, we can see the following notable differences:
(A) The CLK inputs of all of the FFs are connected together so that the
following clock signal is applied to each FF simultaneously.

(B) Only FF A, the LSB, has its J and K inputs permanently at the HIGH level.
The J,K inputs of other FFs are driven by some combination of FF outputs.

(C) The synchronous counter requires more circuitry than does the
asynchronous counter.

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❑ Design a 3-bit synchronous counter using J-K FLIP-FLOPs.:
➢ Requirements

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❑ Design a 3-bit synchronous counter using J-K FLIP-FLOPs.:

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❑ Design a 3-bit synchronous counter using J-K FLIP-FLOPs.:

Figure 10. A 3-bit synchronous binary UP counter.

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❑ Synchronous UP Counters:

Figure 11. MOD-16 synchronous up counter. (a) Logic diagram; (b) waveforms; (c) state transition
diagram; (d) counting sequence.
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❑ Design of MOD-6 Synchronous UP Counter:
• The count sequence and the flip-flops inputs for MOD-6 synchronous up
counter are given in Figure 12.

Figure 12. Count sequence and flip-flops inputs for MOD-6 synchronous up counter.

• There are 6 states in a MOD-6 synchronous up counter which requires 3 flip-flops. The
remaining 2 states are unused states. We will use don’t care in the K-maps for those unused
states. Now we prepare the K-maps (Figure 12) with Q2, Q1, and Q0 as input variables
and flip-flop inputs as output variables.

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❑ Design of MOD-6 Synchronous Counter:
• The logic/circuit diagram of MOD-6 synchronous up counter is shown in
Figure 14.

Figure 14. Logic/circuit diagram of MOD-6 synchronous up counter.

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❑ Advantage of Synchronous Counters Over Asynchronous:
• In a synchronous counter all of the FFs will change states simultaneously; that is, they are
all synchronized to the NGTs of the input clock pulses. Thus, unlike the asynchronous
counters, the propagation delay of the FFs do not add together to produce the overall delay.
That is, for a synchronous counter,
Total delay = FF tpd + AND gate tpd

• It will generally be much lower than with an asynchronous counter with the same number of
FFs. Thus, a synchronous counter can operate at a much higher input frequency.

❑ Synchronous Down Counter:

• We saw that a ripple counter could be made to count down by using the inverted output
of each FF to drive the next FF in the counter. A parallel down counter can be
constructed in a similar manner– that is, by using the inverted FF outputs to drive the following
J, K inputs.
• For example, the parallel up counter can be converted to a down counter by connecting the 𝐀',
𝐁', 𝐚𝐧𝐝 𝐂' outputs in place of A, B, and C. The counter will then proceed to count 15, 14, 13,
12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 15, 14, and so on. MOD-16 synchronous down counter is
shown in Figure 15.

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❑ Synchronous Down Counter:
• The count sequence and the flip-flop inputs are given in Figure 15.

Figure 15. Count sequence and FF inputs for MOD-16 synchronous down counter.
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❑ Synchronous Down Counter:
• The K-maps are shown in Figure 16.

Figure 16. K-maps for MOD-16 synchronous down counter.

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❑ Synchronous Down Counter:
• We then minimize the K-maps and the resulting minimized expressions are ~
J0 = 1
K0 = 1
J1 = 𝑸𝟎
K1 = 𝑸𝟎
J2 = 𝑸𝟏 𝑸𝟎
K2 = 𝑸𝟏 𝑸𝟎
J3 = 𝑸𝟐 𝑸𝟏 𝑸𝟎
K3 = 𝑸𝟐 𝑸𝟏 𝑸𝟎
• The logic/circuit diagram of the MOD-16 synchronous down counter is
shown in Figure 16(a).

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❑ Synchronous Down Counter:

Figure 17. MOD-16 synchronous down counter. (a) Logic diagram; (b) waveforms. 34
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❑ Synchronous Up/Down Counter:
• The process of designing a 3-bit synchronous binary Up/Down counter with
the control input 𝐔𝐩/𝐃𝐨𝐰𝐧 using J-K flip-flops is discussed below. The
count sequence and the flip-flop inputs are shown in Figure 18.

Figure 18. The count sequence and the flip-flop inputs of 3-bit synchronous
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𝐔𝐩/𝐃𝐨𝐰𝐧 counter.
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❑ Synchronous Up/Down Counter:
• The K-maps (considering the FF outputs as inputs & the FF inputs as outputs)
are shown in Figure 19. The counter counts Up when the control input
𝐔𝐩/𝐃𝐨𝐰𝐧 (M) = 0; It counts down when control input 𝐔𝐩/𝐃𝐨𝐰𝐧 (M) = 1.

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Figure 19. K-maps for 3-bit synchronous 𝐔𝐩/𝐃𝐨𝐰𝐧 counter.
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❑ Synchronous Up/Down Counter:
• Therefore the minimized expressions are obtained as ~
J0 = 1 K0 = 1
J1 = 𝐐𝟎𝐌 + 𝐐𝟎M K1 = 𝐐𝟎𝐌 + 𝐐𝟎M
J2 = 𝐌𝐐𝟏𝐐𝟎 +M𝐐𝟏𝐐𝟎 K2 = 𝐌𝐐𝟏𝐐𝟎 +M𝐐𝟏𝐐𝟎
• The logic/circuit diagram of 3-bit synchronous 𝐔𝐩/𝐃𝐨𝐰𝐧 counter is shown
in Figure 20.

Figure 20. Logic/circuit diagram of 3-bit synchronous 𝐔𝐩/𝐃𝐨𝐰𝐧 counter.

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❑ Synchronous Up/Down Counter:
• The waveforms of the 3-bit synchronous 𝐔𝐩/𝐃𝐨𝐰𝐧 counter is shown in
Figure 21(a).

Figure 21. 3-bit synchronous 𝐔𝐩/𝐃𝐨𝐰𝐧 counter. (a) Waveforms; (b) state
transition diagram.
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❑ Synchronous (Parallel) UP/DOWN Counters:

Synchronous, MOD-16, UP counter

❑ Study 7-5
from Tocci

Synchronous, MOD-16, DOWN counter

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❑ Decoding a Counter:
• A decoding sequence is a logic circuit that generates X different outputs, each
of which detects (decodes) the presence of one particular state of the counter.
The decoder outputs can be designed to produce wither a HIGH or a LOW
level when the detection occurs. An active-HIGH decoder produces HIGH
outputs to indicate detection.
• Figure 22 shows the complete active-HIGH decoding logic for a MOD-8
counter. The decoder consists of eight 3-input AND gate produces a HIGH
output for one particular state of the counter.
• For example, AND gate 0 has its inputs the FF outputs 𝐂, 𝐁, and 𝐀. Thus, its
output will be LOW at all times except when A = B = C = 0, that is, on the
count of 000 (zero).
• Similarly, AND gate 5 has as its inputs the FF outputs C, 𝐁 , and A, so that its
output will go HIGH only when C = 1, B = 0, and A = 1, that is, on the count
101 (decimal 5).

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❑ Decoding a Counter:

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Figure 22. Decoding of a MOD-8 counter using AND gates.
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❑ Ring Counter:
• The simplest shift-register counter is essentially a circulating shift register connected so
that the last FF shifts its value into the first FF. This arrangement is shown in Figure 23 using D-
type FFs (J-K flip-flops can also be used).

Figure 23. Ring counter. (a) Logic diagram; (b) waveforms; (c) sequence table; (d) state transition
diagram. 43
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❑ Ring Counter:
• The FFs are connected so that information shifts from left to right and back around
from Q0 to Q3.For this reason, it is called a ring counter.

• The waveforms, sequence table, and state transition diagram of Figure 23 show the various
states of the FFs as pulses are applied, assuming a starting state of Q3 = 1 and Q2 = Q1 = Q0 = 0.

• After the first pulse, the 1 has shifted from Q3 to Q2 so that the counter is in the 0100 state. The
second pulse produces the 0010 state, and the third pulse produces the 0001 state. On the fourth
clock pulse, the 1 from Q0 is transferred to Q3, resulting in the 1000 state, which is of course,
the initial state. Subsequent pulses cause the sequence to repeat.

• This counter functions as a MOD-4 counter, since it has four distinct states before the sequence
repeats. Note that, each FF output waveform has a frequency equal to one- fourth of the clock
frequency, since this is a MOD-4 ring counter.

• Ring counters can be constructed for any desired MOD number, a MOD-N ring counter
uses N flip-flops connected in the arrangement of Figure 24. In general, a ring counter will
require more flip-flops than a binary counter for the same MOD number.

• Despite the fact that it is less efficient in the use of FFs, a ring counter is still useful because it
can be decoded without the use of decoding gates. The decoding signal for each state is obtained
at the output of its corresponding FF.
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❑ Johnson Counter:
• The basic ring counter can be modified slightly to produce another type of
shift-register counter, which will have somewhat different properties.
• The Johnson or twisted-ring counter is constructed exactly like a normal
ring counter except that the inverted output of the last FF is connected to the
input of the first FF. A 3-bit Johnson counter is shown in Figure 24.

Figure 24. MOD-6 (3-bit) Johnson counter. (a) Logic diagram; (b) waveforms; (c) count sequence;
(d) state transition diagram. 45
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❑ Johnson Counter:
• Note that the 𝐐𝟎 output is connected back to the D input of Q2. This means that the
inverse of the level stored in Q0 will be transferred to Q2 on the clock pulse.
• Assuming that all FFs are initially 0, the waveforms, count sequence, and state
transition diagram of Figure 23 can be generated. Examination of the waveforms and
count sequence reveals the following important points ~
(1) This counter has six distinct states, 000, 100, 110, 111, 011, and 001 before it
repeats the sequence. Thus it is a MOD-6 Johnson counter. Note that, it doesn’t
count in a normal binary sequence.
(2) The waveform of each FF is a square wave at one-sixth the frequency of the
clock. In addition, the FF waveforms are shifted by one clock period with respect
to each other.
• The MOD number of Johnson counter will always be equal to twice the number of the
FFs.
• Thus, it is possible to construct a MOD-N Johnson counter (where N is an even
number) by connecting N/2 flip-flops in a Johnson counter arrangement.

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❑ Decoding a Johnson Counter:
• For a given MOD number, a Johnson counter requires only half the number of FFs
that a ring counter requires, However, a Johnson counter requires decoding gates,
whereas a ring counter does not.

• The Johnson counter uses one logic gate to decode for each count, but each
gate requires only two inputs, regardless of the number of FFs in the counter.
Figure 25 shows the decoding gates for the six state Johnson counter of
Figure 24.

Figure 25. Decoding logic for a MOD-6 Johnson counter.

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❑ Examples of Counter Design:
Example (1): Design the following ripple counters using flip-flops: (a) divide- by-5
and (b) divide-by-7.
Solution:
(a) Divide-by-5 (or MOD-5) Ripple Counter:
MOD-5 ripple counter will count from 000 to 100. Then it recycles back to 000,
i.e. when the flip-flops outputs become 101 (decimal 5) it will recycle to 000 (clear the
outputs of the flip-flops). We need 3 flip-flops to make a divide-by-5 ripple counter,
which is shown in Figure 26.

Figure 26. Divide-by-5 (MOD-5) ripple counter.

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❑ Examples of Counter Design:
Example (1): Design the following ripple counters using flip-flops: (a) divide- by-5 and (b)
divide-by-7.
Solution:
(b) Divide-by-7 (or MOD-7) Ripple Counter:
MOD-7 ripple counter will count from 000 to 110. Then it recycles back to 000,
i.e. when the flip-flops outputs become 111 (decimal 7) it will recycle to 000 (clear the outputs of the
flip-flops). We need 3 flip-flops to make a divide-by-7 ripple counter, which is shown in Figure 27.

Figure 27. Divide-by-7 (MOD-7) ripple counter.

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 Counters
❑ Self Study:
• Tocci: Chapter 7:- Example 7.6, 7.7.
• Jain: Chapter 8:- 8.2-Registers
❑ Homework:
• Design a synchronous decade up/down counter.
• Design a synchronous counter for any given sequences.
• Tocci: Chapter 7:- Exercise 7.9, 7.10, 7.37, 7.39, 7.46.

For Lab Project:

• Design a synchronous decade up (G 1, 3, 5)/down (G 2, 4, 6) counter using
ICs and show the output using seven-segment display.

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 References

1 “Digital Systems: Principles and Applications,” Neal S. Widmer,

Gregory L. Moss, and Ronald J. Tocci, 12th Ed., Pearson (2018).

2 “Modern Digital Electronics,” R. P. Jain, 4th Ed., McGraw-Hill

(2010).

3 “Digital Logic and Computer Design,” M. Morris Mano, Pearson

(2016).

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