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The document describes a VHDL implementation of a traffic light control system named 'gest_feux'. It outlines the entity and architecture, detailing the state machine that manages the light states and transitions based on a clock signal. The design includes outputs for four sets of traffic lights, with specific states and timing for each light change.

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rma040903
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2 views4 pages

code-vhdl

The document describes a VHDL implementation of a traffic light control system named 'gest_feux'. It outlines the entity and architecture, detailing the state machine that manages the light states and transitions based on a clock signal. The design includes outputs for four sets of traffic lights, with specific states and timing for each light change.

Uploaded by

rma040903
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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----------------------------------------------------------------------------------

-- Company:

-- Engineer:

--

-- Create Date: 05/27/2025 04:30:25 PM

-- Design Name:

-- Module Name: gest_feux - Behavioral

-- Project Name:

-- Target Devices:

-- Tool Versions:

-- Description:

--

-- Dependencies:

--

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

--

----------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating

-- any Xilinx leaf cells in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity gest_feux is

-- Port ( );

Port (

clk : in STD_LOGIC;

red1 : out STD_LOGIC;

yellow1 : out STD_LOGIC;

green1 : out STD_LOGIC;

red2 : out STD_LOGIC;

yellow2 : out STD_LOGIC;

green2 : out STD_LOGIC;

red3 : out STD_LOGIC;

yellow3 : out STD_LOGIC;

green3 : out STD_LOGIC;

red4 : out STD_LOGIC;

yellow4 : out STD_LOGIC;

green4 : out STD_LOGIC

);

end gest_feux;

architecture Behavioral of gest_feux is

type state_type is (s0, s1, s2, s3, s4, s5, s6, s7);
signal state : state_type := s0;

signal count : integer := 0;

signal lights : STD_LOGIC_VECTOR(11 downto 0);

begin

-- State-based light control

STATEpro : process(state)

begin

case state is

when s0 => lights <= "001100100100";

when s1 => lights <= "010100100100";

when s2 => lights <= "100001100100";

when s3 => lights <= "100010100100";

when s4 => lights <= "100100001100";

when s5 => lights <= "100100010100";

when s6 => lights <= "100100100001";

when s7 => lights <= "100100100010";

when others => lights <= lights;

end case;

end process;

-- Time-based state transitions and light output mapping

LT : process(clk)

begin

if rising_edge(clk) then

case count is

when 0 => state <= s0; count <= count + 1;


when 20 => state <= s1; count <= count + 1;

when 25 => state <= s2; count <= count + 1;

when 45 => state <= s3; count <= count + 1;

when 50 => state <= s4; count <= count + 1;

when 70 => state <= s5; count <= count + 1;

when 75 => state <= s6; count <= count + 1;

when 95 => state <= s7; count <= count + 1;

when 100 => count <= 0;

when others => count <= count + 1;

end case;

-- Output light assignment

green4 <= lights(0);

yellow4 <= lights(1);

red4 <= lights(2);

green3 <= lights(3);

yellow3 <= lights(4);

red3 <= lights(5);

green2 <= lights(6);

yellow2 <= lights(7);

red2 <= lights(8);

green1 <= lights(9);

yellow1 <= lights(10);

red1 <= lights(11);

end if;

end process;

end Behavioral;

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