Kingdom of Saudi Arabia ‫المملكة العربية السعودية‬

Ministry of Education ‫وزارة التعليم‬

Assignment 4

[1] Suppose a computer using direct mapped cache has 232 words of main memory, and a
cache of 1024 blocks, where each cache block contains 32 words.
(a) How many blocks of main memory are there?
(b) What is the format of a memory address as seen by the cache, i.e., what are the
sizes of the tag, block, and word fields?
(c) To which cache block will the memory reference 000063FA16 map?

[2] Suppose a computer using fully associative cache has 224 words of main memory, and
a cache of 128 blocks, where each cache block contains 64 words.
(a) How many blocks of main memory are there?
(b) What is the format of a memory address as seen by the cache, i.e., what are the
sizes of the tag and word fields?
(c) To which cache block will the memory reference 01D87216 map?

[3] Assume a system’s memory has 128M words. Blocks are 64 words in length and the
cache consists of 32K blocks. Show the format for a main memory address assuming
a 2-way set associative cache mapping scheme. Be sure to include the fields as well
as their sizes.

[4] A 2-way set-associative cache consists of four sets. Main memory contains 2K blocks
of eight words each. Show the main memory address format that allows us to map
addresses from main memory to cache. Be sure to include the fields as well as their
sizes.

[5] Suppose a computer using set associative cache has 216 words of main memory, a
cache of 32 blocks and each cache block contains 8 words.
(a) If this cache is 2-way set associative, what is the format of a memory address as
seen by the cache, i.e., what are the sizes of the tag, set, and word fields?
(b) If this cache is 4-way set associative, what is the format of a memory address as
seen by the cache?

[6] A set-associative cache consists of 64 lines, or slots, divided into four-line sets. Main
memory contains 4K blocks of 128 words each. Show the format of main memory
addresses.

[7] A two-way set-associative cache has lines of 16 bytes and a total size of 8k bytes.
The 64-Mbyte main memory is byte addressable. Show the format of main memory
addresses.

Assignment 4 1
 Kingdom of Saudi Arabia ‫المملكة العربية السعودية‬
Ministry of Education ‫وزارة التعليم‬
Taif University
College of Computers & Information Technology ‫جـــامعــة الطـائف‬
Computer Organization & Design ‫كلية احلاسبات وتقنية املعلومات‬
503325-3 ‫تصميم وتنظيم الحاسب‬

[8] Consider a memory system that uses a 32-bit address to address at the byte level, plus
a cache that uses a 64-byte line size.

(a) Assume a direct mapped cache with a tag field in the address of 20 bits.
Show the address format and determine the following parameters: number
of addressable units, number of blocks in main memory, number of lines in
cache, size of tag.
(b) Assume an associative cache. Show the address format and determine the
following parameters: number of addressable units, number of blocks in
main memory, number of lines in cache, size of tag.
(c) Assume a four-way set-associative cache with a tag field in the address of 9
bits. Show the address format and determine the following parameters:
number of addressable units, number of blocks in main memory, number of
lines in set, number of sets in cache, number of lines in cache, size of tag.

[9] Consider a computer with the following characteristics: total of 1Mbyte of main
memory; word size of 1 byte; block size of 16 bytes; and cache size of 64 Kbytes.

(a) For the main memory addresses of F0010, 01234, and CABBE, give the
corresponding tag, cache line address, and word offsets for a direct-mapped
cache.
(b) Give any two main memory addresses with different tags that map to the
same cache slot for a direct-mapped cache.
(c) For the main memory addresses of F0010 and CABBE, give the
corresponding tag and offset values for a fully-associative cache.
(d) For the main memory addresses of F0010 and CABBE, give the
corresponding tag, cache set, and offset values for a two-way set-
associative cache.

Assignment 4 2
 Kingdom of Saudi Arabia ‫المملكة العربية السعودية‬
Ministry of Education ‫وزارة التعليم‬
Taif University
College of Computers & Information Technology ‫جـــامعــة الطـائف‬
Computer Organization & Design ‫كلية احلاسبات وتقنية املعلومات‬
503325-3 ‫تصميم وتنظيم الحاسب‬

[10] A processor has a 32 bytes main memory and an 8 bytes direct-mapped cache. Table
0. shows the current state of the cache.

Write hit or miss (H or M) under each address in the memory reference. Show the
new state of the cache for each miss in a new table, label the table with address, and
circle the change.
Table 1. After handling address "100112"
Table 0. Initial State of the cache Hit / Miss ( )
Index V Tag Data Index V Tag Data
000 N 000
001 Y 00 M [00001] 001
010 N 010
011 Y 11 M [11011] 011
100 Y 10 M [10100] 100
101 Y 01 M [01101] 101
110 Y 00 M [00110] 110
111 N 111

Table 2. After handling address "000012" Table 3. After handling address "001102"
Hit / Miss ( ) Hit / Miss ( )
Index V Tag Data Index V Tag Data
000 000
001 001
010 010
011 011
100 100
101 101
110 110
111 111

Table 4. After handling address "010102" Table 5. After handling address "011102"
Hit / Miss ( ) Hit / Miss ( )
Index V Tag Data Index V Tag Data
000 000
001 001
010 010
011 011
100 100
101 101
110 110
111 111
Assignment 4 3