Analog input/output

Textbook: Chapter 20, Analog-to-Digital Converter

Chapter 21, Digital-to-Analog Converter

STM32F4xx Technical Reference Manual:

Chapter 11 – Analog to Digital Converters
Chapter 12 – Digital to Analog Converters
1
 The Big Picture – A Depth Gauge
V_ref
// Your software
Analog to ADC_Code = ADC0->R[0];
Pressure
Digital V_sensor = ADC_code*V_ref/1023;
Sensor
Converter Pressure_kPa = 250 * (V_sensor/V_supply+0.04);
Depth_ft = 33 * (Pressure_kPa – Atmos_Press_kPa)/101.3;
Air
Pressure ADC
Voltages
Output Codes
V_sensor ADC_Code V_ref 111..111
111..110
111..101
111..100

V_sensor ADC_Code

000..001
Ground 000..000

1. Sensor detects air pressure and generates a proportional

output voltage V_sensor
2. ADC generates a proportional digital integer (code)
based on V_sensor and V_ref
3. Code can convert that integer to a something more
useful
1. first a float representing the voltage,
2. then another float representing pressure,
3. finally another float representing depth
Analog to digital conversion
 Given: continuous-time electrical signal
v(t), t >=0

 Desired: sequence of discrete numeric values that represent

the signal at selected sampling times :
v(0), v(T), v(2T),…v(nT)
 T = “sampling time”: v(t) “sampled” every T seconds
 n = sample number
 v(nT) = value of v(t) measured at the nth sample time and quantized
to one of 2k discrete levels: k = #bits used to represent v(nT)
 A/D conversion process
v(t) v(t*)
Input signal Sampled signal

v(nT) t T 2T 3T 4T 5T 6T 7T t*
Sampled & quantized
(3/4)Vref

(2/4)Vref
Sampled data sequence:
d=10, 10, 10, 10, 11, 11, 11
(1/4)Vref
Binary values of n, where
(0/4)Vref
1 2 3 4 5 6 7 n v(nT) = (d/4)Vref
 Minimum Sampling Rate:
Nyquist–Shannon Sampling Theorem
 In order to be able to reconstruct the analog input signal, the sampling rate should be
at least twice the maximum frequency component contained in the input signal
 Example of two sine waves have the same sampling values. This is called aliasing.

from wiki.com

 Antialiasing (beyond the scope of this course)

 Pre-filtering: use analog hardware to filtering out high-frequency components and only sampling the
low-frequency components. The high-frequency components are ignored.
 Post-filtering: Oversample continuous signal, then use software to filter out high-frequency
components

5
Digital to Analog Converter
 Digital-to-analog converter (DAC)
 Converts digital data into a voltage signal by a N-bit DAC

𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉
𝐷𝐷𝐷𝐷𝐷𝐷𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜 = 𝑉𝑉𝑟𝑟𝑟𝑟𝑟𝑟 ×
2𝑁𝑁 − 1
 For 12-bit DAC

𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉
𝐷𝐷𝐷𝐷𝐷𝐷𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜 = 𝑉𝑉𝑟𝑟𝑟𝑟𝑟𝑟 ×
4095
 Many applications:
 digital audio
 waveform generation
 Performance parameters
 speed
 resolution
 power dissipation

7
 Binary-weighted Resistor DAC
Reference
Voltage Digital value = 𝐷𝐷3 𝐷𝐷2 𝐷𝐷1 𝐷𝐷0

Analog
output

𝑅𝑅𝑟𝑟𝑟𝑟𝑟𝑟
𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜 = 𝑉𝑉𝑟𝑟𝑟𝑟𝑟𝑟 × × (𝐷𝐷3 × 23 + 𝐷𝐷2 × 22 + 𝐷𝐷1 × 2 + 𝐷𝐷0 )
𝑅𝑅

8
Y. Zhu, Chapter 21
 R-2R Resistor Ladder DAC
(Reference)

Current to
voltage
conversion

Equivalent
resistance = R Equivalent
resistance = R I/2n+1

Number = bnbn-1…b1b0= bn*2n + bn-1*2n-1 + …. + b1*21 + b0*20

 STM32F4xx DAC Overview
 Two independent channels
DAC1 connects to PA4
DAC2 connects to PA5
 DACoutput(12bit) =
VREF×DOR÷4095
 Range from 0 to VREF+
 Several data formats
 Dual-channel mode
X = 1 or 2
 Supports DMA
 Output buffers can be enabled
for better ability to drive
external loads
 DAC data holding registers
Single-Channel Data Formats
Data Holding Register:
D8 DAC_DHR8Rx
D12 DAC_DHR12Lx
D12 DAC_DHR12Rx
(x = 1 (DAC1) or 2 (DAC2)

Dual-DAC mode: trigger simultaneous conversions in both DACs

by writing data to Dual-Data Holding Registers: DAC_DHRxyD[31:0]
Data Holding Register:
DAC2 DAC1 DAC_DHR8RD
DAC2 DAC1 DAC_DHR12LD
DAC2 DAC1 DAC_DHR12RD
11
 DAC conversion
 Data sample is written to one of the data holding registers
DAC_DHRx (DHR corresponding to data format)
 No hardware trigger selected (TENx=0 in DAC_CR register):
 DAC_DHRx updates DAC_DORx after one APB1 clock cycle
 Hardware trigger selected: (TENx=1 in DAC_CR register)
 Update delayed to three APB1 clock cycles after trigger event.
 Depending on power supply voltage and output load, the
analog output voltage will be available after a time
tSETTLING (typically 3us) following DAC_DORx update.

 DACoutput = VREF × DOR ÷ 4095 (12-Bit Mode)

o Output voltage range from 0 to VREF+
 TEN(Trigger Enable)
 The timing diagram when trigger is disabled (TEN=0)
 Conversion begins one APB1_CLK cycle after data written to DHR

 When the trigger is enabled (TEN=1), an external event is selected

to trigger the DAC
 Select hardware triggers from 6 on-chip timers or EXTI line 9
 Can also be triggered by software (set bit in SWTRIG register)
 DAC Registers (partial list)
 DAC Register Boundary = 0x4000 7400 (on APB1)
 DAC_CR (control register) – address offset 0x00
 DAC_SR (status register) – 0x34 (only has DMA underrun flags)
 Channel 1 Data Holding Registers
 DAC_DHR12R1 (Channel 1, 12-bit, right-aligned data) – 0x08
 DAC_DHR12L1 (Channel 1, 12-bit left-aligned data) – 0x0C
 DAC_DHR8R1 (Channel 1, 8-bit right-aligned data) – 0x10
 Channel 2 Data Holding Registers
 DAC_DHR12R2 (Channel 2, 12-bit, right-aligned data) – 0x14
 DAC_DHR12L2 (Channel 2, 12-bit left-aligned data) – 0x18
 DAC_DHR8R2 (Channel 2 8-bit right-aligned data) – 0x1C
 Dual-Channel Data Holding Registers (DAC_DHRxyD)
 DAC Control Register : DAC_CR

 DAC_CR[15:0] for channel 1; DAC_CR[31:16] for channel 2

 EN bit: enable the DAC channel
 TEN bit: trigger enable bit (0 to disable, 1 to enable)
(also determines #clock cycles before DHR load into DOR)
 TSEL bits: trigger selection (if TEN=1)
 BOFF bit: output buffer disable, to enhance the driving ability
but the output may not reach 0 if enabled, set 1 to disable
 MAMP/WAVE bits: To generate noise wave or triangle wave (Only use when TEN is 1)
 DMA EN/DMAU DRIE bits: Enable/configure DMA xfers from memory to DHR
Example: Waveform Generator
 Configure corresponding GPIO pin in analog mode
 Enable the DAC Clock (APB1)
 Enable the DAC
 Configure the DAC
 Trigger Enable
 TEN=0: No trigger/normal mode (not buffered)
 TEN=1: Trigger on selected source
 Periodically write data to DAC DHR data register (8 or 12 bits)
Analog to Digital Converter
 Analog-to-Digital Converter (ADC)
 ADC is important almost to all application fields
 Converts a continuous-time voltage signal within a given range to
discrete-time digital values to quantify the voltage’s amplitudes

x(t) x(n)

ADC

quantize
continuous-time analog signal discrete-time digital values

18
 A/D – Flash Conversion
 A multi-level voltage divider is used to set 1V
R Comparators
voltage levels over the complete range of 7/8 V +
conversion. R 1
 A comparator is used at each level to -

determine whether the voltage is lower or 6/8 V +

R 1
higher than the level. -
 The series of comparator outputs are 5/8 V +
encoded to a binary number in digital logic R 1
(a priority encoder)
4/8 V
-

 Components used +
2Nresistors R Encoder 3

-
0
 2 -1 comparators
N
3/8 V
 Note +

 This particular resistor divider generates

R 0
-
voltages which are not offset by ½ bit, so 2/8 V +
maximum error is 1 bit R 0
 We could change this offset voltage by using -
resistors of values R, 2R, 2R ... 2R, 3R 1/8 V +
(starting at bottom) R 0
-

Vin
 Successive-approximation (SAR) ADC

• Binary search algorithm

to gradually approaches
the input voltage
• Settle into ±½ LSB
bound within the time
allowed
𝑇𝑇𝐴𝐴𝐴𝐴𝐴𝐴 = 𝑇𝑇𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠 + 𝑇𝑇𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶

𝑇𝑇𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶 = N × 𝑇𝑇𝐴𝐴𝐴𝐴𝐴𝐴_𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶

𝑇𝑇𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠 is software configurable

20
 ADC - Successive Approximation Conversion
111111
 Successively approximate input voltage
by using a binary search and a DAC Test voltage
(DAC output)
 SA Register holds current
approximation of result Analog
 Set all DAC input bits to 0 Input
100110

Voltage
 Start with DAC’s most significant bit 100100

100000
Repeat

know 1001xx, try 100110



know 10011x, try 100111

know 100xxx, try 100100
know 10xxxx, try 101000
know xxxxxx, try 100000

know 1xxxxx, try 110000

 Set next input bit for DAC to 1

know 100110. Done.

 Wait for DAC and comparator to
stabilize
 If the DAC output (test voltage) is
smaller than the input then set the
current bit to 1, else clear the current
bit to 0
000000
T1 T2 T3 T4 T5 T6
Start of Time
Conversion
Analog to Digital Converter (ADC)
 Successive approximation ADC
 VIN is approximated as a
static value in a sample and hold (S/H) circuit
 the successive approximation register (SAR) is a
end of conversion
counter that increments each clock
as long as it is enabled by
the comparator
 the output of the SAR is fed
to a DAC that generates a voltage for
comparison with VIN
 when the output of the DAC = VIN the value
of SAR is the digital representation of VIN

Bard, Gerstlauer,
Valvano, Yerraballi
 ADC Performance Metrics
 Linearity measures how well the transition voltages lie on a
straight line.

 Differential linearity measure the equality of the step size.

 Conversion time: between start of conversion and generation of

result

 Conversion rate = inverse of conversion time

Sampling Problems
 Nyquist criterion
 Fsample >= 2 * Fmax frequency component
 Frequency components above ½ Fsample are aliased, distort measured signal

 Nyquist and the real world

 This theorem assumes we have a perfect filter with “brick wall” roll-off
 Real world filters have more gentle roll-off
 Inexpensive filters are even worse (e.g. first order filter is 20 dB/decade, aka
6 dB/octave)
 So we have to choose a sampling frequency high enough that our filter
attenuates aliasing components adequately
Inputs
 Differential
 Use two channels, and compute difference between them
 Very good noise immunity
 Some sensors offer differential outputs (e.g. Wheatstone Bridge)

 Multiplexing
 Typically share a single ADC among multiple inputs
 Need to select an input, allow time to settle before sampling

 Signal Conditioning
 Amplify and filter input signal
 Protect against out-of-range inputs with clamping diodes
 Sample and Hold Devices
 May require analog input signal to be held constant during conversion.
 Peak capture or sampling at a specific point in time may necessitate a sampling device.
 “Sample and Hold”: Analog Input (Vin) is sampled when the Capture switch is closed
and its value is held on capacitor Cadc, where it becomes the analog output Vsample
 S&H devices are incorporated into some A/D converters

26
 STM32F4xx ADC Overview
 Successive approximation conversion
 High sampling speeds
 Conversion range 0 to 3.6 volts
 Supports multiple resolutions:
12, 10, 8 and 6 bits
 16 regular and 4 injected channels
 Supports single and continuous
conversions
 Scan mode for sequence of inputs
 Interrupt generation on
 End of conversion
 Analog watchdog
 Overrun
 Supports DMA transfers
 Analog watchdog
 Temperature sensor
ADC System Fundamentals

Output Registers

ADC
Analog Input
Clock
 ADC Modes

29
Using the ADC
 ADC initialization
 Configure GPIO pin (analog mode)
 Enable ADC clock
 Enable ADC
 Select voltage reference
 Select trigger source
 Select input channel
 Select other parameters
 Trigger conversion
 Read results
 Calibrate? Average?
On-off Control
 For power efficiency, the ADC module is usually turned off (even if it is
clocked).
 If ADON bit in ADC control register 2 is set, the module is powered on;
otherwise it is powered off.
 Good practical to shut down ADC whenever you are not using it.
Clock Configuration
 Analog Clock
 ADCCLK, common to all ADCs
 From APB2 (72Mhz) (Can be prescale by 1,2,4,8 or 16)
 Can be prescaled by 2, 4, 6 or 8, which means at most 36MHz
 ADC common control register(ADC_CCR) bit 17:16

 Digital Interface Clock

 Used for registers read/write access
 From APB2 (72Mhz)
 Need to be enable individually for each channel (RCC_APB2ENR)
ADC Conversion Time
 Programmable sample time for all channels
 Sample time register 1 to 2 (ADC_SMPRx)
 Total conversion time = Tsampling + Tconversion
 Channel Selection

 Two groups of channels

 Regular group
 Up to 16 conversions
 Consists of a sequence of conversions that can be done on any channel in any order
 Specify each sequence by configuring the ADC_SQRx registers
 Specify the total number of conversions by configuring the least 4 bits in the
ADC_SQR1 register
 Injected group
 Up to 4 conversions
 Similar to regular group
 But the sequence is specified by the ADC_JSQR register
 Specify the total number of conversions by configuring the least 2 bits in the
ADC_JSQR register
 Modifying either ADC_SQRx or ADC_JSQR will reset the current ADC process.
 Channel Selection
 Three other channels
 ADC1_IN16 is internally
connected to the
temperature sensor
 ADC1_IN17 is internally
connected to the reference
voltage VREFINT
 ADC1_IN18 is connected
to the VBAT. Can be use as
regular or injected
channel.
 But only available on the
master ADC1 peripheral.
 Voltage Reference Selection

 Input range from VREF- to VREF+

 VREF+ Positive analog reference
 VDDA equal to Vdd
 VREF- Negative analog reference,
=VSSA
 VSSA Grounded and equal to VSS
 By default, can convert input range
from 0 to 3V
 Conversion Trigger Selection
 Can be triggered by software
 Setting SWSTART bit in
control register 2 (ADC_CR2)
for regular group
 Setting JSWSTART bit in
control register 2 (ADC_CR2)
for injected group
 Or by external trigger
 Select the trigger detection
mode
 Specify the trigger event
 Different bits for specifying
regular group and injected
group
Hardware Trigger Sources
 ADC control register 2

 Similar for Injected group

 Conversion Options Selection
 Continuous?
 Single conversion or continuous conversion (CR2 CONT bit)
 Discontinuous mode available(CR1 DISCEN bit)
 Sample time
 Data alignment
 CR2 ALIGN
 Scan mode: convert all the channels
 CR1 SCAN
 Resolution
 CR1 RES[1:0]
 Conversion Completion
 In single conversion mode
 Regular channel
 Store the result into the 16-bit ADC_DR register
 Set the EOC (end of conversion) flag
 Interrupt if EOCIE bit is set
 Injected channel
 Store the result into the 16-bit ADC_JDR1 register
 Set the JEOC (end of conversion injected) flag
 Interrupt if JEOCIE bit is set

 Behave differently in other modes. And if there is a sequence of

conversions, can be specified to set the flag at the end of the sequence
or at the end of every conversion
 Result Registers
 After the conversion, may need extra processing
 Offset subtraction from calibration
 Averaging: 1, 4, 8, 16 or 32 samples
 Formatting: Right justification, sign- or zero-extension to 16 bits
 Output comparison
 Result registers for two groups
 ADC_DR for regular group
 ADC_JDRx(x=1..4) for injected group
 Common Control Register

 Select different modes by writing to MULTI [4:0] bits

 Prescale the clock by writing to ADCPRE bits
 Enable the VBAT or the temperature sensor by setting VBATE or TSVREFE
 Decide the delay between to sampling phases by writing to DELAY bits
 Example: ADC with Timer Interrupts
Main program

ADC
Set up timer timer
interrupt
interrupt
Timer ADC
Peripheral Timer Peripheral
ISR

Wait for Set ADC_Done ADC

DAC_Done = 1 flag ISR

Process Data
 ISR = Interrupt Service Routine
 TIMER ISR starts ADC
Repeat  ADC samples multiple channels
 ADC ISR copies ADC data register to memory

43
 Example: ADC with Timer and DMA
Main program
Set up DMA
Set up timer timer
samplin
interrupt
g DMA
Timer ADC channel Controller
Peripheral Timer Peripheral s
ISR

Wait for Set DMA_Done

DMA_Done = 1 flag

Process Data
 Timer ISR starts ADC and DMA
 DMA automatically copies ADC results of
Repeat multiple channels to memory after each
conversion

44
 Using ADC Values
 The ADC gives an integer representing the input voltage relative to the reference
voltages
 Several conversions may be needed
 For many applications you will need to compute the approximate input voltage
 Vin = …
 For some sensor-based applications you will need to compute the physical parameter value
based on that voltage (e.g. pressure) – this depends on the sensor’s transfer function
 You will likely need to do additional computations based on this physical parameter (e.g.
compute depth based on pressure)
 Data type
 It’s likely that doing these conversions with integer math will lead to excessive loss of
precision, so use floating point math
 AFTER you have the application working, you can think about accelerating the program
using fixed-point math (scaled integers).
 Sometimes you will want to output ASCII characters (to the LCD, for example).
You will need to convert the floating point number to ASCII using sprintf, ftoa, or
another method.
Example: Temperature Sensor
 ADC1 Channel 16
 The minimum ADC sampling time for the temperature channel is 10
microseconds
 Sampling cycles at least 110
 T(°C) = {(Vsense-V25)/Avg_Slope}+25
 V25=Vsense value for 25°C(typical value:0.78V)
 Avg_Slope=average slope of the temperature vs. Vsense curve(typical
value:1.3mv/°C)
 Vsense=DR×3/4096 (If Vref+=3v, Vref-=0v, 12-bit format)
 Statics really vary from board to board!

 Use your finger to press the chip in the center of the board, the
temperature will go high.