DD&CO Module-3 Chapter 2

Machine Instructions and Programs

Memory Locations and Addresses

• Number and character operands, as well as instructions, are stored in the memory of a
computer. The memory consists of many millions of storage cells, each of which can store a
bit of information having the value 0 or 1.
• Because a single bit represents a very small amount of information, bits are seldom handled
individually. The usual approach is to deal with them in groups of fixed size.
• For this purpose, the memory is organized so that a group of n bits can be stored or
retrieved in a single basic operation. Each group of n bits is referred to as a word of
information, and n is called the word length. The memory of a computer can be
schematically represented as a collection of words.

Figure 4: Memory words

Modern computers have word lengths that typically range from 16 to 64 bits. If the word length of a
computer is 32 bits, a single word can store a 32-bit 2’s complement number or four ASCII
characters, each occupying 8 bits. A unit of 8 bits is called a byte.

Figure 5a: Four characters

• Accessing the memory to store or retrieve a single item of information, either a word or a
byte, requires distinct names or addresses for each item location. It is customary to use
numbers from 0 through 2K-1, for some suitable values of k, as the addresses of successive
locations in the memory.
 • The 2k addresses constitute the address space of the computer, and the memory can have
up to 2k addressable locations. 24-bit address generates an address space of 2^24
(16,777,216) locations. A 32-bit address creates an address space of 2^32 or 4G (4 giga)

locations
Figure 5b: A Signed Integer

Byte Addressability: - Assignment of successive addresses to successive byte locations in

the memory is called Byte Addressability.
⚫ It is impractical to assign distinct addresses to individual bit locations in the memory.
⚫ Byte locations have addresses,
⚫ If word length of machine is 16 bits, then successive words are located at addresses 0, 1, 2, …
⚫ If word length of machine is 32 bits, then successive words arelocated at addresses 0, 4, 8…
⚫ If word length is 64 bits, then successive words are located at addresses 0, 8, 16…
.
Big-Endian and Little-Endian Assignments
Big-Endian: Lower byte addresses are used for the most significant bytes (the left most bytes) of the
word and higher byte addresses are used for the least significant bytes of the word

Little-Endian: Opposite ordering, lower byte addresses are used for the less significant bytes (the
rightmost bytes) of the word and higher byte addresses are used for the most significant bytes of the
word.

Figure 6: Byte and word addressing

Example Data=22334455 to illustrate Big-Endian and Little-Endian Assignments

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 Figure 7: Example to illustrate Big-Endian and Little-Endian Assignments

Word Alignment
⚫ Address ordering of bytes
⚫ Word alignment
⚫ Words are said to be aligned in memory if they begin at a byte addressing. Thatis a multiple of the number of
bytes in a word (n).
▪ 16-bit word: word addresses: 0, 2, 4,….(multiple of 2)
▪ 32-bit word: word addresses: 0, 4, 8…. .(multiple of 4)
▪ 64-bit word: word addresses: 0, 8, 16… (multiple of 8)

Memory Operations
Both program instructions and data operands are stored in the memory. To execute an instruction, the
processor control circuits must cause the word (or words) containing the instruction to be transferred
from the memory to the processor. Operands and results must also be moved between the memory
and the processor.

Thus, two basic operations involving the memory are needed, namely, Load (or Read or Fetch) and
Store (or Write).

Load (or Read or Fetch):

⚫ The load operation transfers a copy of the contents of a specific memory location to the
processor, t he memorycontents remain unchanged.
⚫ To start a Load operation, the processor sends the address of the desired location to the
memory and requests that its contents are to be read.
⚫ The memory reads the data stored at that address and sends them to the processor

Store operation:
⚫ The store operation transfers an item of information from the processor to a specific memory
location, destroying the former contents of that location.
⚫ The processor sends the address of the desired location to the memory, together with the data
to be written into that location.

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 ⚫ An information item of either one word or byte is transferred b/w Memory and Processor in a
single operation
⚫ An information item of either one word or one byte can be transferred between the processor
and thememory in a single operation. Actually, this is transfer in between the CPU register
and main memory.

Instructions and Instruction Sequencing

A computer must have instructions capable of performing four types of operations.
• Data transfers between the memory and the processor registers
• Arithmetic and logic operations on data
• Program sequencing and control
• I/O transfers

Two ways of representing instructions are -

1. Register Transfer Notation:-
• Transfer of information from one location in the computer to another. Possible locations that
may be involved in such transfers are memory locations processor registers, or registers in the
I/O subsystem.
• Example, names for the addresses of memory locations may be LOC, PLACE, A, VAR2;
processor registers names may be R0, R5; and I/O register names may be DATAIN,
OUTSTATUS, and so on.
• The contents of a location are denoted by placing square brackets around the name of the
location. Thus, the expression is

R1 ← [LOC]

Means that the contents of memory location LOC are transferred into processor register R1.

As another example, consider the operation that adds the contents of registers R1 and R2, and then
places their sum into register R3. This action is indicated as
R3 ← [R1] + [R2]
This type of notation is known as Register Transfer Notation (RTN). Note that the right-hand side of
an RTN expression always denotes a value, and the left-hand side is the name of a location where the
value is to be places, overwriting the old contents of that location.

2. Assembly Language Notation:-

• We can use assembly language format to represent machine instructions and programs. For
example, an instruction that causes the transfer described above, from memory location LOC
to processor register R1, is specified by the statement.
Move LOC, R1
• The contents of LOC are unchanged by the execution of this instruction, but the old contents
of register R1 are overwritten.
• The second example of adding two numbers contained in processor registers R1 and R2 and
placing their sum in R3 can be specified by the assembly language statement.
Add R1, R2, R3

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Basic Instruction Types
The operation of adding two numbers is a fundamental capability in any computer. The statement
• C=A+B
In a high-level language program is a command to the computer to add the current values of the two
variables called A and B, and to assign the sum to a third variable, C. When the program containing
this statement is compiled, the three variables, A, B and C, are assigned to distinct locations in the
memory. We will use the variable names to refer to the corresponding memory location addresses.

According to address reference there four type of instruction:

• Three Address Instruction
• Two Address Instruction
• One Address Instruction
• Zero Address Instruction

1. Three Address Instruction:

The general format for three address instruction is:

Operation source1, source2, destination

Ex- Add R1, R2, R3

Where R1, R2, R3 are the variables. These variable names are assigned to the distinct location in the
memory. In this instruction operand R1 and R2 are the source operand and operand R3 is the
destination operand.
The number of bits required to represent such instruction include:
• Bits required to specify the three memory addresses of the three operands. If n-bits required to
specify one memory address, 3n bits are required to specify three memory addresses.
• Bits required specifying the operation.

2. Two Address Instruction:

The General format for the two address notation is;
Operation Source1, Destination
Ex-Add A, B
Where A, B are the variables. These variable names are assigned to the distinct location in the
memory. In this instruction operand A is the source operand and operand B serve as both source and
destination operand.
The number of bits required to represent such instruction include:
• Bits required specifying the two memory addresses of the two operands. If n-bits required to
specify one memory address, 2n bits are required to specify two memory address.
• Bits required specifying the operation.

3. One Address Instruction:

Instruction specifies only memory operand which may be source or destination. The other operand is
implied to be processor register called accumulator.
The general format for one address instruction is:

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Operation source1
Load A Load A, AC
Ex- ADD B ===> Add B➔ ADD B, AC Where AC= accumulator register.
Store C Store AC, C

Instruction loads the contents of variable A into the processor register called accumulator and add
the contents of accumulator to register B and store the result back into accumulator. Then store the
content of accumulator into register C
The number of bits required to represent such instruction include:
• Bits required to specify the one memory addresses of the one operands. If n-bits required to
specify one memory address, 1n bits are required to specify one memory address.
• Bits required specifying the operation.

4. Zero address instruction

Location of all operand is defined implicitly. The operands are stored in a structure called
Pushdown stack.
Ex – ADD TOS ← TOS + (TOS – 1)
INSTRUCTION EXECUTION AND STRAIGHT-LINE SEQUENCING

Consider task C ← [A] + [B] for example. Figure shows a possible program segment for this task as
it appears in the memory of a computer.
• The memory is byte addressable, word length is 32 bits and the processor has a number of
registers. We use a two address instruction format and instructions stored in successive
memory word locations, starting at location i. Since each instruction is 4 bytes long, the
second and third instructions start at addresses i + 4 and i + 8.

• The processor contains a register called the Program Counter (PC), which holds the address
of the instruction to be executed next. To begin executing a program, the address of its first
instruction (i in our example) must be placed into the PC.
• Then, the processor control circuits use the information in the PC to fetch and execute
instructions, one at a time, in the order of increasing addresses. This is called Straight-Line
Sequencing.
• During the execution of each instruction, the PC is incremented by 4 to point to the next
instruction. Thus, after the Move instruction at location i + 8 is executed, the PC contains the
value i + 12, which is the address of the first instruction of the next program segment.

Figure 8: A Program for C[A]+[B]

Executing is performed in two-phase procedure.
1. Instruction fetch, the instruction is fetched from the memory location whose address is in the PC.
This instruction is placed in the instruction register (IR) in the processor.
2. Instruction execute, the instruction in IR is examined to determine which operation is to be
performed. The specified operation is then performed by the processor. This often involves fetching
operands from the memory or from processor registers, performing an arithmetic or logic operation,
and storing the result in the destination location. At some point during this two-phase procedure, the
contents of the PC are advanced to point to the next instruction.
When the execute phase of an instruction is completed, the PC contains the address of the next
instruction, and a new instruction fetch phase can begin.
In most processors, the execute phase itself is divided into a small number of distinct phases
corresponding to fetching operands, performing the operation, and storing the result

Branching

Consider execution of decision making instruction (branch instruction), we cannot use the
straight–line sequencing always. Based on evaluation of branch condition the control my follow
straight line sequencing or it may transfer the program control from one straight-line sequence to
another straight line sequencing.

Consider the task of adding a list of n numbers. The program outlined in Figure 9a is a
generalization of the program in above Figure.
The addresses of the memory locations containing the n numbers are symbolically given as NUM1,
NUM2, . . . , NUMn, and a separate Add instruction is used to add each number to the contents of
register R0.
After all the numbers have been added, the result is placed in memory location SUM. Instead of
using a long list of Add instructions, it is possible to place a single Add instruction in a program loop,
as shown in Figure 9b. The loop is a straight-line sequence of instructions executed as many times as
needed. It starts at location LOOP and ends at the instruction Branch>0. During each pass through
this loop, the address of the next list entry is determined, and that entry is fetched and added to R0.
Figure 9a: A straight-line program for adding Figure 9b: Using a loop to add n numbers
n Numbers

Condition Codes:

The processor keeps track of information about the results of various operations for use by
subsequent conditional branch instructions. This is accomplished by recording the required
information in individual bits, often called condition code flags. These flags are usually grouped
together in a special processor register called the condition code register or status register.
Individual condition code flags are set to 1 or cleared to 0, depending on the outcome of the operation
performed.
• Carry/Borrow Flag: The carry bit is set when the summation of two 8 bit number is greater
than 1111 1111.A borrow bit is generated when a large number is subtracted from a smaller
number.

• Zero Flag: The zero bit is set when the contents of register are zero after any operation. This
happens not only when we decrement the register, but also any arithmetic and logical
operation.

• Negative or sign Flag: In 2’s complement arithmetic, the most significant bit is a sign bit. If
the bit is logic 1, then number is negative number, otherwise a positive number.

• Auxiliary Flag: The auxiliary carry bit of status register is set when an addition in the 4 bit
cause a carry into the fifth bit.

• Overflow Flag: This flag is set if the result of signed operation is too large to fit in the
number of bit available to represent it.

• Parity Flag: When the result of an operation leaves the even number of 1’s then parity is set.

N (negative): Set to 1 if the result is negative; otherwise, cleared to 0

Z (Zero): Set to 1 if the result is 0; otherwise, cleared to 0
V (Overflow): Set to 1 if arithmetic overflow occurs; otherwise, cleared to 0
C (Carry): Set to 1 if any carry-out results from the operation; otherwise, cleared to 0

Addressing Modes
Programs are normally written in a high-level language, which enables the programmer to use
constants, local and global variables, pointers, and arrays. The different ways in which the location of
an operand is specified in an instruction are referred to as Addressing Modes.
 Table1: Generic addressing modes

Implementation of Variables and Constants:

Variables and constants are the simplest data types and are found in almost every computer program.
In assembly language, a variable is represented by allocating a register or a memory location to hold
its value. Thus, the value can be changed as needed using appropriate instructions.
1) REGISTER MODE - The operand is the contents of a processor register; the name (address) of
the register is given in the instruction.
Move R1, R2
The effective address of register mode is Ea=Ri

2) ABSOLUTE MODE – The operand is in a memory location; the address of this location is
given explicitly in the instruction. (In some assembly languages, this mode is called Direct).
Move LOC, R2
The effective address of absolute mode is Ea=Loc

3) IMMEDIATE MODE – The operand is given explicitly in the instruction. For example, the
instruction Move #200, R0
Places the value 200 in register R0. Clearly, the immediate mode is only used to specify the value of
a source operand. Using a subscript to denote the immediate mode is not appropriate in assembly
languages. A common convention is to use the sharp sign (#) in front of the value to indicate that
this value is to be used as an immediate operand
The effective address of immediate mode is Operand=value

Indirection and Pointers:

In the addressing modes that follow, the instruction does not give the operand or its address
explicitly, inst ead, it provides information from which the memory address of the operand can be
determined. We refer to this address as the effective address (EA) of the operand.

4. INDIRECT MODE – The effective address of the operand is the contents of a register or
Memorylocation whose address appears in the instruction.
For example: Move #num, R1
Add (R1), R0
In the above instruction, the address of the number is copied into the register R1, whenever second
instruction is executed; the content of the number is moved to the register R2.
The effective address of indirect mode is
Ea=(Ri) //register
Ea=(Loc) //memory

Figure 10: Indirect Addressing

Figure 11: Use of indirect addressing in the program

In the program shown Register R2 is used as a pointer to the numbers in the list, and the
operands are accessed indirectly through R2. The initialization section of the program loads the
counter value n from memory location N into R1 and uses the immediate addressing mode to place
the address value NUM1, which is the address of the first number in the list, into R2.
Then it clears R0 to 0. The first two instructions in the loop implement the unspecified instruction
block starting at LOOP. The first time through the loop, the Instruction Add (R2), R0 fetches the
operand at location NUM1and adds it to R0. The second Add instruction adds 4 to the contents of the
pointer R2, so that it will contain the address value NUM2 when the above instruction is executed in
the second pass through the loop.

Indexing and Arrays:

A different kind of flexibility for accessing operands is useful in dealing with lists and arrays.

5. INDEX MODE – the effective address of the operand is generated by adding a constant value to the
contents of a register
Move X(R1), R2
The register use may be either a special register provided for this purpose, or, more commonly; it
may be any one of a set of general-purpose registers in the processor. In either case, it is referred to
asindex register.
We indicate the Index mode symbolically as X (Ri)
Where X denotes the constant value contained in the instruction and Ri is the name of the
register involved. The effective address of the operand is given by EA = X + [Rj]

Figure 13: Indexed Addressing

Figure 13 illustrates two ways of using the Index mode-

In fig a, the index register, R1, contains the address of a memory location, and the
value X defines an offset (also called a displacement) from this address to the location where
the operand is found.
An alternative use is illustrated in fig b. Here, the constant X corresponds to a memory
address, and the contents of the index register define the offset to the operand. In either case, the
effective address is the sum of two values; one is given explicitly in the instruction,and the other is stored in a
register. Consider a simple example involving a list of test scores for students taking a given course.
 Figure 14: A list of Student’s Marks
Assume that the list of scores beginning at location LIST is structured as shown in the figure 14. A four-
word memory block comprises a record that stores the relevant information for each student. Each record
consists of the student’s identification number (ID), followed by the scores the student earned on three
tests.
There are n numbers of students in the class and the value n is stored in location N immediately in front of
the list. We know that the list represents the two-dimensional array having n rows and columns. Each row
contains the entries for one student, and the columns give the IDs and test scores.

Figure 15: Indexed addressing used in decreasing test scores in the list

To compute the sum of all scores obtained on each of the tests and score these three sums in memory
locations SUM1, SUM2, and SUM3. In the body of the loop, the program uses the Index addressing mode
to access each of the scores in the student’s record. Register R0 is used as the index register. Before the
loop is entered, R0 is set to the ID location of the first student record; it contains the address LIST.

On the first pass through the loop, test scores of the first student are added to the running sums held in
registers R1, R2, and R3, which initially cleared to 0. These scores accessed using the Index addressing
modes 4(R0),8(R0), 12(R0). The index register R0 is then incremented by 16 to point to the ID location of
the second student. Register R4, initialized to contain the value n, is decremented by 1at the end of the
each pass through the loop. When the contents of the R4 reach 0, all student records have been accessed,
and the loop terminates. Until then, the conditional branch instruction transfers control back to the start of
the loop to process the record. The last three instructions transfer the accumulated sums from registers R1,
R2, and R3, into memory locations SUM1, SUM2, SUM3.

Relative Addressing:
6. RELATIVE MODE: The effective address is determined by the index mode using program
counter inplace of the general purpose processor register.
EA= [PC] +x
This addressing mode commonly used to specify the target address in the branch instruction.
For example Branch > 0 LOOP
Causes program execution to go to the branch target location identified by the name LOOP if
the branch condition is satisfied. This location can be computed by specifying it as an offset
from the current value of the program counter. Since the branch target may be either before or
after the branch instruction, the offset is given as a signed number

Additional Modes:
7. AUTO INCREMENT MODE: The effective address of the operand is the content of a
register specified in the instruction. After accessing the operand ,the contents of this register
are incremented to the address the next instruction

For example: MOV (R2)+,R0

The effective address of auto increment mode is EA=[Ri]

Figure 16: The Auto increment addressing mode used in program

8. AUTO DECREMENT MODE – The contents of a register specified in the instruction are
first automatically decremented and are then used as the effective address of the operand.
Notation is –(Ri)
Where -(Ri)- The decrement is 1 for byte-sized operands
2 for 16-bit operands, and
4 for 32-bit operands.
Basic Input and Output Operations:
Consider a task that reads in character input from a keyboard and produces character output on a
display screen. A simple way of performing such I/O tasks is to use a method known as
program- controlled I/O.
• The transfer of data between keyboard and processor and display device is called
Input/Output data transfer or I/O data transfer
• The rate of data transfer from the keyboard to a computer is limited by the typing speed
of theuser, which is unlikely to exceed a few characters per second.
• The rate of output transfers from the computer to the display is much higher. Due to the
speedbetween these devices we have to synchronization mechanism for proper transfer
of data between them.
Figure shows the typical bus connection for processor, keyboard and display. The DATAIN
and DATAOUT are the register by which the processor reads the contents from keyboard and
sends the data for display respectively. SIN and SOUT are status bit used to synchronize data
transfer between keyboard and processor and data transfer between display and processor

respectively.
Figure 17: Bus connection for processor, keyboard, and display

• When a key is pressed, the corresponding character code is stored in the DATAIN
register and SIN status bit is set(SIN=1) it indicate that the valid character code is
available in the DATAIN register. Under the program control processor check the SIN
bit and when it finds SIN =1, it read the contents of the DATAIN register. After the
completion of read operation SIN is automatically cleared to 0 and process repeats.

• When the character is transferred from the processor to the display, DATAOUT
register and SOUT status bit are used. Under program control, processor checks SOUT
bit. If SOUT is set(SOUT=1) it indicates that the display is ready to receive character
than processor sends data to DATAOUT register which clears SOUT status to 0 and
process repeats