Unit - III

GPIO Ports

Unit - IV
Embedded C Program on Digital Interface
Referefence:
Muhammad Ali Mazidi, Sarmad Naimi, SepehrNaimi, “The stm32f103 arm
microcontroller and embedded systems: Using assembly and c", 1st Edition,
MicroDigitalEd, 2020
 I/O unit in ARM

RAM Timers

PROGRAM
ROM

Program
Bus Bus
CPU

Interrupt Other
OSC I/O Port
Unit Peripherals

I/O
PINS

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 GPIO pins
 PORTA (PAn) – PA0 – PA15
 PORTB (PBn) – PB0 – PB15
 PORTC (PCn) – PC0 – PC15
 PORTD – PD0 & PD1

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GPIO pins in STM32 Board

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 GPIO Registers
 Only Ports A – D available in STM32F103C6T6

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 GPIO Registers
Register Name Size Role of the Register

Configuration registers 32 Each port bit of the GPIO Ports, can be individually
(GPIOx_CRL & GPIOx_CRH) configured by software in several modes
Data register (GPIOx_IDR) 32 The Input Data register (GPIOx_IDR) captures the data
present on the I/O pin at every APB2 clock cycle
Data register (GPIOx_ODR) 32 Data send as output on the I/O pin. It is possible to use
the output driver in Push-Pull mode or Open-Drain
mode
Bit Set/Reset Register 32 The purpose of the GPIOx_BSRR and GPIOx_BRR
(GPIOx_BSRR) registers is to allow atomic read/modify accesses to any
Bit Reset Register 16 of the GPIO registers.
(GPIOx_BRR)
Bit locking register 32 The locking mechanism allows the IO configuration to
(GPIOx_LCKR) be frozen. When the LOCK sequence has been applied
on a port bit, it is no longer possible to modify the value
of the port bit until the next reset.

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 CRL and CRH (Configuration Registers)

Output (MODE>00)
CNFx bits Configuration MODEx Direction Max speed
bits
00 General purpose output push-pull
00 Input
01 General purpose output Open-drain
01 10 MHz
10 Alternate function output Push-pull 10 Output 2 MHz
11 Alternate function output Open-drain 11 50 MHz
Input (MODE=00)

CNFx bits Configuration Description

00 Analog mode Select this mode when you use a pin as an ADC input.
01 Floating input In this mode, the pin is high-impedance.
10 Input with pull- The value of ODR chooses if the pull-up or pull-down
up/pull-down resistor is enabled. (1: pull-up, 0:pull-down)
11 reserved 7
 GPIO Registers
Port input data register (GPIOx_IDR) (x=A..C)
Address offset: 0x08 and Reset value: 0x0000 xxxx

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 IDRy: Port input data (y= 0 .. 15): These bits are read only and can be
accessed in Word mode only. They contain the input value of the corresponding I/O port.
Port output data register (GPIOx_ODR) (x=A..C)
Address offset: 0x0C and Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 ODRy: Port output data (y= 0 .. 15): These bits can be read and written by
software and can be accessed in Word mode only. For atomic bit set/reset, the ODR bits
can be individually set and cleared by writing to the GPIOx_BSRR register (x = A .. C)
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IDR (Input Data Reg.) and ODR (Output Data Reg.)

 Each I/O port bit is freely

programmable
 But I/O port registers have to
be accessed as 32-bit words
 Half-word or byte accesses
are not allowed

GPIOx->ODR: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

GPIOx->IDR: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Px15 Px14 Px13 Px12 Px11 Px10 Px9 Px8 Px7 Px6 Px5 Px4 Px3 Px2 Px1 Px0

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 GPIO Register
Port Bit Set / Reset Register (GPIOx_BSRR) (x=A..C)
Address offset: 0x10 and Reset value: 0x0000 0000

Bits 31:16 BRy: Port x Reset bit y (y= 0 .. 15)

These bits are write-only and can be accessed in Word mode only.
0: No action on the corresponding ODRx bit
1: Reset the corresponding ODRx bit
Note: If both BSx and BRx are set, BSx has priority.

Bits 15:0 BSy: Port x Set bit y (y= 0 .. 15)

These bits are write-only and can be accessed in Word mode only.
0: No action on the corresponding ODRx bit
1: Set the corresponding ODRx bit

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 GPIO Register
Port Bit Reset Register (GPIOx_BRR) (x=A..C)
Address offset: 0x14 and Reset value: 0x0000 0000

Bits 31:16 Reserved

Bits 15:0 BRy: Port x Reset bit y (y= 0 .. 15)

These bits are write-only and can be accessed in Word mode only.
0: No action on the corresponding ODRx bit
1: Reset the corresponding ODRx bit

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 Clearing pins
 BRR (Bit Reset Register)

 Examples:
 GPIOB->BRR = 1<<5; //make PB5 low
 GPIOA->BRR = (1<<3)|(1<<5); // make PA3 and PA5 low

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 Setting & Clearing Pins
 BSRR (Bit Set/Reset Register)

 Examples:
 GPIOC->BSRR = (1<<5); //make PC5 high
 GPIOB->BSRR = (1<<5)|(1<<19); /*makes PB5 high and

PB3 low */

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 Toggle Port A
#include "stm32f10x.h“
void delay_ms(uint16_t t) {
volatile unsigned long l = 0;
for(uint16_t i = 0; i < t; i++)
{ for(l = 0; l < 6000; l++); }
}

int main() {
RCC->APB2ENR |= 0xFC; //Enable the clocks for GPIO ports

GPIOA->CRL = 0x33333333; //PA0 to PA7 as outputs

GPIOA->CRH = 0x33333333; //PA8 to PA15 as outputs
while(1) {
GPIOA->ODR = 0x0000; //make all the pins of Port A low
delay_ms(1000); //wait 1000ms
GPIOA->ODR = 0xFFFF; //make all the pins of Port A high
delay_ms(1000); //wait 1000ms
}
}
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 Toggling PC13
#include <stm32f10x.h>

void delay_ms(uint16_t t);

int main()
{
RCC->APB2ENR |= 0xFC; //Enable GPIO ports clocks

GPIOC->CRH = 0x44344444; //PC13 as output

while(1)
{
GPIOC->ODR ^= (1<<13); //toggle PC13
delay_ms(1000);
}
}
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7-segment

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 Example: Display 3 on the 7-segment
 A 7-segment is connected to PA0-PA7. Display 3 on
the 7-segment.
CRL: 3 3 3 3 3 3 3 3
ODR: 0 1 0 0 1 1 1 1 CC

STM32F10X 0
#include <stm32f10x.h> 5 1
8 6
int main() { PORTA

RCC->APB2ENR |= 0xFC; //ENABLE GPIO clocks 4 2

GPIOA->CRL = 0x33333333; //PA0-PA7 as outputs 3

GPIOA->ODR = 0x4F; //display 3

while(1) {
}
}

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 Example
 A switch is connected to pin PB10 and an LED to pin PC13. Write a
program to get the status of SW and send it to the LED.
PB10 –Input & PC13 - Output VCC STM32F103

#include <stm32f10x.h> 10K

int main() { PB10 PC13

100

RCC->APB2ENR |= 0xFC; /* Enable GPIO ports clocks */

GPIOB->CRH = 0x44444444; /* PB8-PB15 as inputs */
GPIOC->CRH = 0x44344444; /* PC13 as output */
while(1) {
if((GPIOB->IDR & (1<<10)) != 0) /* is PB10 high*/
GPIOC->ODR |= (1 << 13); /* make PC13 high */
else
GPIOC->ODR &= ~(1 << 13); /* make PC13 low */
}
}

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 Internal Pull-up/Pull-down resistor

bit n of ODR

In CRH:CRL Pin n
0x4 = input bit n of IDR of port
(no pull-up/down)
0x8 = input with
pull-up/down CRH:CRL = 0x8
ODR = 1
Using internal pull-up
MCU MCU
VCC
VCC

Px.n Px.n

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 Example
 A switch is connected to pin PB10 and an LED to pin PC13. STM32F103

Write a program to get the status of SW and send it in LED.

PB10 PC13
100
#include <stm32f10x.h>
int main() {
RCC->APB2ENR |= 0xFC; /* Enable GPIO ports clocks */
GPIOB->CRH = 0x44444844; /* pull-up PB10 */
GPIOB->ODR |= (1<<10); /* set bit 10 of ODR to pull-up */
GPIOC->CRH = 0x44344444; /* PC13 as output */
while(1) {
if((GPIOB->IDR & (1<<10)) != 0) /* if PB10 high */
GPIOC->ODR |= (1 << 13); /* make PC13 high */
else
GPIOC->ODR &= ~(1 << 13); /* make PC13 low */
}
}
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Electrical Characteristics

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