Imam Abdulrahman Bin Faisal University

College of Computer Science & IT

Department of Computer Engineering

CSE 210: Digital Logic Design

Chapter#5: Sequential Logic

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 Introduction
Hand-held devices, cell phones, navigation receivers, personal computers, digital
cameras, personal media players, and virtually all electronic consumer products
have the ability to send, receive, store, retrieve, and process information
represented in a binary format. The technology enabling and supporting these
devices is critically dependent on electronic components that can store
information, i.e., have memory.

Traffic light ATM Vending machine

The digital circuits considered thus far have been combinational - their output
depends only and immediately on their inputs - they have no memory, i.e.,
dependence on past values of their inputs.
Sequential circuits, however, act as storage elements and have memory. They
can store, retain, and then retrieve information when needed at a later time.
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 Sequential Circuits
In sequential circuits, the present output depends on the present input as well as
the past output(s).
In contrast, the outputs of combinational circuits depend only on the present
values of the inputs.

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 Synchronous Sequential Circuits
A synchronous sequential circuit employs signals that affect the storage
elements at only discrete instants of time.

Synchronization is achieved by a timing device called a clock generator,

which provides a clock signal having the form of a periodic train of clock
pulses.

The storage elements (memory) used in clocked sequential circuits are

called flipflops.

A flip-flop is a binary storage device capable of storing one bit of

information.

In a stable state, the output of a flip-flop is either 0 or 1. A sequential circuit

may use many flip-flops to store as many bits as necessary.

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 Storage Elements: Latches
SR Latch:
The most basic type of flip-flops are the latches that operates
with Signal levels. Latches are building blocks of all flip-flops.

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SR Latch:
S R Q0 Q Q’
0 0 0 0 1 Q = Q0

R 0 0
Q

S Q
0 1

Initial Value

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SR Latch:
S R Q0 Q Q’
0 0 0 0 1 Q = Q0
0 0 1 1 0 Q = Q0

R 0 1
Q

S Q
0 0

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SR Latch:
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1 Q=0
R 1 0
Q

S Q
0 1

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SR Latch:
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1 Q=0
R 1 1
Q
0 1 1 0 1 Q=0

S Q
0 0

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SR Latch:
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
R 0
Q=0
0 0 1 1 0 1
Q 1 0 0 1 0 Q=1

S Q
1 1

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SR Latch:
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
R 0
Q=0
1 0 1 1 0 1
Q 1 0 0 1 0 Q=1
1 0 1 1 0 Q=1

S Q
1 0

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SR Latch:
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
R 1
Q=0
0 0 1 1 0 1
Q 1 0 0 1 0
Q=1
1 0 1 1 0
1 1 0 0 0 Q = Q’

S Q
1 10

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SR Latch:

S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 0 1 1 0
R Q 0 1 0 0 1
Q=0
0 1 1 0 1
1 0 0 1 0
Q=1
1 0 1 1 0

S Q 1 1 0 0 0 Q = Q’
0 1 1 1 0 0

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 SR Latch with NAND gate

• SR latch with NAND gates requires a 0 signal to change its state.

• The inputs signals for the NAND-latch are the complement
values used for the NOR latch.
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 SR Latch with control input
• The operation of the basic SR latch can be modified by providing an additional
input signal that determines (controls) when the state of the latch can be
changed by determining whether S and R(or S’ and R’) can affect the circuit.
• An SR latch with a control input is shown in below Figure. It consists of the
basic SR latch and two additional NAND gates. The control input En acts as an
enable signal for the other two inputs. The outputs of the NAND gates stay at
the logic-1 level as long as the enable signal remains at 0.

S* = S’ + En’ & R* = R’ + En’

If En = 1, then S* = S’ & R* = R’
If En = 0, then S* = 1 & R* = 1 =
memory= No change
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D Latch:

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Symbols for Latches

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Storage Elements: Flip-flop

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SR Flip-flop

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Triggering Method

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Example

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Tables of SR flip-flop

Qn+1 = S + QnR’

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Edge Triggered D flip-flop

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D Flip flop

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Latches versus flip-flops

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Waveform of D flip-flop

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Master-Slave D Latch

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Master-Slave D Latch (waveform)

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J-K Flip-flop

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J-K Flip-flop

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J-K Flip-flop Characteristic Equations

J K Q(t) Q(t+1)
0 0 0 0 No change
0 0 1 1
J Q 0 1 0 Reset
0 1 1
K Q 1 0 0 Set
1 0 1
1 1 0 Toggle
1 1 1

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J-K Flip-flop Characteristic Equations

J K Q(t) Q(t+1)
0 0 0 0
0 0 1 1 No change
J Q
0 1 0 0
0 1 1 0 Reset
K Q 1 0 0
1 0 1 Set
1 1 0
1 1 1 Toggle

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J-K Flip-flop Characteristic Equations

J K Q(t) Q(t+1)
0 0 0 0 No change
0 0 1 1
J Q
0 1 0 0 Reset
0 1 1 0
K Q 1 0 0 1 Set
1 0 1 1
1 1 0 Toggle
1 1 1

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J-K Flip-flop Characteristic Equations

J K Q(t) Q(t+1)
0 0 0 0
No change
0 0 1 1
J Q
0 1 0 0
Reset
0 1 1 0
K Q 1 0 0 1
Set
1 0 1 1
1 1 0 1
Toggle
1 1 1 0

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J-K Flip-flop Characteristic Equations

J K Q(t) Q(t+1)
0 0 0 0
0 0 1 1 K
J Q
0 1 0 0 0 1 0 0
0 1 1 0 J 1 1 0 1
K Q 1 0 0 1 Q
1 0 1 1
1 1 0 1
1 1 1 0

Q(t+1) = JQ’ + K’Q

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 T- Flip-flop

T Q(t+1)
Q(t+1) = JQ’ + K’Q
0 Q(t)
= TQ’ + T’Q = T⊕Q
1 Q’(t)

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Flip-Flop Truth Tables and Equations
D Q(t+1)
D Q
0 0 Reset
Q(t+1) = D
Q 1 1 Set

J K Q(t+1)
J Q 0 0 Q(t) No change
0 1 0 Reset Q(t+1) = JQ’ + K’Q
K Q 1 0 1 Set
1 1 Q’(t) Toggle

T Q T Q(t+1)
0 Q(t) No change Q(t+1) = T  Q
Q 1 Q’(t) Toggle 38
Flip-Flop Excitation Table

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Flip-Flops with Direct Inputs

Asynchronous Reset
R D CLK Q(t+1)
0 x x 0

Active low asynchronous reset

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Flip-Flops with Direct Inputs

Asynchronous Reset
R D CLK Q(t+1)
0 x x 0
1 0 ↑ 0
1 1 ↑ 1

Active low asynchronous reset

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Flip-Flops with Direct Inputs
Asynchronous Preset and Clear

PR CLR D CLK Q(t+1)

1 0 x x 0

Active low asynchronous preset and clear

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Flip-Flops with Direct Inputs

Asynchronous Preset and Clear

PR CLR D CLK Q(t+1)
1 0 x x 0
0 1 x x 1

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Flip-Flops with Direct Inputs

Asynchronous Preset and Clear

PR CLR D CLK Q(t+1)
1 0 x x 0
0 1 x x 1
1 1 0 ↑ 0
1 1 1 ↑ 1

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Terminology

45
 Analysis
of
Clocked Sequential
Circuit
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 Analysis of clocked sequential circuit

Analysis Procedure:

1. Determine the flip-flop input equations in terms of

present state and input variable.

2. Substitute the input equations into the flip-flop

characteristic equation to obtain the state equation.

3. Use the corresponding state equations to determine the

state table.

4. Use state table to draw the state diagram.

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 Example
Problem: Drive the state table and state diagram of the sequential
circuit given below:

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Example (Continued)

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 Example
Problem: Drive the state table and state diagram of the sequential circuit
given below:

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 Example (Using J-K Flip-flop)
Problem: Drive the state table and state diagram of the sequential circuit
given below:

Solution:
Step:

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Example (Continued)

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 Example (Using T Flip-flop)
Problem: Drive the state table and state diagram of the sequential
circuit given below:
x A
T Q y

R Q

T Q
B

R Q

Solution: CLK Reset

Step 1:
TA = B x TB = x
y =AB
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 Example
Step 2: A(t+1) = TA Q’A + T’A QA
= AB’ + Ax’ + A’Bx
B(t+1) = TB Q’B + T’B QB
=xB
Step 3:
Step 4:

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 Design
of
Sequential Circuit

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Design Procedure for sequential circuit

 The word description of the circuit behavior to get a state

diagram;

 Assign binary values to the states;

 Obtain the state table;

 Choose the type of flip-flops;

 Derive the simplified flip-flop input equations and output

equations;

 Draw the logic diagram;

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 Example
Problem: Design a Sequential circuit using D flip-flops for a system which
has the following state diagram.
Da Db X DA DB y
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 1
0 1 1 1 1 0
1 0 0 0 0 1
1 0 1 1 0 0
1 1 0 0 0 1
1 1 1 1 0 0

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 Example (Continued)

Use k map to find the value of DA,

DB and Y.

DA = AX+ BX
DB = A’X
Y = (A + B) X’

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60
 Problem
Problem: For the given state diagram, determine the state transitions and output
sequence that will be generated when an input sequence of 110111001 is applied
to the circuit and it is initially in the state 00.

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 Design of Clocked Sequential Circuits

Example: Design a Sequential circuit using D flip-flops for a system

which has the following state diagram.

0/0 1/0
S0 S1
0/0 State A B
S0 0 0
0/1 1/0
0/0 S1 0 1
S2 1 0
S3 S2 S3 1 1
1/0
1/1
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 Example (Continued)

Present Next
Input Output
State State
A B x A B y
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 0
0 1 1 1 0 0
1 0 0 0 0 0
1 0 1 1 1 0
1 1 0 0 0 1
1 1 1 1 1 1
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 Example (Continued)

Present Inpu Next A(t+1) = DA (A, B, x)

Output FF Input
State t State = ∑ (3, 5, 7)
A B x A B y DA DB B(t+1) = DB (A, B, x)
0 0 0 0 0 0 0 0 = ∑ (1, 5, 7)
0 0 1 0 1 0 0 1 y (A, B, x) = ∑ (6, 7)
0 1 0 0 0 0 0 0
Using K-map we get:
0 1 1 1 0 0 1 0
1 0 0 0 0 0 0 0 DA (A, B, x) = ∑ (3, 5, 7)
1 0 1 1 1 0 1 1 = Ax+B x
1 1 0 0 0 1 0 0 DB (A, B, x) = ∑ (1, 5, 7)
1 1 1 1 1 1 1 1 = A x + B’ x
y (A, B, x) = ∑ (6, 7)
=AB
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 Example (Continued)

DA = A x + B x
DB = A x + B’ x
y =AB

x D Q A

Q
y

D Q B

CLK Q

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Flip-Flop Excitation Tables

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Example: Design a Sequential circuit using J-K flip-flops for a system
which has the following state diagram.

y (A, B, x) = ∑ (6, 7) 67
Example (Continued)

y (A, B, x) = ∑ (6, 7)
= AB

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69
Design a Sequential circuit using T flip-flops for a system which has the
following state diagram.

y (A, B, x) = ∑ (6, 7)

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70
Design a Sequential circuit using T flip-flops for a system which
has the following state diagram.

y (A, B, x) = ∑ (6, 7)
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=AB
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Example-1: Draw a state diagram for

11011 Sequence recognizer

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Draw a state diagram for 11011 Sequence

recognizer (Overlap case)

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Draw a state diagram for 11011 Sequence

recognizer (Overlap case)

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Design a 11011 Sequence recognizer

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Explanation (Continued…)

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Explanation (Continued…)

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Example-2: Draw a state diagram for

1001 Sequence recognizer
• What happens if we’re in state D (the last three inputs were 100), and
the current input is 1?
– The output should be a 1, because we’ve found the desired pattern
– But this last 1 could also be the start of another occurrence of the pattern! For
example, 1001001 contains two occurrences of 1001
– To detect overlapping occurrences of the pattern, the next state
should be B.
1/0 0/0 0/0
A B C D
1/1
State Meaning
A None of the desired pattern (1001) has been input yet.
B We’ve already seen the first bit (1) of the desired pattern.
C We’ve already seen the first two bits (10) of the desired pattern.
D We’ve already seen the first three bits (100) of the desired pattern.
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Filling in the other arrows

• Two outgoing arrows for each node, to account for the possibilities of
X=0 and X=1

• The remaining arrows we need are shown in blue. They also allow for
the correct detection of overlapping occurrences of 1001.
0/0
1/0
1/0 0/0 0/0
A B C D
1/0
0/0 1/1
State Meaning
A None of the desired pattern (1001) has been input yet.
B We’ve already seen the first bit (1) of the desired pattern.
C We’ve already seen the first two bits (10) of the desired pattern. 78
D We’ve already seen the first three bits (100) of the desired pattern.
 Example-3: Sequence Detector

• 101 sequence Detector

X = 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0

Z = 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0

(time: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15)
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 Design of 101 Sequence Detector

• State Diagram:

1/0

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 Design of 101 Sequence Detector

• State Diagram (final):

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Assignment#5

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