Chapter 10

10.1. LIBRARY ieee ;

USE ieee.std logic 1164.all ;

ENTITY prob10 1 IS
GENERIC ( modulus : INTEGER := 8 ) ;
PORT ( Resetn : IN STD LOGIC ;
Clock, E, L : IN STD LOGIC ;
R : IN INTEGER RANGE 0 TO modulus,1 ;
Q : OUT INTEGER RANGE 0 TO modulus,1 ) ;
END prob10 1 ;

ARCHITECTURE Behavior OF prob10 1 IS

SIGNAL Count : INTEGER RANGE 0 TO modulus,1 ;
BEGIN
PROCESS ( Resetn, Clock )
BEGIN
IF Resetn = ’0’ THEN
Count <= 0 ;
ELSIF (Clock’EVENT AND Clock = ’1’) THEN
IF E = ’1’ THEN
IF L = ’1’ THEN
Count <= R ;
ELSE
Count <= Count+1 ;
END IF ;
END IF ;
END IF ;
END PROCESS ;
Q <= Count ;
END Behavior ;

10.2. (a) A modified ASM chart that has only Moore-type outputs in state S2 is given below.

10-1
 Reset

S1
Load A
B←0

0
0 1
s s

1
S2 S4
Shift A Done

S3
Shift A 1
A = 0?
B←B+1

0
a0

(b) Reset

S1
EA LB, EB

0 0
1 0 1
LA s s

1
S2 S4
EA Done = 1

S3
1
EA, EB z

0
a0

10-2
(c) LIBRARY ieee ;
USE ieee.std logic 1164.all ;
USE work.components.shiftrne ;

ENTITY prob10 2 IS
PORT ( Clock, Resetn : IN STD LOGIC ;
LA, s : IN STD LOGIC ;
Data : IN STD LOGIC VECTOR(7 DOWNTO 0) ;
B : BUFFER INTEGER RANGE 0 to 8 ;
Done : OUT STD LOGIC ) ;
END prob10 2 ;

ARCHITECTURE Behavior OF prob10 2 IS

TYPE STATE TYPE IS ( S1, S2, S3, S4 ) ;
SIGNAL y : STATE TYPE ;
SIGNAL A : STD LOGIC VECTOR(7 DOWNTO 0) ;
SIGNAL z, EA, LB, EB, low : STD LOGIC ;
BEGIN
FSM transitions: PROCESS ( Resetn, Clock )
BEGIN
IF Resetn = ’0’ THEN
y <= S1 ;
ELSIF (Clock’EVENT AND Clock=’1’) THEN
CASE y IS
WHEN S1 =>
IF s = ’0’ THEN y <= S1 ; ELSE y <= S2 ; END IF ;
WHEN S2 j S3 =>
IF z =’0’ THEN
IF A(0) = ’0’ THEN y <= S2 ;
ELSE y <= S3 ;
END IF ;
ELSE
y <= S4 ;
END IF ;
WHEN S4 =>
IF s = ’1’ THEN y <= S4 ; ELSE y <= S1 ; END IF ;
END CASE ;
END IF ;
END PROCESS ;
FSM outputs: PROCESS ( y, s, LA )
BEGIN
EA <= ’0’ ; LB <= ’0’ ; EB <= ’0’ ; Done <= ’0’ ;
CASE y IS
WHEN S1 =>
LB <= ’1’ ; EB <= ’1’ ;
IF s = ’0’ AND LA = ’1’ THEN EA <= ’1’ ; ELSE EA <= ’0’ ; END IF ;
WHEN S2 =>
EA <= ’1’ ;

: : : con’t

10-3
 WHEN S3 =>
EA <= ’1’ ; EB <= ’1’ ;
WHEN S4 =>
Done <= ’1’ ;
END CASE ;
END PROCESS ;
- - The datapath circuit is described below
upcount: PROCESS ( Resetn, Clock )
BEGIN
IF Resetn = ’0’ THEN
B <= 0 ;
ELSIF (Clock’EVENT AND Clock = ’1’) THEN
IF EB = ’1’ THEN
IF LB = ’1’ THEN B <= 0 ;
ELSE B <= B + 1 ;
END IF ;
END IF ;
END IF ;
END PROCESS ;
low <= ’0’ ;
ShiftA: shiftrne GENERIC MAP ( N => 8 ) PORT MAP ( Data, LA, EA, low, Clock, A ) ;
z <= ’1’ WHEN A = ”00000000” ELSE ’0’ ;
END Behavior ;

10.3. (a) Reset

S1

Load A P ← 0, C ← 0
Load B

0
0 1
s s

S2 S3

Shift left A, C ← C + 1 Done

1
P←P+A C = n – 1?

0
bC

10-4
 (b)

LA 0 DataA DataB LC 0

L EB L
E
EA E Shift-left Register EC E .
Counter

A B C

Clock
2n

n log2n
+

n-to-1
Sum
0
2n 2n bC
Psel
2n
z
DataP

EP E
register

2n

(c) The ASM chart for the control circuit is shown below. Note that we assume the EB signal is controlled
by external logic.

10-5
 Reset

S1

Psel = 0, EP, LC, EC

0 0
LA s

1 1

EA 0
1
s

S2 S3

Psel = 1, EA, EC Done

1
EP z

0
bC

(d) LIBRARY ieee ;

USE ieee.std logic 1164.all ;
USE ieee.std logic unsigned.all ;
USE work.components.all ;

ENTITY prob10 3 IS
GENERIC ( N : INTEGER := 8 ; NN : INTEGER := 16 ) ;
PORT ( Clock : IN STD LOGIC ;
Resetn : IN STD LOGIC ;
LA, LB, s : IN STD LOGIC ;
DataA : IN STD LOGIC VECTOR(N,1 DOWNTO 0) ;
DataB : IN STD LOGIC VECTOR(N,1 DOWNTO 0) ;
P : BUFFER STD LOGIC VECTOR(NN,1 DOWNTO 0) ;
Done : OUT STD LOGIC ) ;
END prob10 3 ;

: : : con’t

10-6
ARCHITECTURE Behavior OF prob10 3 IS
TYPE State type IS ( S1, S2, S3 ) ;
SIGNAL y : State type ;
SIGNAL Psel, EA, EP, Zero : STD LOGIC ;
SIGNAL B, N Zeros : STD LOGIC VECTOR(N,1 DOWNTO 0) ;
SIGNAL A, Ain, DataP, Sum : STD LOGIC VECTOR(NN,1 DOWNTO 0) ;
SIGNAL ZeroI, C : INTEGER RANGE 0 TO N,1 ;
SIGNAL EC, LC, Bc, z : STD LOGIC ;
BEGIN
FSM transitions: PROCESS ( Resetn, Clock )
BEGIN
IF Resetn = ’0’ THEN
y <= S1 ;
ELSIF (Clock’EVENT AND Clock=’1’) THEN
CASE y IS
WHEN S1 =>
IF s = ’0’ THEN y <= S1 ; ELSE y <= S2 ; END IF ;
WHEN S2 =>
IF z =’0’ THEN y <= S2 ; ELSE y <= S3 ; END IF ;
WHEN S3 =>
IF s = ’1’ THEN y <= S3 ; ELSE y <= S1 ; END IF ;
END CASE ;
END IF ;
END PROCESS ;
FSM outputs: PROCESS ( y, s, LA, Bc )
BEGIN
EP <= ’0’ ; EA <= ’0’ ; Done <= ’0’ ; Psel <= ’0’ ;
EC <= ’0’ ; LC <= ’0’ ;
CASE y IS
WHEN S1 =>
EP <= ’1’ ; EC <= ’1’ ; LC <= ’1’ ;
IF s = ’0’ AND LA = ’1’ THEN EA <= ’1’ ; ELSE EA <=’0’ ; END IF ;
WHEN S2 =>
Psel <= ’1’ ; EA <= ’1’ ; EC <= ’1’ ;
IF Bc = ’1’ THEN EP <= ’1’ ; ELSE EP <= ’0’ ; END IF ;
WHEN S3 =>
Done <= ’1’ ;
END CASE ;
END PROCESS ;
- - datapath
Zero <= ’0’ ;
N Zeros <= (OTHERS => ’0’) ;
Ain <= N Zeros & DataA ;

ShiftA: shiftlne GENERIC MAP ( N => NN )

PORT MAP ( Ain, LA, EA, Zero, Clock, A ) ;
RegB: regne GENERIC MAP ( N => N )
PORT MAP ( DataB, Resetn, LB, Clock, B ) ;

: : : con’t

10-7
 Sum <= A + P ;
DataP <= Sum WHEN Psel=’1’ ELSE (OTHERS => ’0’) ;
RegP: regne GENERIC MAP ( N => NN )
PORT MAP ( DataP, Resetn, EP, Clock, P ) ;
ZeroI <= 0 ;
- - Multiplexer to Select bit C from B
Bc <= B(C) ;
upcounter: prob10 1
GENERIC MAP ( modulus => N )
PORT MAP ( Resetn, Clock, EC, LC, ZeroI, C ) ;
- - check if we have gone through all n bits of B
z <= ’1’ WHEN (C = (N,1)) ELSE ’0’ ;
END Behavior ;

10.4. LIBRARY ieee ;

USE ieee.std logic 1164.all ;
USE ieee.std logic unsigned.all ;
USE work.components.all ;

ENTITY prob10 4 IS
GENERIC ( N : INTEGER := 8 ) ;
PORT ( Clock, Resetn : IN STD LOGIC ;
DataA, DataB : IN STD LOGIC VECTOR(N,1 DOWNTO 0) ;
LA, EB, s : IN STD LOGIC ;
Q, R : OUT STD LOGIC VECTOR(N,1 DOWNTO 0) ;
Done : OUT STD LOGIC ) ;
END prob10 4 ;

ARCHITECTURE Behavior OF prob10 4 IS

TYPE State type IS (S1, S2, S3, S4 ) ;
SIGNAL y : State type ;
SIGNAL EC, LC, ER, LR, EA, EQ, LQ, Rsel, low, Cout, z : STD LOGIC ;
SIGNAL RminusB, AR, Rmux : STD LOGIC VECTOR(N,1 DOWNTO 0) ;
SIGNAL BR, RR, QR, Zero : STD LOGIC VECTOR(N,1 DOWNTO 0) ;
SIGNAL RminusBwCarry : STD LOGIC VECTOR(N DOWNTO 0) ;
SIGNAL CR : INTEGER RANGE 0 TO N,1 ;
BEGIN
FSM transitions: PROCESS ( Resetn, Clock )
BEGIN
IF Resetn = ’0’ THEN
y <= S1 ;
ELSIF (Clock’EVENT AND Clock=’1’) THEN
CASE y IS
WHEN S1 =>
IF s = ’0’ THEN y <= S1 ; ELSE y <= S2 ; END IF ;
WHEN S2 =>
y <= S3 ;

: : : con’t

10-8
 WHEN S3 =>
IF z = ’1’ THEN y <= S4 ; ELSE y <= S2 ; END IF ;
WHEN S4 =>
IF s = ’1’ THEN y <= S4 ; ELSE y <= S1 ; END IF ;
END CASE ;
END IF ;
END PROCESS ;
FSM outputs: PROCESS ( y, s, Cout, z, LA )
BEGIN
Rsel <= ’0’ ; LR <= ’0’; ER <= ’0’; LC <= ’0’; EC <= ’0’;
EA <= ’0’ ; EQ <= ’0’; Done <= ’0’;
CASE y IS
WHEN S1 =>
LR <= ’1’ ; ER <= ’1’; LC <= ’1’; EC <= ’1’;
IF s = ’0’ AND LA=’1’ THEN EA <=’1’ ; ELSE EA <= ’0’; END IF ;
WHEN S2 =>
ER <= ’1’ ; EA <= ’1’;
WHEN S3 =>
EQ <= ’1’ ; Rsel <= ’1’; EC <= ’1’;
IF Cout = ’1’ THEN ER <= ’1’ ; LR <= ’1’; ELSE LR <= ’0’; ER <= ’0’; END IF ;
WHEN S4 =>
Done <= ’1’ ;
END CASE ;
END PROCESS ;
SHLR: shiftlne GENERIC MAP ( N => N )
PORT MAP ( Rmux, LR, ER, AR(N,1), Clock, RR ) ;
low <= ’0’ ;
SHLA: shiftlne GENERIC MAP ( N => N )
PORT MAP ( DataA, LA, EA, low, Clock, AR ) ;
LQ <= ’0’ ;
Zero <= (OTHERS => ’0’) ;
SHLQ: shiftlne GENERIC MAP ( N => N )
PORT MAP ( Zero, LQ, EQ, Cout, Clock, QR ) ;
REGB: regne GENERIC MAP ( N => N )
PORT MAP ( DataB, Resetn, EB, Clock, BR ) ;
RminusBwCarry <= (”0” & RR) + (”0” & (NOT BR)) + 1 ;
RminusB <= RminusBwCarry(N,1 DOWNTO 0) ;
Cout <= RminusBwCarry(N) ;
Rmux <= RminusB WHEN Rsel=’1’ ELSE Zero ;
- - downcnt component can be used instead
CNT C: PROCESS
BEGIN
WAIT UNTIL Clock’EVENT AND Clock=’1’ ;
IF EC=’1’ THEN
IF LC=’1’ THEN CR <= N,1 ; ELSE CR <= CR,1 ; END IF ;
END IF ;
END PROCESS ;
z <= ’1’ WHEN CR=0 ELSE ’0’ ;
R <= RR ;
Q <= QR ;
END Behavior ;

10-9
10.5. (a) Reset

S1

Q←0
Load A
Load B
0
0 1
s s

1
S3

Done

S2

R←R–B 1 0
Q←Q+1 R – B ≥ 0?

(b)

R sel A LoadB B

1 0 E

ER
E
LoadA

LQ 0
R n

L
C out Ci 1 EQ E Counter
+

R–B
C out
n Q

Clock

10-10
(c) Reset

S1

LQ, EQ, Rsel = 0

0
0 1
s s

1
S3
Done

S2
Rsel = 1

EQ 1 0
C out
ER

(d) LIBRARY ieee ;

USE ieee.std logic 1164.all ;
USE ieee.std logic unsigned.all ;
USE work.components.all ;

ENTITY prob10 5 IS
GENERIC ( N : INTEGER := 8 ; P2N : INTEGER := 256 ) ;
PORT ( Clock, Resetn, s: IN STD LOGIC ;
LoadA, LoadB : IN STD LOGIC ;
DataA, DataB : IN STD LOGIC VECTOR(N,1 DOWNTO 0) ;
Q : OUT INTEGER RANGE 0 TO P2N,1 ;
R : BUFFER STD LOGIC VECTOR(N,1 DOWNTO 0) ;
Done : OUT STD LOGIC );
END prob10 5 ;

ARCHITECTURE Behavior OF prob10 5 IS

TYPE State type IS ( S1, S2, S3 ) ;
Signal y : State type ;
SIGNAL Rsel, ER, ERint, LQ, EQ : STD LOGIC ;
SIGNAL Rmux, RminusB, B : STD LOGIC VECTOR(N,1 DOWNTO 0) ;
SIGNAL RminusBwCarry : STD LOGIC VECTOR(N DOWNTO 0) ;
SIGNAL Zero : INTEGER RANGE 0 TO P2N,1 ;
SIGNAL Cout : STD LOGIC ;
BEGIN

: : : con’t

10-11
 FSM transitions: PROCESS ( Resetn, Clock )
BEGIN
IF Resetn = ’0’ THEN
y <= S1 ;
ELSIF (Clock’EVENT AND Clock=’1’) THEN
CASE y IS
WHEN S1 =>
IF s = ’0’ THEN y <= S1 ; ELSE y <= S2 ; END IF ;
WHEN S2 =>
IF Cout =’1’ THEN y <= S2 ; ELSE y <= S3 ; END IF ;
WHEN S3 =>
IF s = ’1’ THEN y <= S3 ; ELSE y <= S1 ; END IF ;
END CASE ;
END IF ;
END PROCESS ;
FSM outputs: PROCESS ( y, Cout )
BEGIN
EQ <= ’0’; LQ <= ’0’; ER <= ’0’; Rsel <= ’0’; Done <= ’0’;
CASE y IS
WHEN S1 =>
LQ <= ’1’; EQ <= ’1’;
WHEN S2 =>
Rsel <= ’1’;
If Cout=’1’ THEN EQ <= ’1’; ER <= ’1’; ELSE EQ <= ’0’; ER <=’0’; END IF ;
WHEN S3 =>
Done <= ’1’;
END CASE ;
END PROCESS ;
- - Data Path Definition
Rmux <= DataA WHEN Rsel=’0’ ELSE RminusB ;
ERint <= ER OR LoadA ;
RegR: regne GENERIC MAP ( N => N )
PORT MAP ( Rmux, Resetn, ERint, Clock, R ) ;
RegB: regne GENERIC MAP ( N => N )
PORT MAP ( DataB, Resetn, LoadB, Clock, B ) ;
Zero <= 0 ;
CntQ: prob10 1 GENERIC MAP ( modulus=> P2N )
PORT MAP ( Resetn, Clock, EQ, LQ, Zero, Q ) ;
RminusBwCarry <= ( ”0” & R ) + ( ”0” & ( NOT B ) ) + 1 ;
RminusB <= RminusBwCarry( N,1 DOWNTO 0 ) ;
Cout <= RminusBwCarry( N ) ;
END Behavior ;

(e) This implementation of a divider is less efficient in the worst case when compared to the other implemen-
tations shown. The efficient algorithms presented are able to perform division in n cycles for n-bit inputs.
However, the method of repeated subtraction takes 2n cycles for the worst case, which is when dividing by
1. On the other hand, if the two numbers A and B are close in size, then repeated subtraction is an efficient
approach.

10-12
10.6. State S3 is responsible for loading the operands into the divider, while state S4 starts the division operation.
These states can be combined into a single state. We can use the z flag to indicate the first time that we’ve
entered the new combined state. When z = 1 a mealy output is produced which loads the operands and
decrements the counter. Thus, the z flag changes to a 0. The combined state now produces a mealy output
which starts the division, on the condition that z = 0. This control circuit ASM chart is shown below.

Reset

S1

EC, LC, Ssel = 0, ES

0
s

S2

EC Ssel = 1, ES

0
z

1
S3

0
1
LA, EB, EC z s
1
0
S4
Div Div, Done

0 1
zz

10.7. LIBRARY ieee ;

USE ieee.std logic 1164.all ;

ENTITY prob10 7 IS
PORT ( Clock, Resetn, s, z, zz : IN STD LOGIC ;
EC, LC, Ssel, ES, LA, EB, Div, Done : OUT STD LOGIC ) ;
END prob10 7 ;

: : : con’t

10-13
 ARCHITECTURE Behavior OF prob10 7 IS
TYPE STATE TYPE IS (S1, S2, S3, S4) ;
SIGNAL y : STATE TYPE ;
BEGIN
FSM transitions: PROCESS ( Resetn, Clock, s, z, zz )
BEGIN
IF Resetn = ’0’ THEN
y <= S1 ;
ELSIF (Clock’EVENT AND Clock=’1’) THEN
CASE y IS
WHEN S1 =>
IF s = ’0’ THEN y <= S1 ; ELSE y <= S2 ; END IF ;
WHEN S2 =>
IF z =’0’ THEN y <= S2 ; ELSE y <= S3 ; END IF ;
WHEN S3 =>
IF z = ’1’ THEN
y <= S3 ;
ELSE
IF zz = ’0’ THEN y <= S3 ; ELSE y <= S4 ; END IF ;
END IF ;
WHEN S4 =>
IF s = ’1’ THEN y <= S4 ; ELSE y <= S1 ; END IF ;
END CASE ;
END IF ;
END PROCESS ;
FSM outputs: PROCESS ( y, z )
BEGIN
LA <= ’0’ ; EB <= ’0’; EC <= ’0’; LC <= ’0’;
ES <= ’0’ ; Ssel <= ’0’; Div <= ’0’; Done <= ’0’;
CASE y IS
WHEN S1 =>
EC <= ’1’ ; LC <= ’1’; ES <= ’1’;
WHEN S2 =>
ES <= ’1’ ; Ssel <= ’1’;
IF z = ’0’ THEN EC <= ’1’ ; ELSE EC <= ’0’; END IF ;
WHEN S3 =>
IF z = ’0’ THEN Div <= ’1’ ; LA <= ’0’; EB <= ’0’; EC <= ’0’;
ELSE Div <= ’0’ ; LA <= ’1’; EB <= ’1’; EC <= ’1’;
END IF ;
WHEN S4 =>
Div <= ’1’ ; Done <= ’1’;
END CASE ;
END PROCESS ;
END Behavior ;

10.8. The states S 2 and S 3 can be merged into a single state by performing the assignment Cj = Ci + 1. The
circuit would require an adder to increment Ci by 1 and the outputs of this adder would be loaded in parallel
into the counter Cj . If instead of using counters to implement Ci and Cj we used shift registers, then the
effect of producing Ci + 1 could be efficiently implemented by wiring Ci to the parallel-load data inputs on
Cj such that the bits are shifted by one position.

10-14
10.9. (a) The part of the datapath circuit that needs to be modified is shown below. The rest of the datapath is the
same as the circuit shown in Figure 10.37.

1000

4 4

LI L LJ L
EI E Shift-left EJ E Shift-left

Ci Cj
Clock
C i ( k – 2 ) ⇒ zi
C j(k – 1) ⇒ z j

0 1 Csel
ExtAdd
decoder

2
2-to-4

RAdd 4 Cmux
4
0 1 Int

encoder
Rout [0-3] 4 4 2

4-to-2
Imux
Rout 0
WrInit Rin 0
Wr Rout 1
Rin 1
Rout 2
Rin 2
Rout 3
Rin 3

(b) LIBRARY ieee ;

USE ieee.std logic 1164.all ;
USE ieee.std logic unsigned.all ;
USE work.components.all ;

ENTITY prob10 9 IS
GENERIC ( N : INTEGER := 4 ) ;
PORT ( Clock, Resetn : IN STD LOGIC ;
s, WrInit, Rd : IN STD LOGIC ;
DataIn : IN STD LOGIC VECTOR(N,1 DOWNTO 0) ;
RAdd : IN INTEGER RANGE 0 TO 3 ;
DataOut : BUFFER STD LOGIC VECTOR(N,1 DOWNTO 0) ;
Done : BUFFER STD LOGIC ) ;
END prob10 9 ;

: : : con’t

10-15
ARCHITECTURE Behavior OF prob10 9 IS
TYPE STATE TYPE IS ( S1, S2, S3, S4, S5, S6, S7, S8, S9 ) ;
SIGNAL y : STATE TYPE ;
SIGNAL Rin : STD LOGIC VECTOR(0 TO 3) ; - - reg write controls
TYPE RegArray IS ARRAY(0 TO 3) OF STD LOGIC VECTOR(N,1 DOWNTO 0) ;
SIGNAL R : RegArray ; - - reg outputs
SIGNAL RData, ABMux : STD LOGIC VECTOR(N,1 DOWNTO 0) ; - - reg inputs
SIGNAL Int, Csel, Wr, BltA : STD LOGIC ;
- - SIGNAL CMux, IMux : INTEGER RANGE 0 TO 3 ;
SIGNAL Ain, Bin, Aout, Bout : STD LOGIC ;
SIGNAL LI, LJ, EI, EJ, zi, zj : STD LOGIC ;
SIGNAL A, B, ABData : STD LOGIC VECTOR(N,1 DOWNTO 0) ;
- - Redefined Signals
SIGNAL Ci, Cj, Cmux : STD LOGIC VECTOR(0 TO 3);
- - New Signals
SIGNAL low : STD LOGIC ;
SIGNAL Rout : STD LOGIC VECTOR(0 TO 3);
SIGNAL Addr0 : STD LOGIC VECTOR(0 TO 3); - - Parallel Load for Ci
SIGNAL ExtAdd : STD LOGIC VECTOR(0 TO 3);
BEGIN
FSM transitions: PROCESS ( Resetn, Clock )
BEGIN
IF Resetn = ’0’ THEN
y <= S1 ;
ELSIF (Clock’EVENT AND Clock = ’1’) THEN
CASE y IS
WHEN S1 => IF S = ’0’ THEN y <= S1 ; ELSE y <= S2 ; END IF ;
WHEN S2 => y <= S3 ;
WHEN S3 => y <= S4 ;
WHEN S4 => y <= S5 ;
WHEN S5 => IF BltA = ’1’ THEN y <= S6 ; ELSE y <= S8 ; END IF ;
WHEN S6 => y <= S7 ;
WHEN S7 => y <= S8 ;
WHEN S8 =>
IF zj = ’0’ THEN y <= S4 ;
ELSIF zi = ’0’ THEN y <= S2 ;
ELSE y <= S9 ;
END IF ;
WHEN S9 => IF s = ’1’ THEN y <= S9 ; ELSE y <= S1 ; END IF ;
END CASE ;
END IF ;
END PROCESS ;

Int <= ’0’ WHEN y = S1 ELSE ’1’ ;

Done <= ’1’ WHEN y = S9 ELSE ’0’ ;
FSM outputs: PROCESS ( y, zi, zj )
BEGIN
LI <= ’0’ ; LJ <= ’0’ ; EI <= ’0’ ; EJ <= ’0’ ; Csel <= ’0’ ; Wr <= ’0’;
Ain <= ’0’ ; Bin <= ’0’ ; Aout <= ’0’ ; Bout <= ’0’ ;
: : : con’t

10-16
 CASE y IS
WHEN S1 => LI <= ’1’ ; EI <= ’1’ ;
WHEN S2 => Ain <= ’1’ ; LJ <= ’1’ ; EJ <= ’1’ ;
WHEN S3 => EJ <= ’1’ ;
WHEN S4 => Bin <= ’1’ ; Csel <= ’1’ ;
WHEN S5 => - - no outputs asserted in this state
WHEN S6 => Csel <= ’1’ ; Wr <= ’1’ ; Aout <= ’1’ ;
WHEN S7 => Wr <= ’1’ ; Bout <= ’1’ ;
WHEN S8 => Ain <= ’1’ ;
IF zj = ’0’ THEN EJ <= ’1’ ;
ELSE EJ <= ’0’ ;
IF zi = ’0’ THEN EI <= ’1’ ;
ELSE EI <= ’0’ ;
END IF ;
END IF ;
WHEN S9 => - - Done is assigned 1 by conditional signal assignment
END CASE ;
END PROCESS ;
- - define the datapath circuit
GenReg: FOR i IN 0 TO 3 GENERATE
Reg: regne GENERIC MAP ( N => N )
PORT MAP ( RData, Resetn, Rin(i), Clock, R(i) );
END GENERATE ;
RegA: regne GENERIC MAP ( N => N )
PORT MAP ( ABData, Resetn, Ain, Clock, A );
RegB: regne GENERIC MAP ( N => N )
PORT MAP ( ABData, Resetn, Bin, Clock, B );
BltA <= ’1’ WHEN B < A ELSE ’0’;
ABMux <= A WHEN Bout=’0’ ELSE B ;
RData <= ABMux WHEN WrInit=’0’ ELSE DataIn ;
Addr0 <= ”1000”; low <= ’0’;
OuterLoop: shiftrne GENERIC MAP ( N => 4 )
PORT MAP ( Addr0, LI, EI, low, Clock, Ci );
InnerLoop: shiftrne GENERIC MAP ( N => 4 )
PORT MAP ( Ci, LJ, EJ, low, Clock, Cj );
CMux <= Ci WHEN Csel= ’0’ ELSE Cj ;
Rout <= Cmux WHEN Int=’1’ ELSE ExtAdd ;
- - Note that the 4-to-2 encoder that drives IMux is implicitly implemented below
WITH Rout SELECT
ABData <= R(0) WHEN ”1000”,
R(1) WHEN ”0100”,
R(2) WHEN ”0010”,
R(3) WHEN OTHERS ;
Rin <= Rout WHEN (WrInit OR Wr) = ’1’ ELSE ”0000”;
zi <= Ci(2); zj <= Cj(3);
DataOut <= (OTHERS => ’Z’) WHEN Rd = ’0’ ELSE ABData ;
WITH Radd SELECT - - 2-to-4 decoder
ExtAdd <= ”1000” WHEN 0,
”0100” WHEN 1,
”0010” WHEN 2,
”0001” WHEN OTHERS ;
END Behavior ;

10-17
 (c) The major drawback of using shift-registers instead of counters is that the number of flip-flops is in-
creased. Each counter uses log2 n flip-flops while each shift register contains n flip-flops. However, the
shift-register requires no combinational logic to perform tests such as whether the count value k , 2 has been
reached — in the shift register we directly access bit k , 2 of the register to perform this test. It should also
be possible to clock the datapath at a higher maximum clock frequency when using shift-registers, because
they are simpler than counters.

10.11. The VHDL code below shows the changes needed in the datapath so that an SRAM block can be used instead
of registers. The SRAM block is clocked on the negative edge of the Clock signal, hence changes in the
outputs produced by the other datapath elements must be stable before the negative edge; the clock period
must be long enough to accommodate this constraint.

LIBRARY ieee ;
USE ieee.std logic 1164.all ;
USE ieee.std logic unsigned.all ;
LIBRARY lpm ;
USE lpm.lpm components.all ;
USE work.components.regne ;
USE work.components.upcount ;

ENTITY prob10 11 IS
GENERIC ( N : INTEGER := 4 ) ;
PORT ( Clock, Resetn : IN STD LOGIC ;
s, WrInit, Rd : IN STD LOGIC ;
DataIn : IN STD LOGIC VECTOR(N,1 DOWNTO 0) ;
RAdd : IN INTEGER RANGE 0 TO 3 ;
DataOut : BUFFER STD LOGIC VECTOR(N,1 DOWNTO 0) ;
Done : BUFFER STD LOGIC ) ;
END prob10 11 ;

ARCHITECTURE Behavior OF prob10 11 IS

TYPE STATE TYPE IS ( S1, S2, S3, S4, S5, S6, S7, S8, S9 ) ;
SIGNAL y : STATE TYPE ;
SIGNAL Ci, Cj : INTEGER RANGE 0 TO 3 ; - - counters Ci & Cj output
SIGNAL RData, ABMux : STD LOGIC VECTOR(N,1 DOWNTO 0) ;
SIGNAL Int, Csel, Wr, BltA : STD LOGIC ;
SIGNAL CMux, IMux : INTEGER RANGE 0 TO 3 ;- - address mux outputs
SIGNAL Ain, Bin, Aout, Bout : STD LOGIC ;
SIGNAL LI, LJ, EI, EJ, zi, zj, WE, NClock : STD LOGIC ;
SIGNAL Zero : INTEGER RANGE 3 DOWNTO 0 ; - - parallel data for Ci = 0
SIGNAL A, B, ABData : STD LOGIC VECTOR(N,1 DOWNTO 0) ;
SIGNAL MemAdd : STD LOGIC VECTOR(1 DOWNTO 0) ; - - SRAM address holder
BEGIN
FSM transitions: PROCESS ( Resetn, Clock )
BEGIN
: : : code not shown. See Figure 10.40
END PROCESS ;

: : : con’t

10-18
 FSM outputs: PROCESS ( y, s, BltA, zi, zj )
BEGIN
: : : code not shown. See Figure 10.40
END PROCESS ;
Int <= ’0’ WHEN y = S1 ELSE ’1’ ;
Zero <= 0 ;
RegA: regne GENERIC MAP ( N => N )
PORT MAP ( ABData, Resetn, Ain, Clock, A ) ;
RegB: regne GENERIC MAP ( N => N )
PORT MAP ( ABData, Resetn, Bin, Clock, B ) ;
BltA <= ’1’ WHEN B < A ELSE ’0’ ;
ABMux <= A WHEN Bout = ’0’ ELSE B ;
RDAta <= ABMux WHEN WrInit = ’0’ ELSE DataIn ;
OuterLoop: upcount GENERIC MAP ( modulus => 4 )
PORT MAP ( Resetn, Clock, EI, LI, Zero, Ci ) ;
InnerLoop: upcount GENERIC MAP ( modulus => 4 )
PORT MAP ( Resetn, Clock, EJ, LJ, Ci, Cj ) ;
CMux <= Ci WHEN Csel = ’0’ ELSE Cj ;
IMux <= Cmux WHEN Int = ’1’ ELSE Radd ;

MemAdd <= CONV STD LOGIC VECTOR(IMux, 2) ;

WE <= WrInit OR Wr ;
NClock <= NOT Clock ;

SRAM block : LPM RAM DQ

GENERIC MAP ( LPM WIDTH => 4, LPM WIDTHAD => 2,
LPM ADDRESS CONTROL => ”REGISTERED”,
LPM INDATA => ”REGISTERED”,
LPM OUTDATA => ”UNREGISTERED” )
PORT MAP ( address => MemAdd, we => WE, q => ABData,
inclock => NClock, data => RData ) ;
Zi <= ’1’ WHEN Ci = 2 ELSE ’0’ ;
Zj <= ’1’ WHEN Cj = 3 ELSE ’0’ ;
DataOut <= (OTHERS => ’Z’) WHEN Rd = ’0’ ELSE ABData ;
END Behavior ;

10.12. Pseudo-code that represents the log2 operation is

- - assume that K  1
L=0;
while (K > 1) do
K = K 2;
L= L+1;
end while ;
- - L now has the largest value such that 2L <K

An ASM chart that corresponds to the pseudo-code is

10-19
 Reset

S1
L←0
Load K

0 0
s
1
s
1

S2 S3
L←L+1 Shift-right K Done = 1

1 0
K > 1?

From the ASM chart, a shift-register is needed to divide K by 2, and a counter is needed for L. An appropriate
datapath circuit is

LK Data LL 0

n log2n

L L
EK E Shift-Right EL E Counter

K n
Clock
L

K > 1?

Kgt1

An ASM chart for the control circuit is

10-20
 Reset

S1
EL, LL
EK
1
0 0
LK s
0 1
s
1

S2 S3

EL EK Done = 1

1 0
Kgt1

Complete VHDL code for this circuit is shown below.

LIBRARY ieee ;
USE ieee.std logic 1164.all ;
USE ieee.std logic unsigned.all ;
USE work.components.all ;

ENTITY prob10 12 IS
PORT ( Clock, Resetn, LK, s : IN STD LOGIC ;
Data : IN STD LOGIC VECTOR(7 DOWNTO 0) ;
L : BUFFER INTEGER RANGE 0 TO 7 ;
Done : OUT STD LOGIC ) ;
END prob10 12 ;

ARCHITECTURE Behavior OF prob10 12 IS

TYPE State type IS ( S1, S2, S3 ) ;
SIGNAL y : State type ;
SIGNAL K : STD LOGIC VECTOR(7 DOWNTO 0) ;
SIGNAL Kgt1, EK, LL, EL, low : STD LOGIC ;
SIGNAL Zero : INTEGER RANGE 0 TO 7 ;
BEGIN
FSM transitions: PROCESS ( Resetn, Clock )
BEGIN
IF Resetn = ’0’ THEN
y <= S1 ;
ELSIF (Clock’EVENT AND Clock = ’1’) THEN

: : : con’t

10-21
 CASE y IS
WHEN S1 =>
IF s = ’0’ THEN y <= S1 ; ELSE y <= S2 ; END IF ;
WHEN S2 =>
IF Kgt1 =’1’ THEN y <= S2 ; ELSE y <= S3 ; END IF ;
WHEN S3 =>
IF s = ’1’ THEN y <= S3 ; ELSE y <= S1 ; END IF ;
END CASE ;
END IF ;
END PROCESS ;
FSM outputs: PROCESS ( y, LK, Kgt1 )
BEGIN
EL <= ’0’ ; LL <= ’0’; EK <= ’0’; Done <= ’0’;
CASE y IS
WHEN S1 =>
EL <= ’1’ ; LL <= ’1’;
IF LK = ’1’ THEN EK <= ’1’ ; ELSE EK <=’0’; END IF ;
WHEN S2 =>
EK <= ’1’ ;
IF Kgt1 = ’1’ THEN EL <= ’1’ ; ELSE EL <=’0’; END IF ;
WHEN S3 =>
Done <= ’1’ ;
END CASE ;
END PROCESS ;
low <= ’0’ ;
ShiftK: shiftrne GENERIC MAP ( N => 8 )
PORT MAP ( Data, LK, EK, low, Clock, K ) ;
Zero <= 0 ;
CntL: upcount GENERIC MAP ( modulus => 8 )
PORT MAP ( Resetn, Clock, EL, LL, Zero, L ) ;
Kgt1 <= ’1’ WHEN K > 1 ELSE ’0’ ;
END Behavior ;

10.13. LIBRARY ieee ;

USE ieee.std logic 1164.all ;
USE ieee.std logic unsigned.all ;
USE work.components.all ;

entity prob10 13 is
GENERIC ( N : INTEGER := 8 ) ;
PORT ( Clock, Resetn : IN STD LOGIC ;
Data : IN STD LOGIC VECTOR(N,1 DOWNTO 0) ;
RAdd : IN INTEGER RANGE 0 TO 3 ;
s, ER : IN STD LOGIC ;
M : OUT STD LOGIC VECTOR(N,1 DOWNTO 0) ;
Done : OUT STD LOGIC ) ;
END prob10 13 ;

: : : con’t

10-22
ARCHITECTURE Behavior OF prob10 13 IS
TYPE State type IS ( S1, S2, S3, S4, S5 ) ;
SIGNAL y : State type ;
SIGNAL Dec RAdd, Rin : STD LOGIC VECTOR(0 TO 3) ;
TYPE RegArray IS
ARRAY(0 TO 3) OF STD LOGIC VECTOR(N,1 DOWNTO 0) ;
SIGNAL R : RegArray ;
SIGNAL Ri, SR, Sin: STD LOGIC VECTOR(N,1 DOWNTO 0) ;
SIGNAL Sum : STD LOGIC VECTOR(N,1 DOWNTO 0) ;
SIGNAL ES, Ssel, EC, LC, z : STD LOGIC ;
SIGNAL C : INTEGER RANGE 0 TO 3 ;
SIGNAL LA, EB, zz, Div : STD LOGIC ;
BEGIN
FSM transitions: PROCESS ( Resetn, Clock )
BEGIN
IF Resetn = ’0’ THEN
y <= S1 ;
ELSIF (Clock’EVENT AND Clock = ’1’) THEN
CASE y IS
WHEN S1 => IF s = ’0’ THEN y <= S1 ; ELSE y <= S2 ; END IF ;
WHEN S2 => IF z = ’1’ THEN y <= S3 ; ELSE y <= S2 ; END IF ;
WHEN S3 => y <= S4 ;
WHEN S4 => IF zz=’0’ THEN y <= S4 ; ELSE y <= S5 ; END IF ;
WHEN S5 => IF s = ’1’ THEN y <= S5 ; ELSE y <= S1 ; END IF ;
END CASE ;
END IF ;
END PROCESS ;
FSM outputs: PROCESS ( y, z )
BEGIN
EC <= ’0’ ; LC <= ’0’; Ssel <= ’0’; ES <= ’0’; Done <= ’0’;
LA <= ’0’ ; EB <= ’0’; Div <= ’0’;
CASE y IS
WHEN S1 =>
EC <= ’1’ ; LC <= ’1’; ES <= ’1’;
WHEN S2 =>
ES <= ’1’ ; Ssel <= ’1’;
IF z=’0’ THEN EC <= ’1’ ; ELSE EC <= ’0’; END IF ;
WHEN S3 =>
LA <= ’1’ ; EB <= ’1’;
WHEN S4 =>
Div <= ’1’ ; - - (not really used in this cct)
WHEN S5 =>
Div <= ’1’ ; Done <= ’1’;
END CASE ;
END PROCESS ;
WITH RAdd SELECT - - 2-to-4 decoder
Dec RAdd <= ”1000” WHEN 0,
”0100” WHEN 1,
”0010” WHEN 2,
”0001” WHEN OTHERS ;
Rin <= Dec RAdd WHEN ER = ’1’ ELSE ”0000” ;

: : : con’t
10-23
 GenReg: FOR i IN 0 TO 3 GENERATE
Reg: regne GENERIC MAP ( N => N )
PORT MAP ( Data, Resetn, Rin(i), Clock, R(i) ) ;
END GENERATE ;
- - downcnt is defined in Figure 7.55
Count: downcnt GENERIC MAP ( modulus => 4 )
PORT MAP ( Clock, EC, LC, C ) ;
z <= ’1’ WHEN C = 0 ELSE ’0’ ; - - NOR GATE
Sin <= Sum WHEN Ssel = ’1’ ELSE (OTHERS => ’0’) ;
RegS: regne GENERIC MAP ( N => N )
PORT MAP ( Sin, Resetn, ES, Clock, SR ) ;
- - Mux Regs
WITH C SELECT
Ri <= R(0) WHEN 0, R(1) WHEN 1, R(2) WHEN 2, R(3) WHEN OTHERS ;
Sum <= SR + Ri ;
- - Divide By 4
M <= ”00” & SR(N,1 DOWNTO 2) ;
zz <= ’1’ ;
END Behavior ;

10.14. From Figures 10.26 and 10.27, we can see that the divider subcircuit does not use its adder while in state S1.
Since the control circuit for the divider stays in S1 while s = 0, it is possible to lend the adder to another
circuit while we are in S1 and s = 0. The Figure below shows the changes needed in the divider circuit: a
multiplexer is added to each data input on the adder. The multiplexer select line is driven by the divider’s s
input — this signal is called Div in the figure, because Div is the signal in the Mean circuit that drives the s
input on the divider subcircuit. When Div = 1 the adder is provided with the normal data used in the division
operation. But when Div = 0 the adder is provided with the external data inputs named Op1 and Op2, which
come from the Mean circuit. Note that the Cin input on the adder is controlled by Div. This feature is needed
because the divider uses its adder to perform subtraction.

Op1 R Op2 B

n n n n
0 1 0 1

AddIn0 AddIn1

Cout C out + C in Div

MeanOut

DivOut

VHDL code for the modified divider circuit is shown below.

10-24
LIBRARY ieee ;
USE ieee.std logic 1164.all ;
USE ieee.std logic unsigned.all ;
USE work.components.all ;

ENTITY divider IS
GENERIC ( N : INTEGER := 8 ) ;
PORT ( Clock, Resetn : IN STD LOGIC ;
s, LA, EB : IN STD LOGIC ;
DataA, DataB : IN STD LOGIC VECTOR(N,1 DOWNTO 0) ;
R, Q : BUFFER STD LOGIC VECTOR(N,1 DOWNTO 0) ;
Op1, Op2 : IN STD LOGIC VECTOR(N,1 DOWNTO 0) ; - - new ports
Result : OUT STD LOGIC VECTOR(N,1 DOWNTO 0) ; - - new port
Done : OUT STD LOGIC ) ;
END divider ;

ARCHITECTURE Behavior OF divider IS

TYPE STATE TYPE IS ( S1, S2, S3 ) ;
SIGNAL y : STATE TYPE ;
SIGNAL Zero, Cout, z : STD LOGIC ;
SIGNAL EA, Rsel, LR, ER, ER0, LC, EC, R0 : STD LOGIC ;
SIGNAL A, B, DataR : STD LOGIC VECTOR(N,1 DOWNTO 0) ;
SIGNAL Sum : STD LOGIC VECTOR(N DOWNTO 0) ; - - adder outputs
SIGNAL Count : INTEGER RANGE 0 TO N,1 ;
SIGNAL AddIn1 : STD LOGIC VECTOR(N DOWNTO 0) ; - - see problem 10.14
SIGNAL AddIn2 : STD LOGIC VECTOR(N,1 DOWNTO 0) ;
BEGIN
FSM transitions: PROCESS ( Resetn, Clock )
BEGIN
: : : code not shown. See Figure 10.28
END PROCESS ;

FSM outputs: PROCESS ( s, y, Cout, z )

BEGIN
: : : code not shown. See Figure 10.28
END PROCESS ;

Zero <= ’0’ ;

RegB: regne GENERIC MAP ( N => N )
PORT MAP ( DataB, Resetn, EB, Clock, B ) ;
ShiftR: shiftlne GENERIC MAP ( N => N )
PORT MAP ( DataR, LR, ER, R0, Clock, R ) ;
FF R0: muxdff PORT MAP ( Zero, A(N,1), ER0, Clock, R0 ) ;
ShiftA: shiftlne GENERIC MAP ( N => N )
PORT MAP ( DataA, LA, EA, Cout, Clock, A ) ;
Q <= A ;
Counter: downcnt GENERIC MAP ( modulus => N )
PORT MAP ( Clock, EC, LC, Count ) ;
z <= ’1’ WHEN Count = 0 ELSE ’0’ ;

: : : con’t

10-25
 - - new code; see problem 10.14
AddIn1 <= R & R0 WHEN s = ’1’ ELSE ’0’ & Op1 ;
AddIn2 <= NOT B WHEN s = ’1’ ELSE Op2 ;
Sum <= AddIn1 + AddIn2 + s ;
Cout <= Sum(N) ;
DataR <= (OTHERS => ’0’) WHEN Rsel = ’0’ ELSE Sum ;
Result <= Sum(N,1 DOWNTO 0) ;
END Behavior ;

Code for the modified Mean circuit is shown below.

LIBRARY ieee ;
USE ieee.std logic 1164.all ;
USE ieee.std logic unsigned.all ;
USE work.components.all ;

ENTITY prob10 15 is
GENERIC ( N : INTEGER := 8 ) ;
PORT ( Clock, Resetn : IN STD LOGIC ;
Data : IN STD LOGIC VECTOR(N,1 DOWNTO 0) ;
RAdd : IN INTEGER RANGE 0 TO 3 ;
s, ER : IN STD LOGIC ;
M : BUFFER STD LOGIC VECTOR(N,1 DOWNTO 0) ;
Done : OUT STD LOGIC ) ;
END prob10 15 ;

ARCHITECTURE Behavior OF prob10 15 IS

COMPONENT divider
GENERIC ( N : INTEGER := 8 ) ;
PORT ( Clock, Resetn : IN STD LOGIC ;
s, LA, EB : IN STD LOGIC ;
DataA, DataB : IN STD LOGIC VECTOR(N,1 DOWNTO 0) ;
R, Q : BUFFER STD LOGIC VECTOR(N,1 DOWNTO 0) ;
Op1, Op2 : IN STD LOGIC VECTOR(N,1 DOWNTO 0) ; - - new ports
Result : OUT STD LOGIC VECTOR(N,1 DOWNTO 0) ; - - new port
Done : OUT STD LOGIC ) ;
END COMPONENT ;
TYPE State type IS ( S1, S2, S3, S4, S5 ) ;
SIGNAL y : State type ;
SIGNAL Dec RAdd, Rin : STD LOGIC VECTOR(0 TO 3) ;
TYPE RegArray IS
ARRAY(0 TO 3) OF STD LOGIC VECTOR(N,1 DOWNTO 0) ;
SIGNAL R : RegArray ;
SIGNAL Ri, SR, Sin: STD LOGIC VECTOR(N,1 DOWNTO 0) ;
SIGNAL Sum, Remainder, K : STD LOGIC VECTOR(N,1 DOWNTO 0) ;
SIGNAL ES, Ssel, EC, LC, z : STD LOGIC ;

: : : con’t

10-26
 SIGNAL C : INTEGER RANGE 0 TO 3 ;
SIGNAL LA, EB, zz, Div : STD LOGIC ;
BEGIN
FSM tran: PROCESS ( Resetn, Clock )
BEGIN
IF Resetn = ’0’ THEN
y <= S1 ;
ELSIF (Clock’EVENT AND Clock = ’1’) THEN
CASE y IS
WHEN S1 => IF s = ’0’ THEN y <= S1 ; ELSE y <= S2 ; END IF ;
WHEN S2 => IF z = ’1’ THEN y <= S3 ; ELSE y <= S2 ; END IF ;
WHEN S3 => y <= S4 ;
WHEN S4 => IF zz=’0’ THEN y <= S4 ; ELSE y <= S5 ; END IF ;
WHEN S5 => IF s = ’1’ THEN y <= S5 ; ELSE y <= S1 ; END IF ;
END CASE ;
END IF ;
END PROCESS ;
FSM outputs: PROCESS ( y, z )
BEGIN
EC <= ’0’ ; LC <= ’0’; Ssel <= ’0’; ES <= ’0’; Done <= ’0’;
LA <= ’0’ ; EB <= ’0’; Div <= ’0’;
CASE y IS
WHEN S1 =>
EC <= ’1’ ; LC <= ’1’; ES <= ’1’;
WHEN S2 =>
ES <= ’1’ ; Ssel <= ’1’;
IF z=’0’ THEN EC <= ’1’ ; ELSE EC <= ’0’; END IF ;
WHEN S3 =>
LA <= ’1’ ; EB <= ’1’;
WHEN S4 =>
Div <= ’1’ ;
WHEN S5 =>
Div <= ’1’ ; Done <= ’1’;
END CASE ;
END PROCESS ;

- - 2-to-4 decoder
WITH RAdd SELECT
Dec RAdd <= ”1000” WHEN 0,
”0100” WHEN 1,
”0010” WHEN 2,
”0001” WHEN OTHERS ;
Rin <= Dec RAdd WHEN ER = ’1’ ELSE ”0000” ;
GenReg: FOR i IN 0 TO 3 GENERATE
Reg: regne GENERIC MAP ( N => N )
PORT MAP ( Data, Resetn, Rin(i), Clock, R(i) ) ;
END GENERATE ;

: : : con’t

10-27
 - - downcnt is defined in Figure 7.55
Count: downcnt GENERIC MAP ( modulus => 4 )
PORT MAP ( Clock, EC, LC, C ) ;
z <= ’1’ WHEN C = 0 ELSE ’0’ ; - - NOR GATE
Sin <= Sum WHEN Ssel = ’1’ ELSE (OTHERS => ’0’) ;
RegS: regne GENERIC MAP ( N => N )
PORT MAP ( Sin, Resetn, ES, Clock, SR ) ;
- - Mux Regs
WITH C SELECT
Ri <= R(0) WHEN 0, R(1) WHEN 1, R(2) WHEN 2, R(3) WHEN OTHERS ;
- - Sum <= SR + Ri (see problem 10.13);
K <= ”00000100” ;
DivideBy4: divider
PORT MAP ( Clock => Clock, Resetn => Resetn, s => Div, LA => LA,
EB => EB, DataA => SR, DataB => K, R => Remainder, Q => M,
Op1 => SR, Op2 => Ri, Result => Sum, Done => zz );
END Behavior ;

10.15. The modified pseudo-code is

for i = 0 to k , 2 do
A = Ri ;
for j = i + 1 to k , 1 do
if Rj < A then
Ri = Rj ;
Rj = A ;
end if ;
A = Ri ;
end for ;
end for ;

An ASM chart that corresponds to the pseudo-code is

10-28
 Reset

S1

Ci ← 0
Load registers

0
s

1
S2

A ← R i, C j ← C i

S3
Ci ← Ci + 1
Cj ← Cj + 1

S4

S5

Ri ← R j
1
R j < A?
Cj ← Cj + 1 S6
0
Rj ← A

S7

A ← Ri

0
C j = k – 1?

S8
1 0
Done = 1 s

0 1
C i = k – 2?

10-29
 From the ASM chart, we can see that the datapath circuit needs a multiplexer to allow the operation Ri Rj .
An appropriate datapath is shown below.

DataIn

WrInit
n

Rin 0 E Rin 1 E Rin 2 E Rin 3 E

Imux

Ain E
Cj n
Clock
A n Rj

Rjout Rd
<

RjltA DataOut

An ASM chart for the control circuit is

10-30
 Reset

S1

LI, EI, Int = 0

0
s

1
S2

Int = 1, Csel = 0, Ain, LJ, EJ

S3
EI
EJ

S4

S5

Csel = 0, Int = 1, Wr, Rjout

1
RjltA
EJ S6
0
Csel = 1, Int = 1, Wr, Aout

S7

Csel = 0, Int = 1, Ain

0
zj

S8
1 0
Done = 1 s

0 1
zi

10-31
10.17. LIBRARY ieee ;
USE ieee.std logic 1164.all ;
USE ieee.std logic unsigned.all ;
USE work.components.all ;

ENTITY prob10 17 is
GENERIC ( N : INTEGER := 4 ; LOG2K : INTEGER := 2 );
PORT ( Clock, Resetn : IN STD LOGIC ;
s, WrInit, Rd : IN STD LOGIC ;
DataIn : IN STD LOGIC VECTOR(N,1 DOWNTO 0) ;
RAdd : IN INTEGER RANGE 0 TO 3 ;
DataOut : BUFFER STD LOGIC VECTOR(N,1 DOWNTO 0) ;
Done : BUFFER STD LOGIC ) ;
END prob10 17 ;

ARCHITECTURE Behavior of prob10 17 IS

TYPE State type IS ( S1, S2, S3, S4, S5, S6, S7, S8 ) ;
SIGNAL y : State type ;
SIGNAL Ci, Cj : INTEGER RANGE 0 to 3 ;
SIGNAL Rin : STD LOGIC VECTOR(0 TO 3) ;
TYPE RegArray IS
ARRAY(0 TO 3) OF STD LOGIC VECTOR(N,1 DOWNTO 0) ;
SIGNAL R : RegArray ;
SIGNAL RData : STD LOGIC VECTOR(N,1 DOWNTO 0) ;
SIGNAL Int, Csel, Wr, RjltA : STD LOGIC ;
SIGNAL Cmux, Imux : INTEGER RANGE 0 TO 3 ;
SIGNAL LI, LJ, EI, EJ, zi, zj, Ain, Rjout : STD LOGIC ;
SIGNAL Zero : INTEGER RANGE 0 TO 3 ;
SIGNAL A, AData : STD LOGIC VECTOR(N,1 DOWNTO 0) ;
SIGNAL ARjMux, Rj : STD LOGIC VECTOR(N,1 DOWNTO 0) ;
BEGIN
FSM transitions: PROCESS ( Resetn, Clock )
BEGIN
IF Resetn = ’0’ THEN
y <= S1 ;
ELSIF ( Clock’EVENT AND Clock = ’1’) THEN
CASE y IS
WHEN S1 => IF s = ’0’ THEN y <= S1 ; ELSE y <= S2 ; END IF ;
WHEN S2 => y <= S3 ;
WHEN S3 => y <= S4 ;
WHEN S4 => IF RjltA = ’1’ THEN y <= S5 ; ELSE y <= S7 ; END IF ;
WHEN S5 => y <= S6 ;
WHEN S6 => y <= S7 ;
WHEN S7 =>
IF zj = ’0’ THEN y <= S4 ;
ELSIF zi =’0’ THEN y <= S2 ;
ELSE y <= S8 ;
END IF ;

: : : con’t

10-32
 WHEN S8 =>
IF s =’1’ THEN y <= S8 ; ELSE y <= S1 ; END IF ;
END CASE ;
END IF ;
END PROCESS ;
Int <= ’0’ WHEN y = S1 ELSE ’1’ ;
Done <= ’1’ WHEN y = S8 ELSE ’0’ ;
FSM outputs: PROCESS ( y, zi, zj )
BEGIN
LI <=’0’ ; LJ <= ’0’; EI <=’0’; EJ <=’0’; Csel <= ’0’;
Wr <= ’0’ ; Ain <= ’0’; RjOut <= ’0’;
CASE y IS
WHEN S1 => LI <= ’1’ ; EI <= ’1’;
WHEN S2 => Ain <= ’1’ ; LJ <= ’1’; EJ <= ’1’;
WHEN S3 => EJ <= ’1’ ;
WHEN S4 => - - nothing to do
WHEN S5 => Wr <= ’1’ ; Rjout <= ’1’;
WHEN S6 => Csel <= ’1’ ; Wr <= ’1’;
WHEN S7 => Ain <= ’1’ ;
IF zj = ’0’ THEN EJ <= ’1’ ;
ELSE EJ <= ’0’ ;
IF zi = ’0’ THEN EI <= ’1’ ;
ELSE EI <= ’0’ ;
END IF ;
END IF ;
WHEN S8 => - -
END CASE ;
END PROCESS ;
Zero <= 0 ;
GenReg: FOR i IN 0 TO 3 GENERATE
Reg: regne GENERIC MAP ( N => N )
PORT MAP ( RData, Resetn, Rin(i), Clock, R(i) ) ;
END GENERATE ;
RegA: regne GENERIC MAP ( N => N )
PORT MAP ( AData, Resetn, Ain, Clock, A ) ;
- - New DataPath
WITH Cj SELECT
Rj <= R(0) WHEN 0,
R(1) WHEN 1,
R(2) WHEN 2,
R(3) WHEN OTHERS ;
ARjMux <= Rj WHEN Rjout=’1’ ELSE A ;
RData <= ARjMux WHEN WRInit = ’0’ ELSE DataIn ;
RjltA <= ’1’ WHEN Rj < A ELSE ’0’ ;
- - End of New DataPath

OuterLoop: upcount GENERIC MAP ( modulus => 4 )

PORT MAP ( Resetn, Clock, EI, LI, Zero, Ci ) ;
InnerLoop: upcount GENERIC MAP ( modulus => 4 )
PORT MAP ( Resetn, Clock, EJ, LJ, Ci, Cj ) ;

: : : con’t

10-33
 Cmux <= Ci WHEN Csel = ’0’ ELSE Cj ;
Imux <= Cmux WHEN Int = ’1’ ELSE Radd ;
WITH Imux SELECT
AData <= R(0) WHEN 0,
R(1) WHEN 1,
R(2) WHEN 2,
R(3) WHEN OTHERS ;
RinDec: PROCESS ( WrInit, Wr, Imux )
BEGIN
IF (WrInit OR Wr) = ’1’ THEN
CASE Imux IS
WHEN 0 => Rin <= ”1000” ;
WHEN 1 => Rin <= ”0100” ;
WHEN 2 => Rin <= ”0010” ;
WHEN OTHERS => Rin <= ”0001” ;
END CASE ;
ELSE Rin <= ”0000” ;
END IF ;
END PROCESS ;
zi <= ’1’ WHEN Ci = 2 ELSE ’0’ ;
zj <= ’1’ WHEN Cj = 3 ELSE ’0’ ;
DataOut <= (OTHERS => ’Z’) WHEN Rd=’0’ ELSE AData ;
END Behavior ;

10.18. Reset

S1

Load registers

0
w

1
S2

R3 ← R1

S3
R1 ← R2

S4
R2 ← R3

10-34
10.19. (a) An ASM chart for the control circuit is shown below.

Reset

S1

0
w

1
S2

R1 out ,R3 in

S3
R2 out ,R1 in

S4
R3 out ,R2 in

(b) LIBRARY ieee ;

USE ieee.std logic 1164.all ;
USE ieee.std logic unsigned.all ;
USE work.components.all ;

ENTITY prob10 19 IS
GENERIC ( N : INTEGER := 8 ) ;
PORT ( Data : IN STD LOGIC VECTOR(N,1 DOWNTO 0) ;
Resetn, w : IN STD LOGIC ;
Clock : IN STD LOGIC ;
RinExt : IN STD LOGIC VECTOR(1 TO 3);
BusWires : BUFFER STD LOGIC VECTOR(N,1 DOWNTO 0) ) ;
END prob10 19 ;

ARCHITECTURE Behavior OF prob10 19 IS

TYPE State type IS ( S1, S2, S3, S4 ) ;
SIGNAL y : State type ;
SIGNAL RinCtrl, Rin, Rout : STD LOGIC VECTOR(1 TO 3) ;
SIGNAL R1, R2, R3 : STD LOGIC VECTOR(N,1 DOWNTO 0) ;

: : : con’t

10-35
 BEGIN
FSM transitions: PROCESS ( Resetn, Clock )
BEGIN
IF Resetn = ’0’ THEN
y <= S1 ;
ELSIF (Clock’EVENT AND Clock = ’1’) THEN
CASE y IS
WHEN S1 => IF w = ’0’ THEN y <= S1 ; ELSE y <= S2 ; END IF ;
WHEN S2 => y <= S3 ;
WHEN S3 => y <= S4 ;
WHEN S4 => y <= S1 ;
END CASE ;
END IF ;
END PROCESS ;
FSM outputs: PROCESS ( y )
BEGIN
RinCtrl <= ”000” ; Rout <= ”000” ;
CASE y IS
WHEN S1 =>
WHEN S2 => Rout(1) <= ’1’ ; RinCtrl(3) <= ’1’ ;
WHEN S3 => Rout(2) <= ’1’ ; RinCtrl(1) <= ’1’ ;
WHEN S4 => Rout(3) <= ’1’ ; RinCtrl(2) <= ’1’ ;
END CASE ;
END PROCESS ;
Reg1: regne GENERIC MAP ( N => N )
PORT MAP ( BusWires, Resetn, Rin(1), Clock, R1 ) ;
Reg2: regne GENERIC MAP ( N => N )
PORT MAP ( BusWires, Resetn, Rin(2), Clock, R2 ) ;
Reg3: regne GENERIC MAP ( N => N )
PORT MAP ( BusWires, Resetn, Rin(3), Clock, R3 ) ;
Rin <= RinCtrl OR RinExt ;
- - Mux
WITH Rout SELECT
BusWires <= R1 WHEN ”100”,
R2 WHEN ”010”,
R3 WHEN ”001”,
Data WHEN OTHERS ;
END Behavior ;

10.20. An ASM chart for the processor is shown below.

10-36
 Reset

T0

0
w

Load function register

T1

1
R X ← Data ,Done I=0

1
R X ← R Y ,Done I=1

A ← RX

T2

1
I=2

0
G ← A + RY
G ← A – RY

T3
R X ← G ,Done

10-37
10.21. (a) An ASM chart for the control circuit is shown below.

Reset

T0

0
w

FRin

T1

1
Rin = X, Extern, Done I=0

1
Rin = X, Rout = Y, Done I=1

Ain, Rout = X

T2
Gin, Rout = Y

1
I=2

0
AddSub = 0
AddSub = 1

T3

Gout, Rin = X, Done

10-38
(b) LIBRARY ieee ;
USE ieee.std logic 1164.all ;
USE ieee.std logic unsigned.all ;
USE work.components.all ;

ENTITY prob10 21 IS
PORT ( Data : IN STD LOGIC VECTOR(7 DOWNTO 0) ;
Clock, Resetn,w : IN STD LOGIC ;
F, Rx, Ry : IN STD LOGIC VECTOR(1 DOWNTO 0) ;
Done : OUT STD LOGIC ;
BusWires : INOUT STD LOGIC VECTOR(7 DOWNTO 0) ) ;
END prob10 21 ;

ARCHITECTURE Behavior OF prob10 21 IS

TYPE State Type IS ( T0, T1, T2, T3 ) ;
SIGNAL T : State Type ;
SIGNAL Gin, Gout, Extern : STD LOGIC ;
SIGNAL High, FRin, AddSub, Ain : STD LOGIC ;
SIGNAL Rin, Rout, X, Y : STD LOGIC VECTOR(0 TO 3) ;
SIGNAL I : STD LOGIC VECTOR(1 DOWNTO 0) ;
SIGNAL R0, R1, R2, R3, G, A, Sum : STD LOGIC VECTOR(7 DOWNTO 0) ;
SIGNAL Func, FuncReg, Sel : STD LOGIC VECTOR(1 TO 6) ;
BEGIN
FSM Transitions: PROCESS ( Clock, Resetn )
BEGIN
IF Resetn = ’0’ THEN
T <= T0 ;
ELSIF Clock’EVENT AND Clock = ’1’ THEN
CASE T IS
WHEN T0 =>
IF w = ’0’ THEN T <= T0 ; ELSE T <= T1 ; END IF ;
WHEN T1 =>
IF I = ”00” OR I = ”01” THEN T <= T0 ; ELSE T <= T2 ; END IF ;
WHEN T2 =>
T <= T3 ;
WHEN T3 =>
T <= T0 ;
END CASE ;
END IF ;
END PROCESS ;
FSM Outputs: PROCESS ( w, T, I )
BEGIN
FRin <= ’0’ ; Rin <= ”0000” ; Rout <= ”0000” ; Done <= ’0’ ;
Gin <= ’0’ ; Gout <= ’0’ ; Extern <= ’0’ ;
Ain <= ’0’ ; AddSub <= ’0’ ;

: : : con’t

10-39
 CASE T IS
WHEN T0 =>
IF w = ’1’ THEN FRin <= ’1’ ;
ELSE FRin <= ’0’ ;
END IF ;
WHEN T1 =>
Ain <= ’1’ ; - - doesn’t matter if we load A when not needed
IF I = ”00” THEN
Done <= ’1’ ; Rin <= X ; Rout <= ”0000”; Extern <= ’1’ ;
ELSIF I = ”01” THEN
Done <= ’1’ ; Rin <= X ; Rout <= Y ; Extern <= ’0’ ;
ELSE
Done <= ’0’ ; Rin <= ”0000” ; Rout <= X ; Extern <= ’0’ ;
END IF ;
WHEN T2 =>
Gin <= ’1’ ; Rout <= Y ;
IF I = ”10” THEN AddSub <= ’0’ ;
ELSE AddSub <= ’1’ ;
END IF ;
WHEN T3 =>
Gout <= ’1’ ; Rin <= X ; Done <= ’1’ ;
END CASE ;
END PROCESS ;
- - Datapath is the same as in Figure 7.75, without the T counter
Func <= F & Rx & Ry ;
functionreg: regne GENERIC MAP ( N => 6 )
PORT MAP ( Func, Resetn, FRin, Clock, FuncReg ) ;
High <= ’1’ ;
I <= FuncReg(1 TO 2) ;
decX: dec2to4 PORT MAP ( FuncReg(3 TO 4), High, X ) ;
decY: dec2to4 PORT MAP ( FuncReg(5 TO 6), High, Y ) ;
- - Note: changed GENERIC parameter N in regne that sets # bits to 8
reg0: regne PORT MAP ( BusWires, Resetn, Rin(0), Clock, R0 ) ;
reg1: regne PORT MAP ( BusWires, Resetn, Rin(1), Clock, R1 ) ;
reg2: regne PORT MAP ( BusWires, Resetn, Rin(2), Clock, R2 ) ;
reg3: regne PORT MAP ( BusWires, Resetn, Rin(3), Clock, R3 ) ;
regA: regne PORT MAP ( BusWires, Resetn, Ain, Clock, A ) ;
alu: WITH AddSub SELECT
Sum <= A + BusWires WHEN ’0’,
A , BusWires WHEN OTHERS ;
regG: regne PORT MAP ( Sum, Resetn, Gin, Clock, G ) ;
Sel <= Rout & Gout & Extern ;
WITH Sel SELECT
BusWires <= R0 WHEN ”100000”,
R1 WHEN ”010000”,
R2 WHEN ”001000”,
R3 WHEN ”000100”,
G WHEN ”000010”,
Data WHEN OTHERS ;
END Behavior ;

10-40
10.22. (a) An ASM chart for the traffic controller is shown below.

Reset

S1
C1 ← t1

S2

C 1 ← C 1 – 1, G1 ,R2 C1 ← t1

0 C 2 = 0?
C 1 = 0? 0

1 S5
C2 ← t2 C 2 ← C 2 – 1, R1 ,Y2

S3
C 2 ← C 2 – 1, Y1 ,R2 C2 ← t2

0 C 1 = 0?
C 2 = 0? 0

1 S4
C1 ← t1 C 1 ← C 1 – 1, R1 ,G2

(b). The two counters, C1 and C2, each require clock enable and parallel-load inputs. Assuming that the
clock enables signals are called EC1 and EC2 and the parallel-load inputs are called LC1 and LC2, an ASM
chart for the control circuit is

10-41
 Reset

S1
EC1, LC1

S2

EC1, G1 ,R2 EC1, LC1

0 zC2
zC1 0

1 S5
EC2, LC2 EC2, R1 ,Y2

S3
EC2, Y1 ,R2 EC2, LC2

0 zC1
zC2 0

1 S4

EC1, LC1 EC1, R1 ,G2

(c) LIBRARY ieee ;

USE ieee.std logic 1164.all ;
USE ieee.std logic unsigned.all ;

ENTITY prob10 22 IS
PORT ( Clock, Resetn : IN STD LOGIC ;
G1, Y1, R1 : OUT STD LOGIC ;
G2, Y2, R2 : OUT STD LOGIC ) ;
END prob10 22 ;

: : : con’t

10-42
ARCHITECTURE Behavior OF prob10 22 IS
TYPE State type IS ( S1, S2, S3, S4, S5 ) ;
SIGNAL y : State type ;
SIGNAL zC1, zC2, EC1, LC1, EC2, LC2 : STD LOGIC ;
SIGNAL C1, C2, TICKS1, TICKS2 : STD LOGIC VECTOR(3 DOWNTO 0) ;
BEGIN
FSM transition: PROCESS ( Clock, Resetn )
BEGIN
IF Resetn = ’0’ THEN
y <= S1 ;
ELSIF Clock’EVENT AND Clock = ’1’ THEN
CASE y IS
WHEN S1 => y <= S2 ;
WHEN S2 => IF zC1 = ’0’ THEN y <= S2 ; ELSE y <= S3 ; END IF ;
WHEN S3 => IF zC2 = ’0’ THEN y <= S3 ; ELSE y <= S4 ; END IF ;
WHEN S4 => IF zC1 = ’0’ THEN y <= S4 ; ELSE y <= S5 ; END IF ;
WHEN S5 => IF zC2 = ’0’ THEN y <= S5 ; ELSE y <= S2 ; END IF ;
END CASE ;
END IF ;
END PROCESS ;
FSM outputs: PROCESS ( y, zC1, zC2 )
BEGIN
G1 <= ’0’ ; Y1 <= ’0’ ; R1 <= ’0’ ;
G2 <= ’0’ ; Y2 <= ’0’ ; R2 <= ’0’ ;
LC1 <= ’0’ ; EC1 <= ’0’ ; EC2 <= ’0’ ; LC2 <= ’0’ ;
CASE y IS
WHEN S1 =>
LC1 <= ’1’ ; EC1 <= ’1’ ;
WHEN S2 =>
EC1 <= ’1’ ; G1 <= ’1’ ; R2 <= ’1’ ;
IF zC1 = ’1’ THEN LC2 <= ’1’ ; EC2 <= ’1’ ; ELSE LC2 <= ’0’ ; EC2 <= ’0’ ; END IF ;
WHEN S3 =>
EC2 <= ’1’ ; Y1 <= ’1’ ; R2 <= ’1’ ;
IF zC2 = ’1’ THEN LC1 <= ’1’ ; EC1 <= ’1’ ; ELSE LC1 <= ’0’ ; EC1 <= ’0’ ; END IF ;
WHEN S4 =>
EC1 <= ’1’ ; R1 <= ’1’ ; G2 <= ’1’ ;
IF zC1 = ’1’ THEN LC2 <= ’1’ ; EC2 <= ’1’ ; ELSE LC2 <= ’0’ ; EC2 <= ’0’ ; END IF ;
WHEN S5 =>
EC2 <= ’1’ ; R1 <= ’1’ ; Y2 <= ’1’ ;
IF zC2 = ’1’ THEN LC1 <= ’1’ ; EC1 <= ’1’ ; ELSE LC1 <= ’0’ ; EC1 <= ’0’ ; END IF ;
END CASE ;
END PROCESS ;

- - Setup Constants
TICKS1 <= ”0011” ; - - 4 TICKS for C1
TICKS2 <= ”0001” ; - - 2 TICKS for C2
- - Check for zero count
zC1 <= ’1’ WHEN C1 = 0 ELSE ’0’ ;
zC2 <= ’1’ WHEN C2 = 0 ELSE ’0’ ;

: : : con’t

10-43
 - - Could use downcnt component instead
CNT C1: PROCESS
BEGIN
WAIT UNTIL Clock’EVENT AND Clock = ’1’ ;
IF EC1 = ’1’ THEN
IF LC1 = ’1’ THEN C1 <= TICKS1 ; ELSE C1 <= C1 , 1 ; END IF ;
END IF ;
END PROCESS ;
CNT C2: PROCESS
BEGIN
WAIT UNTIL Clock’EVENT AND Clock = ’1’ ;
IF EC2 = ’1’ THEN
IF LC2 = ’1’ THEN C2 <= TICKS2 ; ELSE C2 <= C2 , 1 ; END IF ;
END IF ;
END PROCESS ;
END Behavior ;

10.23. The debounce circuit has three parts, as shown below. The Data signal from the switch has to be synchronized
to the 102.4 KHz signal using two flip-flops. The synchronized signal called Sync is fed to an FSM. The FSM
also uses the counter shown, which counts for 1024 cycles of the 102.4 KHz signal, providing a 10 msec
delay.

1111111111
Sync 10

Meta LC L
Data D Q D Q
EC E Down-counter
102.4 KHz

Done

An ASM chart for the FSM is given below. The FSM provides the z output, which is the debounced version
of the Data signal.

10-44
 Reset

S1 1

z = 0, C ← 1023 Done
0

S4
0
Sync z = 0, C ← C – 1

S2 0

z = 1, C ← C – 1 Sync
1

S3
0
Done z = 1, C ← 1023

10.24. (a) If we set C1 = 1 pF, then Ra = 0 and Rb = 1:43 k

(b) If we set C1 = 1 pF, then Ra = 1:42 k and Rb = 0:71 k

10-45