Chapter 7

7.1.
Clock

Qa

Qb

Qc

7.2. The circuit in Figure 7.3 can be modified to implement an SR latch by connecting S to the Data input and
S + R to the Load input. Thus the value of S is loaded into the latch whenever either S or R is asserted.
Care must be taken to ensure that the Data signal remains stable while the Load signal is asserted.

7.3. R
Qb S R Qa Qb

1 1 0/1 1/0 (no change)

1 0 0 1
0 1 1 0
Qa 0 0 1 1
S

7.4. S
Q

Clk

Q
R

7-1
7.5.

1 T Q T Q T Q

100 MHz Q Q Q

50 MHz 25 MHz 12.5 MHz

100 MHz

50 MHz

25 MHz

12.5 MHz

0 ns 10 ns 20 ns 30 ns 40 ns 50 ns 60 ns 70 ns

7.6.

D Q Q
R

Q Q

Clock

S R Q(t + 1)

0 0 Q(t ) S Q
0 1 0
1 0 1 R Q
1 1 0

7-2
7.7. R
Q

Q
S

7.8.

T Q Q

K
Q Q

Clock

7.9. As the circuit in Figure P7.2 is drawn, it is not a useful flip-flop circuit, because setting C = 0 results in both
of the circuit outputs being set to 0. Consider the slightly modified circuit shown below:

This modified circuit acts as a negative-edge-triggered JK flip-flop, in which J = A; K = B; Clock =

C; Q = D; and Q = E . This circuit is found in the standard chip called 74LS107A (plus a Clear input,
which is not shown).

7-3
7.10. LIBRARY ieee ;
USE ieee.std logic 1164.all ;

ENTITY prob7 10 IS
PORT ( T, Resetn, Clock : IN STD LOGIC ;
Q : OUT STD LOGIC ) ;
END prob7 10 ;

ARCHITECTURE Behavior OF prob7 10 IS

SIGNAL Qint : STD LOGIC ;
BEGIN
PROCESS ( Resetn, Clock )
BEGIN
IF Resetn = ’0’ THEN
Qint <= ’0’ ;
ELSIF Clock’EVENT AND Clock = ’1’ THEN
IF T = ’1’ THEN
Qint <= NOT Qint ;
ELSE
Qint <= Qint ;
END IF ;
END IF ;
END PROCESS ;
Q <= Qint ;
END Behavior ;

7.11. LIBRARY ieee ;

USE ieee.std logic 1164.all ;

ENTITY prob7 11 IS
PORT ( J, K, Resetn, Clock : IN STD LOGIC ;
Q : OUT STD LOGIC ) ;
END prob7 11 ;

ARCHITECTURE Behavior OF prob7 11 IS

SIGNAL Qint : STD LOGIC ;
BEGIN
PROCESS ( Resetn, Clock )
BEGIN
IF Resetn = ’0’ THEN
Qint <= ’0’ ;
ELSIF Clock’EVENT AND Clock = ’1’ THEN
Qint <= ( J AND NOT Qint ) OR ( NOT K AND Qint ) ;
END IF ;
END PROCESS ;
Q <= Qint ;
END Behavior ;

7-4
7.13. Let S = s1 s0 be a binary number that specifies the number of bit-positions to shift by. Also let L be a
parallel-load input, and let R = r3 r2r1r0 be parallel data. If the inputs to the flip-flops are D0 : : :D3 and
the outputs are Q0 : : :Q3, then the barrel-shifter can be represented by the logic expressions

D3 = L
R3 + L
(s1s0 q3)
D2 = L
R2 + L
(s1s0 q2 + s1 s0 q3)
D1 = L
R1 + L
(s1s0 q1 + s1 s0 q2 + s1 s0 q3)
D0 = L
R0 + L
(s1s0 q0 + s1 s0 q1 + s1 s0 q2 + s1 s0 q3)

7.14. LIBRARY ieee ;

USE ieee.std logic 1164.all ;

ENTITY prob7 14 IS
PORT ( R : IN STD LOGIC VECTOR (3 DOWNTO 0) ;
Shift : IN STD LOGIC VECTOR (1 DOWNTO 0) ;
L, Clock : IN STD LOGIC ;
Q : BUFFER STD LOGIC VECTOR (3 DOWNTO 0) ) ;
END prob7 14 ;

ARCHITECTURE Behavior OF prob7 14 IS

BEGIN
PROCESS ( Clock )
BEGIN
WAIT UNTIL Clock’EVENT AND Clock = ’1’ ;
IF L = ’1’ THEN
Q <= R ;
ELSE
CASE Shift IS
WHEN ”10” => Q <= ”00” & Q(3 DOWNTO 2) ;
WHEN ”01” => Q <= ”0” & Q(3 DOWNTO 1) ;
WHEN OTHERS => Q <= Q ;
END CASE ;
END IF ;
END PROCESS ;
END Behavior ;

7-5
7.15. Enable

0
D0
T Q Q0
1

D1 0
T Q Q1
1

D2 0
T Q Q2
1

0
D3
T Q Q3
1

Output
carry
Load
Clock

7.16. Up/down

1 T Q 0 T Q 0 T Q
Q0 Q1 Q2
1 1
Clock Q Q Q

7-6
7.17.

Up/down

0 0
D Q Q D Q D Q
0 Q1 Q2
1 1
Clock Q Q Q

7.18. The counting sequence is 000; 001; 010; 111.

7.19. The circuit in Figure P7.4 is a master-slave JK flip-flop. It suffers from a problem sometimes called ones-
catching. Consider the situation where the Q output is low, Clock = 0, and J = K = 0. Now let Clock
remain stable at 0 while J change from 0 to 1 and then back to 0. The master stage is now set to 1 and this
value will be incorrectly transferred into the slave stage when the clock changes to 1.

7.20. Repeated application of DeMorgan’s theorem can be used to change the positive-edge triggered D flip-flop
in Figure 7.11 into the negative-edge D triggered flip-flop:

Clock

7-7
7.21. LIBRARY ieee ;
USE ieee.std logic 1164.all ;
USE ieee.std logic unsigned.all ;

ENTITY prob7 21 IS
PORT ( R : IN STD LOGIC VECTOR(23 DOWNTO 0) ;
Clock, Resetn, L, U : IN STD LOGIC ;
Q : BUFFER STD LOGIC VECTOR(23 DOWNTO 0) ) ;
END prob7 21 ;

ARCHITECTURE Behavior OF prob7 21 IS

BEGIN
PROCESS ( Clock, Resetn )
BEGIN
IF Resetn = ’0’ THEN
Q <= (OTHERS => ’0’) ;
ELSIF Clock’EVENT AND Clock = ’1’ THEN
IF L = ’1’ THEN
Q <= R ;
ELSIF U = ’1’ THEN
Q <= Q+1 ;
ELSE
Q <= Q,1 ;
END IF ;
END IF ;
END PROCESS ;
END Behavior ;

7.22. LIBRARY ieee ;

USE ieee.std logic 1164.all ;
USE ieee.std logic unsigned.all ;

ENTITY prob7 22 IS
GENERIC ( N : INTEGER := 4 ) ;
PORT ( Clock, Resetn, E : IN STD LOGIC ;
Q : OUT STD LOGIC VECTOR ( N,1 DOWNTO 0) ) ;
END prob7 22 ;

ARCHITECTURE Behavior OF prob7 22 IS

SIGNAL Count : STD LOGIC VECTOR ( N,1 DOWNTO 0 ) ;
BEGIN
PROCESS ( Clock, Resetn )
BEGIN
IF Resetn = ’0’ THEN
Count <= (OTHERS => ’0’) ;

: : : con’t

7-8
 ELSIF Clock’EVENT AND Clock = ’1’ THEN
IF E = ’1’ THEN
Count <= Count + 1 ;
ELSE
Count <= Count ;
END IF ;
END IF ;
END PROCESS ;
Q <= Count ;
END Behavior ;

7.23. LIBRARY ieee ;

USE ieee.std logic 1164.all ;

ENTITY prob7 23 IS
PORT ( R : IN INTEGER RANGE 0 TO 11 ;
Clock, Resetn, L : IN STD LOGIC ;
Q : BUFFER INTEGER RANGE 0 TO 11 ) ;
END prob7 23 ;

ARCHITECTURE Behavior OF prob7 23 IS

BEGIN
PROCESS ( Clock, Resetn )
BEGIN
IF Resetn = ’0’ THEN
Q <= 0 ;
ELSIF Clock’EVENT AND Clock = ’1’ THEN
IF L = ’1’ THEN
Q <= R ;
ELSE
IF Q = 11 THEN
Q <= 0 ;
ELSE
Q <= Q + 1 ;
END IF ;
END IF ;
END IF ;
END PROCESS ;
END Behavior ;

7.24. The longest delay in the circuit is the from the output of FF0 to the input of FF3 . This delay totals 5 ns. Thus
the minimum period for which the circuit will operate reliably is

Tmin = 5 ns + tsu = 8 ns
The maximum frequency is
Fmax = 1=Tmin = 125 MHz

7-9
7.25. LIBRARY ieee ;
USE ieee.std logic 1164.all ;

ENTITY prob7 25 IS
PORT ( Clock, Clear : IN STD LOGIC ;
BCD0, BCD1 : BUFFER STD LOGIC VECTOR(3 DOWNTO 0) ) ;
END prob7 25 ;

ARCHITECTURE Structure OF prob7 25 IS

COMPONENT fig7 25
PORT ( D : IN STD LOGIC VECTOR(3 DOWNTO 0) ;
Clock, Enable, Load : IN STD LOGIC ;
Q : BUFFER STD LOGIC VECTOR(3 DOWNTO 0) ) ;
END COMPONENT ;
SIGNAL Load0, Load1 : STD LOGIC ;
SIGNAL Enab0, Enab1 : STD LOGIC ;
SIGNAL Zero : STD LOGIC VECTOR(3 DOWNTO 0) ;
BEGIN
Zero <= ”0000” ;
Enab0 <= ’1’ ;
Enab1 <= BCD0(0) AND BCD0(3) ;

Load0 <= Enab1 OR Clear ;

Load1 <= (BCD1(0) AND BCD1(3)) OR Clear ;

cnt0: fig7 25 PORT MAP ( Clock => Clock, Load => Load0, Enable => Enab0,
D => Zero, Q => BCD0 ) ;
cnt1: fig7 25 PORT MAP ( Clock => Clock, Load => Load1, Enable => Enab1,
D => Zero, Q => BCD1 ) ;
END Structure ;

7.26. LIBRARY ieee ;

USE ieee.std logic 1164.all ;

ENTITY prob7 26 IS
PORT ( Clock, Resetn : IN STD LOGIC ;
Q : BUFFER STD LOGIC VECTOR(0 TO 7) ) ;
END prob7 26 ;

ARCHITECTURE Behavior OF prob7 26 IS

BEGIN
PROCESS ( Clock, Resetn )
BEGIN
IF Resetn = ’0’ THEN
Q <= ”00000000” ;
ELSIF Clock’EVENT AND Clock = ’1’ THEN
Q <= (NOT Q(7)) & Q(0 TO 6) ;
END IF ;
END PROCESS ;
END Behavior ;

7-10
7.27. LIBRARY ieee ;
USE ieee.std logic 1164.all ;

ENTITY prob7 27 IS
GENERIC ( N : INTEGER := 8 ) ;
PORT ( Clock, Start : IN STD LOGIC ;
Q : BUFFER STD LOGIC VECTOR(0 TO N,1) ) ;
END prob7 27 ;

ARCHITECTURE Behavior OF prob7 27 IS

BEGIN
PROCESS ( Clock, Start )
BEGIN
IF Start = ’1’ THEN
Q <= (OTHERS => ’0’) ;
Q(0) <= ’1’ ;
ELSIF Clock’EVENT AND Clock = ’1’ THEN
GenBits: FOR i IN 1 TO N,1 LOOP
Q(i) <= Q(i,1) ;
END LOOP ;
Q(0) <= Q(N,1) ;
END IF ;
END PROCESS ;
END Behavior ;

7.28. LIBRARY ieee ;

USE ieee.std logic 1164.all ;
USE ieee.std logic unsigned.all ;

ENTITY prob7 28 IS
PORT ( Clock, Reset : IN STD LOGIC ;
Data : IN STD LOGIC VECTOR(3 DOWNTO 0) ;
Q : BUFFER STD LOGIC VECTOR(3 DOWNTO 0) ) ;
END prob7 28;

ARCHITECTURE Behavior OF prob7 28 IS

BEGIN
PROCESS ( Clock, Reset )
BEGIN
IF Reset = ’1’ THEN
Q <= ”0000” ;
ELSIF Clock’EVENT AND Clock = ’1’ THEN
Q <= Q + Data ;
END IF ;
END PROCESS ;
END Behavior ;

7-11
7.29. LIBRARY ieee ;
USE ieee.std logic 1164.all ;
LIBRARY lpm ;
USE lpm.lpm components.all ;

ENTITY prob7 29 IS
PORT ( Clock, Reset : IN STD LOGIC ;
Q : OUT STD LOGIC VECTOR(31 DOWNTO 0) ) ;
END prob7 29 ;

ARCHITECTURE Structural OF prob7 29 IS

BEGIN
cnt: lpm counter
GENERIC MAP ( lpm width => 32 )
PORT MAP ( clock => Clock, aclr => Reset, q => Q ) ;
END Structural ;

7.33. T1 T2 T3
(Swap): I4 Rout = X , Tin Rout = Y , Rin = X Tout , Rin = Y ,
Done

Since the processor now has five operations a 3-to-8 decoder is needed to decode the signals f2 ; f1; f0 . The
SWAP operation is represented by the code

I4 = f2f 1 f 0
New expressions are needed for Rin and Rout to accommodate the SWAP operation:

Rkin = I I
T1
Xk + (I2 + I3 )
T3
Xk + I4
T2
Xk + I4
T3
Yk
( 0 + 1)
Rkout = I1
T1
Yk + (I2 + I3 )
(T1 Xk + T2 Yk ) + I4
T1 Xk + I4
T2 Yk

The control signals for the temporary register, T , are

Tin = T1I4
Tout = T3I4

7.34. (a) Period = 2  n  tp

(b)
Reset Reset
Interval E Counter
Ring Osc

Count

The counter tallies the number of pulses in the 100 ns time period. Thus

tp = 2  Count
100 ns
n

7-12
7.35. D
Q

Clock

Clock 1
0

D 1
0

A 1
0

Q 1
0

7.36.
Start Reset
3-bit counter
Clock

f g

7-13