7

1-Encoder and Decoder

1.1 Encoder

An encoder is a digital circuit that performs the inverse of a decoder, the

encoder has 2n (or less) input lines and n output lines, the output lines generate
the binary code corresponding to the input value. Some attributes of encoder
can list below

•An encoder accepts an active level on one of its inputs, representing digit,
such as a decimal or octal digits, and converts it to a coded output such as
BCD or binary.

•Encoders can also be devised to encode various symbols and alphabetic

characters.

•The process of converting from familiar symbols or numbers to a coded

format is called encoding.

•Most decoders accept an input code and produce a HIGH or a LOW at one
and only one output line. In other worlds, a decoder identifies, recognizes, or
detects a particular code. The opposite of this decoding process is called
encoding and is performed by a logic circuit called an encoder.

•An encoder has a number of input lines, only one of which input is activated
at a given time and produces an N-bit output code, depending on which input
is activated.
 Table 1- truth table of 8-line-to-3-line encoder

I0 I1 I2 I3 I4 I5 I6 I7 Y I Y1 Y Decimal
0
2 0
Digit

1 0 0 0 0 0 0 0 0 0 0 0

0 1 0 0 0 0 0 0 0 0 1 1

0 0 1 0 0 0 0 0 0 1 0 2

0 0 0 1 0 0 0 0 0 1 1 3

0 0 0 0 1 0 0 0 1 0 0 4

0 0 0 0 0 1 0 0 1 0 1 5

0 0 0 0 0 0 1 0 1 1 0 6

0 0 0 0 0 0 0 1 1 1 1 7

For an 8-to-3 binary encoder with inputs I0-I7 the logic expressions of the outputs Y0-Y2
are:

Y0 = I1 + I3 + I5 + I7
Yo 0
Y1 = I2 + I3 + I6 + I7
Y2 = I4 + I5 + I6 + I7

10
Y
8 3 93 o
-

Encoder
I
8-line-to-3-line encoder
1

16 4
BE
Iis Eng
 1.2 Decoder
In order to decode all possible combinations of three bits, eight (23 = 8) decoding
logic gates are required. This type of decoder is called the 3-line-to-8-line
decoder because they are 3 inputs and 8 outputs. Let us consider the design of such
a decoder and assume that we require ACTIVE HIGH outputs. That is, for a given
input combination the decoder outputs ‘1’. To illustrate let's consider Table-2 which
list the decoding functions and truth tables for the 3-line-to-8-line decoder.

Table 2-truth table 3-line-to-8-line decoder

Decimal Binary Logic Outputs

Digit Inputs Function D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 0 1 0 0 0 0 0 0 0
⑧
1 0 0 1 0 1 0 0 0 0 0 0

2 0 1 0 0 0 1 0 0 0 0 0

3 0 1 1 0 0 0 1 0 0 0 0

4 1 0 0 0 0 0 0 1 0 0 0

5 1 0 1 0 0 0 0 0 1 0 0

231
6 1 1 0 0 0 0 0 0 0 1 0

7 1 1 1 0 0 0 0 0 0 0 1

0 11 0

xox 0
Ao
A

Az

3-line-to-8-line decoder
Example
1- By using Decoder, design and implement a full adder that satisfy condition below

Solution

equation for sum S = ab’c’ + a’b’c + a’bc’ + abc = Σ(1,2,4,7)

= abc +a’bc +ab’c+abc’= Σ (3, 5, 6, 7)
So we can implement it from decoder using OR gates as follow:
H.W -1
r
How can I implement a full subtractor using a 3x8 decoder.?
(
you

2- Multiplexer and De-Multiplexer

2.1 The Multiplexer (MUX)

The multiplexer, shortened to “MUX” or “MPX”, is a combinational logic circuit designed to
switch one of several input lines through to a single common output line by the application of a
control signal. Multiplexers operate like very fast acting multiple position rotary switches
connecting or controlling multiple input lines called “channels” one at a time to the output.

Multiplexers, or MUX’s, can be either digital circuits made from high speed logic gates used to
switch digital or binary data or they can be analogue types using transistors, MOSFET’s or relays
to switch one of the voltage or current inputs through to a single output.

The most basic type of multiplexer device is that of a one-way rotary switch as shown.

The rotary switch, also called a wafer switch as each layer of the switch is known as a wafer, is a
mechanical device whose input is selected by rotating a shaft. In other words, the rotary switch is
a manual switch that you can use to select individual data or signal lines simply by turning its inputs
“ON” or “OFF”. So how can we select each data input automatically using a digital device. In
digital electronics, multiplexers are also known as data selectors because they can “select” each
input line, are constructed from individual Analogue Switches encased in a single IC package as
opposed to the “mechanical” type selectors such as normal conventional switches and relays.

They are used as one method of reducing the number of logic gates required in a circuit design or
when a single data line or data bus is required to carry two or more different digital signals. For
example, a single 8-channel multiplexer.
Generally, the selection of each input line in a multiplexer is controlled by an additional set of
inputs called control lines and according to the binary condition of these control inputs, either
“HIGH” or “LOW” the appropriate data input is connected directly to the output. Normally, a
multiplexer has an even number of 2N data input lines and a number of “control” inputs that
correspond with the number of data inputs.

Note that multiplexers are different in operation to Encoders. Encoders are able to switch an n-bit
input pattern to multiple output lines that represent the binary coded (BCD) output equivalent of
the active input.

We can build a simple 2-line to 1-line (2-to-1) multiplexer from basic logic gates as shown.

Basic Concept of 2-to-1 Channel Multiplexer

In the case of a 2-to-1 multiplexer, a logic value of 0 would connect A to the output while a logic
value of 1 would connect B to the output. In larger multiplexers, the number of selector pins is
equal to (log2 n) where n is the number of inputs.

Data
a Output
0 A
1 B

O/P=Aa+Ba

4 Channel Multiplexer using Logic Gates

-
-

-
-

u
 O/P
b a "Q"
0 0 A
0 1 B I as
1 0 C
A_ 1 1 D 1
-

The Boolean expression for this 4-to-1 Multiplexer above with inputs A to D and data
a's select lines a, b is given as:

Q = abA + abB + abC + abD

4
I t To

Adding more control address lines will allow the multiplexer to control more inputs but
each control line configuration will connect only ONE input to the output.
The symbol used in logic diagrams to identify a multiplexer is as follows.

The De-Multiplexer
The data distributor, known more commonly as a Demultiplexer or “Demux” for short, is the exact
opposite of the Multiplexer we saw in the previous part. The demultiplexer takes one single input
data line and then switches it to any one of a number of individual output lines one at a time.
The demultiplexer converts a serial data signal at the input to a parallel data at its output lines as
shown below.

1-to-4 Channel De-multiplexer

Output Select Data Output

b a Selected

0 0 A
 0 1 B

1 0 C

1 1 D

The Boolean expression for this 1-to-4 Demultiplexer above with outputs A to D and data
select lines a, b is given as:

F = abF + abB + abC + abD

F F F
B C I
A

b a
A
I B

abf
=

Demultiplexer Output Line Selection

b
Some standarda demultiplexer IC´s also have an additional “enable output” pin which
disables or prevents the input from being passed to the selected output. The symbol used
in logic diagrams to identify a demultiplexer is as follows.
 f
O
1-Practical Example: - D
e
4 x 1 MUX data selector.

D MUX
5 so
I MUX 1 4
441

1- Construct 4 x1 multiplexer using 2x 1 multiplexer

5,5 8
11
Example. 1

Construct 8 x1 using 2 blocks of 4x1 and one block 2x1.

l

Minx mix 8 1 Dini only 2 1 D Mux

 Solution
So

i ~

so S

Example.2 Implement the following function using 8:1 MUX: f (A, B, C, D) =

m (0, 2, 4, 6, 8, 10, 12, 14)

Solution.
The truth table of the function is shown in Fig below. List the input of the
multiplexer and under then list all the minterms in two rows. The first row lists all
those minterms where “A” is complement, and second row all the minterms
with “A” uncomplemented, as shown in Fig below. Below Circle all the
minterms of the function and inspect each column separately as follows:
 A

log
I IEEE
1

9010
...
2340560

0.10
13
IF
is
0
A

Logico
I
ABCI

B
-

Example.3 Implement f (a,b,c,d) =∑ 𝑚(0,1,5,6,7,9,10,15) by using 8x1

multiplexer and a,b,c as a select line .

construct the following function

by using 5 1
D Max
 I

E 61,567.910,5
Solution

idomee
[ 0, 1, 5, 6, 7, 9, 10,15)

d d

D0 0 1 1

D1 2 3 0 ao .ie

D2 4 5 d

D3 6 7 1

D4 8 9 d

D5 10 11 d
D6 12 13 0

D7 14 15 d

H.W

1- Construct 8 x 1 multiplexer by using 2 x 1 multiplexer

2- Implement 1 x 8 De-multiplexer using only 2 of 1 x 4 De-multiplexer
3- Implement f (a,b,c,d) =∑ 𝑚(0,1,5,6,7,9,10,15) by using 4 multiplexer and a,b
as a select line .

8 4

EE
2

14 Iff
2 2 1
I
2
 2 150
000 8 4 8 2

Solution

d d

D0 0 1 1

D1 2 3 0

D2 4 5 d

D3 6 7 1

D4 8 9 d

D5 10 11 d
D6 12 13 0

D7 14 15 d

H.W

1- Construct 8 x 1 multiplexer by using 2 x 1 multiplexer

2- Implement 1 x 8 De-multiplexer using only 2 of 1 x 4 De-multiplexer
3- Implement f (a,b,c,d) =∑ 𝑚(0,1,5,6,7,9,10,15) by using 4 multiplexer and a,b
as a select line .
Design AND gate using MUX

Do A B AND
D
D AND
D

Log c 1A B