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The document contains various Verilog HDL programs including a factorial calculator, an 8-bit ALU, an even parity checker for 16-bit numbers, and a CMOS-based XOR gate. Each section includes the program code, test benches, and timing diagrams for simulation. The document serves as an assignment for a course on digital design and hardware description languages.

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3 views11 pages

Assign 5

The document contains various Verilog HDL programs including a factorial calculator, an 8-bit ALU, an even parity checker for 16-bit numbers, and a CMOS-based XOR gate. Each section includes the program code, test benches, and timing diagrams for simulation. The document serves as an assignment for a course on digital design and hardware description languages.

Uploaded by

madhankumars2362004
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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19ECE41-VERILOG HDL S SRIDHARAN

DATE: ASSIGNMENT- 71762204125

1.FACTORIAL

PROGRAM:

module Factorial4bitin_32bitout(
input [3:0] num,
output reg [31:0] result
);
always @(*) begin
case (num)
4'd0: result = 32'd1;
4'd1: result = 32'd1;
4'd2: result = 32'd2;
4'd3: result = 32'd6;
4'd4: result = 32'd24;
4'd5: result = 32'd120;
4'd6: result = 32'd720;
4'd7: result = 32'd5040;
4'd8: result = 32'd40320;
4'd9: result = 32'd362880;
4'd10: result = 32'd3628800;
4'd11: result = 32'd39916800;
4'd12: result = 32'd479001600;
4'd13: result = 32'd6227020800;
4'd14: result = 32'd87178291200;
4'd15: result = 32'd1307674368000;
default: result = 32'd0;
endcase
end
endmodule
RTL SCHEMATIC:

TEST BENCH

initial begin
$display("num\tfactorial");
num = 0; #10 $display("%d\t%d", num, result);
num = 1; #10 $display("%d\t%d", num, result);
num = 2; #10 $display("%d\t%d", num, result);
num = 3; #10 $display("%d\t%d", num, result);
num = 4; #10 $display("%d\t%d", num, result);
num = 5; #10 $display("%d\t%d", num, result);
num = 6; #10 $display("%d\t%d", num, result);
num = 7; #10 $display("%d\t%d", num, result);
num = 8; #10 $display("%d\t%d", num, result);
num = 9; #10 $display("%d\t%d", num, result);
num = 10;#10 $display("%d\t%d", num, result);
$finish;
end
endmodule
TIMING DIAGRAM:
2.8 Bit ALU

PROGRAM:

module ALU8bit(
input [3:0] a, b,
input [2:0] sel,
output reg [4:0] out
);

always @(*) begin


case (sel)
3'b000: out = a; // pass a
3'b001: out = a + b; // a + b
3'b010: out = a - b; // a - b
3'b011: out = b != 0 ? a / b : 5'd0; // a / b (prevent divide by 0)
3'b100: out = b != 0 ? a % b : 5'd0; // a % b (prevent mod by 0)
3'b101: out = a << 1; // a << 1
3'b110: out = a >> 1; // a >> 1
3'b111: out = (a > b) ? 5'd1 : 5'd0; // a > b (comparison)
default: out = 5'd0;
endcase
end
endmodule
RTEST BENCH:

initial begin

$display("sel\ta\tb\tout");

a = 4'd10; b = 4'd2;

sel = 3'b000; #10 $display("%b\t%d\t%d\t%d", sel, a, b, out); // a

sel = 3'b001; #10 $display("%b\t%d\t%d\t%d", sel, a, b, out); // a + b

sel = 3'b010; #10 $display("%b\t%d\t%d\t%d", sel, a, b, out); // a - b

sel = 3'b011; #10 $display("%b\t%d\t%d\t%d", sel, a, b, out); // a / b


sel = 3'b100; #10 $display("%b\t%d\t%d\t%d", sel, a, b, out); // a % b

sel = 3'b101; #10 $display("%b\t%d\t%d\t%d", sel, a, b, out); // a << 1

sel = 3'b110; #10 $display("%b\t%d\t%d\t%d", sel, a, b, out); // a >> 1

sel = 3'b111; #10 $display("%b\t%d\t%d\t%d", sel, a, b, out); // a > b

$finish;

end

end module
RTL SCHEMATIC:

TIMING DIAGRAM:
3. EvenParity-16BitNumber

PROGRAM:

module EvenParity_16bit(
input clk,
input start,
input [15:0] data,
output reg parity
);

reg [15:0] temp_data;


reg [3:0] count;
reg compute;

task compute_parity;
input [15:0] in_data;
output reg result;
integer i;
begin
result = 0;
for (i = 0; i < 16; i = i + 1) begin
result = result ^ in_data[i];
end
result = ~result;
end
endtask

always @(posedge clk) begin


if (start) begin
temp_data <= data;
count <= 3;
compute <= 1;
end else if (compute) begin
if (count > 0)
count <= count - 1;
else begin
compute_parity(temp_data, parity);
compute <= 0;
end
end
end
endmodule

RTL SCHEMATIC:

TEST BENCH:

// Clock generation

always #5 clk = ~clk;

initial begin

clk = 0;

start = 0;

data = 16'b0;

#10;

data = 16'b1010_1010_1010_1010; // even number of 1s -> parity = 1

start = 1; #10;

start = 0;
#40; // Wait for 3 posedges

$display("Data: %b, Even Parity: %b", data, parity);

data = 16'b1111_0000_0000_1110; // odd number of 1s -> parity = 0

start = 1; #10;

start = 0;

#40;

$display("Data: %b, Even Parity: %b", data, parity);

$finish;

end

endmodule

TIMING DIAGRAM:
4.XOR_Using Cmos

PROGRAM:

(i)
module XOR_Gate(
output Y,
input A, B
);
wire notA, notB;
wire n1, n2;
not (notA, A);
not (notB, B);
cmos #(4) (n1, A, notB, B);
cmos #(4) (n2, notA, B, notB);
or (Y, n1, n2);
endmodule

(ii)
module switch_delays;

wire out_pmos, out_nmos, out_cmos, out_tranif1, out_tranif0;


reg data, ctrl;
assign #2 out_pmos = (ctrl) ? data : 1'bz; // PMOS model with delay
assign #4 out_nmos = (ctrl) ? data : 1'bz; // NMOS model with rise delay
assign #6 out_nmos = (ctrl) ? 1'bz : data; // NMOS fall delay
assign #5 out_nmos = (ctrl) ? 1'bz : 1'b0; // NMOS turn-off delay
assign #6 out_cmos = (ctrl) ? data : 1'bz; // CMOS model with delay
assign #5 out_tranif1 = (ctrl) ? data : 1'bz; // tranif1 turn-on delay
assign #6 out_tranif1 = (ctrl) ? 1'bz : data; // tranif1 turn-off delay
assign #3 out_tranif0 = (ctrl) ? 1'bz : data; // tranif0 model with delay
initial begin
data = 0; ctrl = 0; #10;
data = 1; ctrl = 1; #10;
data = 0; ctrl = 1; #10;
data = 1; ctrl = 0; #10;

$finish;
end

initial begin
$monitor("time=%0t | data=%b ctrl=%b | pmos=%b nmos=%b cmos=%b tranif1=%b tranif0=%b",
$time, data, ctrl, out_pmos, out_nmos, out_cmos, out_tranif1, out_tranif0);
end

endmodule
CMOS DESIGN:

TEST BENCH

module tb_switch_delays;
wire out_pmos, out_nmos, out_cmos, out_tranif1, out_tranif0;
reg data, ctrl;
switch_delays uut (
.out_pmos(out_pmos),
.out_nmos(out_nmos),
.out_cmos(out_cmos),
.out_tranif1(out_tranif1),
.out_tranif0(out_tranif0),
.data(data),
.ctrl(ctrl)
);

initial begin
$display("time=%0t | data=%b ctrl=%b | pmos=%b nmos=%b cmos=%b tranif1=%b tranif0=%b",
$time, data, ctrl, out_pmos, out_nmos, out_cmos, out_tranif1, out_tranif0);
data = 0; ctrl = 0; #10;
data = 1; ctrl = 1; #10;
data = 0; ctrl = 1; #10;
data = 1; ctrl = 0; #10;

$finish;
end
endmodule

TIMING DIAGRAM:

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