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DLD Lab

This document is a lab report for the Digital Logic Design LAB course at Comilla University, detailing various experiments conducted by the student Parvez Hossain. The report includes a list of experiments with their corresponding page numbers, covering topics such as gate implementations, function implementations using different methods, and the design of decoders and multiplexers. The report is submitted to Assistant Professor Md. Faisal Bin Abdul Aziz with a submission date of December 10, 2024.

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Parvez Hossain
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3 views2 pages

DLD Lab

This document is a lab report for the Digital Logic Design LAB course at Comilla University, detailing various experiments conducted by the student Parvez Hossain. The report includes a list of experiments with their corresponding page numbers, covering topics such as gate implementations, function implementations using different methods, and the design of decoders and multiplexers. The report is submitted to Assistant Professor Md. Faisal Bin Abdul Aziz with a submission date of December 10, 2024.

Uploaded by

Parvez Hossain
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Comilla University

A Lab Report on
Digital Logic Design LAB
Course Code: CSE-2106

Course Tittle: Digital Logic Design LAB


Department of CSE, CoU

Submitted To:
Md. Faisal Bin Abdul Aziz Submitted By:
Assistant Professor Parvez Hossain
ID:12208022
Department of CSE,
Comilla University

Submission Date: 10 December


2024
LIST OF EXPERIMENTS

S.NO NAME OF THE EXPERIMENT PAGE NO.

01 AND,OR,NOT gates implementation 01-04


02 F=x+xy implementation 04-07
03 F=A+B’C implementation using sum of minturm 07-11
04 F=xy+x’y implement using product of maxterms 11-15
05 F(x,y,z)= ∑(0,6) implementation using NAND 15-21
gate
06 F=A’B’C’+B’CD’+A’BCD’+AB’C’ 21-25
implementation using k map
07 F(w,x,y,z)= ∑(1,3,7,11,15) implementation using 25-28
don’t care method d(w,x,y,z)= ∑(0,2,5)
08 F(w,x,y,z)= ∑(1,4,6,7,8,9,10,11,15) 29-32
implementation using tabulation method
09 Half Adder implementation using XOR gate 32-34

10 Design a 3 to 8 line decoder 34-37

11 Design a 4 to 1 Multiplexer 38-39

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