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2c Structural Modelling Vhdl Example

The lecture discusses structural VHDL modeling, focusing on the implementation of modules as compositions of subsystems, including signal declarations, component instances, and port maps. It provides examples of structural and mixed behavioral-structural modeling, illustrating how to declare entities and architectures for components like D-latches and multipliers. Additionally, resources for further learning are provided, including tutorials and guidelines for VHDL synthesis.

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Fana Admasu
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4 views

2c Structural Modelling Vhdl Example

The lecture discusses structural VHDL modeling, focusing on the implementation of modules as compositions of subsystems, including signal declarations, component instances, and port maps. It provides examples of structural and mixed behavioral-structural modeling, illustrating how to declare entities and architectures for components like D-latches and multipliers. Additionally, resources for further learning are provided, including tutorials and guidelines for VHDL synthesis.

Uploaded by

Fana Admasu
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 15

© Ahmad El-Banna

Benha University
Faculty of Engineering at Shoubra

ECE-322
Electronic Circuits (B)

Lecture #12

Spring 2015
Structural VHDL Modeling

Instructor:
Dr. Ahmad El-Banna
Elec. Cts B, Lec#12 , Spring 2015 © Ahmad El-Banna
Agenda

Modeling the Structure way

Structural Example

Behavioral & Structural Example


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Elec. Cts B, Lec#12 , Spring 2015 © Ahmad El-Banna
Modeling the Structurural way
• Structural architecture
• implements the module as a composition of subsystems
• contains
• signal declarations, for internal interconnections
• the entity ports are also treated as signals
• component instances
• instances of previously declared entity/architecture pairs
• port maps in component instances
• connect signals to component ports

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Elec. Cts B, Lec#12 , Spring 2015 © Ahmad El-Banna
Structural way Example
Not complete example, just for concept justification ..

4
Elec. Cts B, Lec#12 , Spring 2015 © Ahmad El-Banna
Structural way..
• First declare D-latch and and-gate entities and architectures

entity d_latch is entity and2 is


port ( d, clk : in bit; q : out bit ); port ( a, b : in bit; y : out bit );
end entity d_latch; end entity and2;

architecture basic of d_latch is architecture basic of and2 is


begin begin
process (clk, d) process (a, b)
begin begin
if clk = ‘1’ then y <= a and b after 2 ns;
q <= d after 2 ns; end process ;
end if; end basic;
end process;
end basic;
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Elec. Cts B, Lec#12 , Spring 2015 © Ahmad El-Banna
Structural way...
• Declare corresponding components in register architecture body

architecture struct of reg4 is


component d_latch
port ( d, clk : in bit; q : out bit );
end component;
component and2
port ( a, b : in bit; y : out bit );
end component;
signal int_clk : bit;
...

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Elec. Cts B, Lec#12 , Spring 2015 © Ahmad El-Banna
Structural way....
• Now use them to implement the register

...
begin
bit0 : d_latch
port map ( d0, int_clk, q0 );
bit1 : d_latch
port map ( d1, int_clk, q1 );
bit2 : d_latch
port map ( d2, int_clk, q2 );
bit3 : d_latch
port map ( d3, int_clk, q3 );
gate : and2
port map ( en, clk, int_clk );
end struct; 7
Trace the code & Draw the model structure

Elec. Cts B, Lec#12 , Spring 2015 © Ahmad El-Banna


structure..
Trace the code &
Draw the model

Elec. Cts B, Lec#12 , Spring 2015 © Ahmad El-Banna


Elec. Cts B, Lec#12 , Spring 2015 © Ahmad El-Banna
Trace the code & Draw the model structure..

• the model

• Simulation waveform

10
Elec. Cts B, Lec#12 , Spring 2015 © Ahmad El-Banna
Mixed Behavior and Structure
• An architecture can contain both behavioral and structural
parts
• process statements and component instances
• collectively called concurrent statements
• processes can read and assign to signals
• Example: register-transfer-level (RTL) Model
• data path described structurally
• control section described behaviorally

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Elec. Cts B, Lec#12 , Spring 2015 © Ahmad El-Banna
Mixed Example
Not complete example, just for concept justification ..

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Elec. Cts B, Lec#12 , Spring 2015 © Ahmad El-Banna
Mixed Example
entity multiplier is
port ( clk, reset : in bit;
multiplicand, multiplier : in integer;
product : out integer );
end multiplier;

architecture mixed of mulitplier is


signal partial_product, full_product : integer;
signal arith_control, result_en, mult_bit, mult_load : bit;
begin
arith_unit : entity work.shift_adder(behavior)
port map ( addend => multiplicand, augend => full_product,
sum => partial_product,
add_control => arith_control );
result : entity work.reg(behavior)
port map ( d => partial_product, q => full_product, 13
en => result_en, reset => reset );
...
Elec. Cts B, Lec#12 , Spring 2015 © Ahmad El-Banna
Mixed Example..
…
multiplier_sr : entity work.shift_reg(behavior)
port map ( d => multiplier, q => mult_bit,
load => mult_load, clk => clk );
product <= full_product;
process (clk, reset)
-- variable declarations for control_section
-- …
begin
-- sequential statements to assign values to control signals
-- …
end process;
end mixed;

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Elec. Cts B, Lec#12 , Spring 2015© Ahmad El-Banna
• For more details, refer to:
• VHDL Tutorial: Learn by Example by Weijun Zhang
• http://esd.cs.ucr.edu/labs/tutorial/
• VHDL GUIDELINES FOR SYNTHESIS
• http://www.utdallas.edu/~zxb107020/EE6306/Tutorial/VHDL.pdf
• “Introduction to VHDL” presentation by Dr. Adnan Shaout, The
University of Michigan-Dearborn
• The VHDL Cookbook, Peter J. Ashenden, st1 edition, 1990.
• The lecture is available online at:
• http://bu.edu.eg/staff/ahmad.elbanna-courses/12135
• For inquires, send to:
• [email protected]
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