University of British Columbia

Electrical and Computer Engineering

Digital Systems and Microcomputers
CPEN312

Lecture 16-17: Stack, Interrupts,

Timers
Dr. Jesús Calviño-Fraga
Department of Electrical and Computer Engineering, UBC
Office: KAIS 3024
E-mail: [email protected]
Phone: (604)-827-5387

April 6, 2022

Copyright © 2009-2022, Jesus Calvino-Fraga. Not to be copied, used, or

revised without explicit written permission from the copyright owner.

Objectives
• Understand and use the 8051 stack.
• Understand and use the ‘lcall’ and ‘ret’
instructions.
• Understand and use the ‘push’ and ‘pop’
instructions.
• Setup and use Interrupts.
• Understand and use Timers/Counters.

Lecture 16-17: Stack, Interrupts, Timers 2

Copyright © 2009-2022, Jesus Calvino-Fraga. Not to be copied, used, or
revised without explicit written permission from the copyright owner.

1
 The 8051 stack ii it
any
e
• We need the stack to use the lcall instruction as well as
interrupts.
s
men
I
• The stack is an area of memory where variables can be
stacked. It is a LIFO memory: the last variable you put in
is the first variable that comes out.
• Special Function Register SP (stack pointer) points to
the beginning of the stack. SP in the 8051 is
incremented before it is used (for push), or used and

i.ciii Iii
them decremented (for pop).
• After reset, SP is set to 07H. If you have variables in
internal RAM, any usage of the stack is likely to corrupt
them. Solution: at the beginning of your program set the
SP special function register so it points to free memory:
mov SP, #7FH ; Set the stack pointer to idata start

Lecture 16-17: Stack, Interrupts, Timers 3

Copyright © 2009-2022, Jesus Calvino-Fraga. Not to be copied, used, or
revised without explicit written permission from the copyright owner.

push

pun

‘lcall’ and ‘ret’ instructions

Pop I
• The ‘lcall’ instructions pushes the address of the
next instruction (16-bit, LSB first) into the stack
and jumps to the address passed as an operand pop x̅
to the ‘lcall’ instruction.
onlytopto
bottom
• The ‘ret’ instruction pops the address stored in
the stack and then jumps to that address.
• The ‘lcall’ can call any address in the 64k code
it filled stack
memory space. Works similarly to ‘ljmp’…
keeppush

Lecture 16-17: Stack, Interrupts, Timers

Copyright © 2009-2022, Jesus Calvino-Fraga. Not to be copied, used, or
revised without explicit written permission from the copyright owner.
4 I
stackoverflow.no

2
 DSO upto F

iiiiimn
i.fif
x Ds6
i
Push and Pop

ii.net • When the microcontroller executes a push into

the stack, it:
a) Increments the SP.
a iÉ5rE b) Saves the value in the internal RAM location
pointed by the SP.
• When the microcontroller executes a pop from
I the stack, it:
a) Retrieves the value from the internal RAM location
pointed by the SP.
no an c b) Decrements the SP.
• The 8051 (as well as most other

it
microprocessors!) have push and pop
o
er instructions.
1.0 itTo Lecture 16-17: Stack, Interrupts, Timers
Copyright © 2009-2022, Jesus Calvino-Fraga. Not to be copied, used, or
revised without explicit written permission from the copyright owner.
5

c.ini
i iiiii
a
lcall example
; Blinky.asm: blinks an LED connected to LEDR0
using2 bond 2no R $MODDE0CV

org 0000H
ljmp myprogram

;The clock in the CV-8052 is 33.3333MHz. (1 cycle=30ns)

WaitHalfSec:
mov R2, #90 Subroutine
L3: mov R1, #250
L2: mov R0, #250
L1: djnz R0, L1 ; 3 machine cycles-> 3*30ns*250=22.5us
djnz R1, L2 ; 22.5us*250=5.625ms
djnz R2, L3 ; 5.625ms*90=0.506s (give or take)
ret
A subroutine (or function) starts with
a label and ends with a ‘ret’ or ‘iret’.
Lecture 16-17: Stack, Interrupts, Timers 6
Copyright © 2009-2022, Jesus Calvino-Fraga. Not to be copied, used, or
revised without explicit written permission from the copyright owner.

3
 lcall example

myprogram:
mov SP, #7FH
; Turn off all LEDs...
mov LEDRA, #0
mov LEDRB, #0 Never jump into
M0:
cpl LEDRA.0
a subroutine!
lcall WaitHalfSec
sjmp M0
END

Lecture 16-17: Stack, Interrupts, Timers 7

Copyright © 2009-2022, Jesus Calvino-Fraga. Not to be copied, used, or
revised without explicit written permission from the copyright owner.

Saving and Restoring Registers to/from

the Stack using push and pop
• Before using the stack (lcall, push, pop) make
sure you set the SP special function register.
• Popular registers to push/pop: ACC, DPL, DPH,
PSW, R0 to R7 (using their addresses: AR0 to
AR7).
• Pop registers from the stack in the REVERSE
order you pushed them! Remember the stack is
a LIFO.

Lecture 16-17: Stack, Interrupts, Timers 8

Copyright © 2009-2022, Jesus Calvino-Fraga. Not to be copied, used, or
revised without explicit written permission from the copyright owner.

4
 Push and Pop Example
WasteTime:
push Acc
push B
push dpl
mov Acc, #100
L3: mov B, #100
L2: mov dpl, #100
L1: djnz dpl, L1
djnz B, L2
djnz Acc, L3
pop dpl
pop B
pop Acc
ret
Lecture 16-17: Stack, Interrupts, Timers 9
Copyright © 2009-2022, Jesus Calvino-Fraga. Not to be copied, used, or
revised without explicit written permission from the copyright owner.

Common bug!
WasteTime:
push B
push Acc
push dpl
mov Acc, #100
L3: mov B, #100
L2: mov dpl, #100
L1: djnz dpl, L1 ; 3 bytes, 2 machine cycles
djnz B, L2
djnz Acc, L3
pop dpl
pop B
pop Acc Where is it?
ret pops are in the
wrong order!

Lecture 16-17: Stack, Interrupts, Timers 10

Copyright © 2009-2022, Jesus Calvino-Fraga. Not to be copied, used, or
revised without explicit written permission from the copyright owner.

5
 Push/Pop for R0 to R7
WaitHalfSec:
push AR0
push AR1
push AR2
mov R2, #20
L3: mov R1, #250
L2: mov R0, #184
L1: djnz R0, L1 ; 2 machine cycles-> 2*0.27126us*184=100us
djnz R1, L2 ; 100us*250=0.025s
djnz R2, L3 ; 0.025s*20=0.5s
pop AR2
pop AR1
pop AR0 The extra ‘A’ is for ‘direct address’ of
ret register R0. This is only required for
registers R0 to R7

Lecture 16-17: Stack, Interrupts, Timers 11

Copyright © 2009-2022, Jesus Calvino-Fraga. Not to be copied, used, or
revised without explicit written permission from the copyright owner.

Interrupts
work along
a Icall
progan to
a predecine
• ‘Interrupts’ are a means of executing subroutines
on automatically without using the ‘lcall’ instruction. The
memory in only difference is that the subroutine that is automatically
called must end with ‘reti’ instead of ‘ret’.
ammechangewaofinter.pl
• Associated with external logic that requires CPU
attention on command.
• Interrupt uses:
– Handshake I/O thus preventing CPU from being tied up.
– Providing a way to handle some errors: illegal opcodes, dividing
by 0, power failure, etc.
– Getting the CPU to perform periodic tasks: generate square
waves, keep time of day, measure frequency, etc.
– Waking up the processor when in low power mode.

Lecture 16-17: Stack, Interrupts, Timers 12

Copyright © 2009-2022, Jesus Calvino-Fraga. Not to be copied, used, or
revised without explicit written permission from the copyright owner.

6
 Interrupts
I “borrowed” this from an old 68HC11
textbook!

Lecture 16-17: Stack, Interrupts, Timers 13

Copyright © 2009-2022, Jesus Calvino-Fraga. Not to be copied, used, or
revised without explicit written permission from the copyright owner.

Interrupts
• Most processors provide a way of enabling /
disabling all maskable interrupts. For the 8051:
clr EA ;Disable interrupts
setb EA ;Enable interrupts
• Some other interrupts are non-maskable and
they MUST be serviced. For example, the X86
has the “Non-Maskable Interrupt” NMI.
• Maskable interrupts can be enabled/disabled
individually. For the 8051 use register IE:

Lecture 16-17: Stack, Interrupts, Timers 14

Copyright © 2009-2022, Jesus Calvino-Fraga. Not to be copied, used, or
revised without explicit written permission from the copyright owner.

7
 IE: INTERRUPT ENABLE REGISTER.
(Address A8H)
EA EC ET2 ES ET1 EX1 ET0 EX0
Bit Name Description
7 EA Interrupt Enable Bit: EA = 1 interrupt(s) can be
serviced, EA = 0 interrupt servicing disabled.
6 BPE Breakpoint Enable bit. (CV-8052)
5 ET2 Timer 2 Interrupt Enable. (8052)
4 ES Serial Port Interrupt Enable
3 ET1 Timer 1 Overflow Interrupt Enable.
2 EX1 External Interrupt 1 Enable.
1 ET0 Timer 0 Overflow Interrupt Enable.
0 EX0 External Interrupt 0 Enable.

Lecture 16-17: Stack, Interrupts, Timers 15

Copyright © 2009-2022, Jesus Calvino-Fraga. Not to be copied, used, or
revised without explicit written permission from the copyright owner.

Interrupt Service Routines (ISR) Vectors

w • The 8051 will lcall to an specific memory location when an interrupt
occurs. They are different for different 8051 variants. For the CV-
8052 this are the interrupts supported and their vector addresses:
use
we
can
Interrupt source Address
External 0 0003H
Timer 0 000BH
External 1 0013H
Timer 1 001BH
Serial port 0023H
Timer 2 002BH

Lecture 16-17: Stack, Interrupts, Timers 16

Copyright © 2009-2022, Jesus Calvino-Fraga. Not to be copied, used, or
revised without explicit written permission from the copyright owner.

8
 Interrupt Service Routines (ISR)
Vectors
• Notice that there are only 8 bytes available between
vectors. Not enough for a decent ISR, but more than
enough for a ljmp instruction!
• IF you enable a particular interrupt, there MUST be an
ISR, or your program WILL crash. A fool proof code
technique is to setup all the ISR vectors and place a reti
(return from interrupt) instruction for those that are not
used (next example).
• In assembly language you can use the “org” directive to
set an ISR vector.
• To return from an ISR use the reti instruction. To return
from a normal routine use the ret instruction.

Lecture 16-17: Stack, Interrupts, Timers 17

Copyright © 2009-2022, Jesus Calvino-Fraga. Not to be copied, used, or
revised without explicit written permission from the copyright owner.

Example 1
; Basic interrupt setup

; We need the register definitions for the 8052:

$MOD52

org 0h
ljmp myprogram

; Interrupt Service Routines (see page 2-12 of MCS-51 bible)

; Notice that there is not much space to put code between
; service routines, but enough to put a ljmp!

; External interrupt 0
org 3h
reti

; Timer 0 interrupt Dummy ISRs

org 0bh
reti
WARNING: org directives must be sequential!
Lecture 16-17: Stack, Interrupts, Timers 18
Copyright © 2009-2022, Jesus Calvino-Fraga. Not to be copied, used, or
revised without explicit written permission from the copyright owner.

9
 Example 1 (cont.)
; External interrupt 1
org 13h
reti

; Timer 1 interrupt
org 1bh
reti

; Serial port interrupt

org 23h Dummy ISRs
reti

; Timer 2 interrupt
org 2bh
reti

; Dummy program, just to compile and see...

myprogram:
mov R1, #00H ; do something
sjmp myprogram
END
Lecture 16-17: Stack, Interrupts, Timers 19
Copyright © 2009-2022, Jesus Calvino-Fraga. Not to be copied, used, or
revised without explicit written permission from the copyright owner.

Example 2: Enable timer 0 interrupt

and setup an ISR
myprogram:
; Enable timer 0
mov a, TMOD
anl a, #0f0H
orl a, #00000010B ; 8-bit auto reload timer (this is in binary)
mov TMOD, a
mov TH0, #080H ; Set the interrupt rate
setb TR0 ; Enable timer 0
setb ET0 ; Enable timer 0 interrupt

setb EA ; Enable all interrupts!

forever:
[...other code here...]
jmp forever

Lecture 16-17: Stack, Interrupts, Timers 20

Copyright © 2009-2022, Jesus Calvino-Fraga. Not to be copied, used, or
revised without explicit written permission from the copyright owner.

10
 Example 2: (cont.) the ISR.

; Timer 0 interrupt
org 0bh
cpl P1.1 ; Check this pin with the scope!
reti

Lecture 16-17: Stack, Interrupts, Timers 21

Copyright © 2009-2022, Jesus Calvino-Fraga. Not to be copied, used, or
revised without explicit written permission from the copyright owner.

Example 2: use a ljmp to go to the

ISR
; Timer 0 interrupt
org 0bh
ljmp timer0_ISR

; Other ISR vectors come here! (Not shown to save space)

; Actual ISR for timer 0.

timer0_ISR:
cpl P1.1
reti

Lecture 16-17: Stack, Interrupts, Timers 22

Copyright © 2009-2022, Jesus Calvino-Fraga. Not to be copied, used, or
revised without explicit written permission from the copyright owner.

11
 Saving and Restoring Registers in
the Stack
• If your ISR routine uses a register, you
must make sure that it will remain
unmodified before returning to the
interrupted program.
• As mentioned before you use the
instructions push/pop to save/restore
registers to/from the stack.
• Additionally, you could use one of four
available register banks in your ISR.
Lecture 16-17: Stack, Interrupts, Timers 23
Copyright © 2009-2022, Jesus Calvino-Fraga. Not to be copied, used, or
revised without explicit written permission from the copyright owner.

8051’s Timers/Counters
• The original 8051 has only two
timers/counters: 0 and 1.
• Newer 8051 microcontrollers usually have:
1. The 8051 timers/counters: timers 0 and 1
2. The 8052 timer/counter: timer 2
3. Additional timers (3, 4, 5, etc.) Not available in
the CV-8052.
4. The Programmable Counter Array (PCA). Not
available in the CV-8052, but very common in
many other processors.
• Let us begin with timers 0 and 1:
Lecture 16-17: Stack, Interrupts, Timers 24
Copyright © 2009-2022, Jesus Calvino-Fraga. Not to be copied, used, or
revised without explicit written permission from the copyright owner.

12
 Timer 0 and Timer 1 Operation Modes
(Section 3-10 of MCS-51 manual)
• Timer 0 and 1 have four modes of operation:
• Mode 0: 13-bit timer/counter (compatible with the 8048
microcontroller, the predecessor of the 8051). Do not
use this mode; use mode 1 instead!
• Mode 1: 16-bit timer/counter.
• Mode 2: 8-bit auto reload timer counter.
• Mode 3: Special mode 8-bit timer/counter (timer 0
only). (I have never used it!)
• Timer 1 can be used as baud rate generator for
the serial port. Some 8051/8052 microcontrollers
have a dedicated baud rate generator.
Lecture 16-17: Stack, Interrupts, Timers 25
Copyright © 2009-2022, Jesus Calvino-Fraga. Not to be copied, used, or
revised without explicit written permission from the copyright owner.

TMOD timer/counter mode control register

(Address 89H)

Timer 1 Timer 0
GATE C/T* M1 M0 GATE C/T* M1 M0

Bit Name Description

Is this SFR bit addressable?

7&3 GATE 1: uses either INT0 or INT1 pins to

enable/disable the timer/counter
6&2 C/T* 0: timer; 1: counter (pins T0 and T1)
All the M1 M0
other
0 0 13-bit timer/counter
pins!
0 1 16-bit timer/counter
1 0 8-bit auto-reload timer/counter
1 1 Special mode
Lecture 16-17: Stack, Interrupts, Timers 26
Copyright © 2009-2022, Jesus Calvino-Fraga. Not to be copied, used, or
revised without explicit written permission from the copyright owner.

13
 TCON: timer/counter control register.
(Address 88H)
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Bit Name Description
7 TF1 Timer 1 overflow flag.
6 TR1 Timer 1 run control.
5 TF0 Timer 0 overflow flag.
4 TR0 Timer 0 run control.
3 IE1 Interrupt 1 flag.
2 IT1 Interrupt 1 type control bit.
1 IE0 Interrupt 0 flag.
0 IT0 Interrupt 0 type control bit.

Lecture 16-17: Stack, Interrupts, Timers 27

Copyright © 2009-2022, Jesus Calvino-Fraga. Not to be copied, used, or
revised without explicit written permission from the copyright owner.

Timer/Counter 0 or 1 in Mode 0

OSC ÷12 Replace ‘x’ with either ‘0’ or ‘1’.

C/T*=0
Interrupt
THx TLx
TFx
(8 bits) (5 bits)
C/T*=1
Tx PIN Overflow
Control

GATE
Do not use this
mode! Use mode
INTx* pin
1 instead.
TRx
Lecture 16-17: Stack, Interrupts, Timers 28
Copyright © 2009-2022, Jesus Calvino-Fraga. Not to be copied, used, or
revised without explicit written permission from the copyright owner.

14
 Timer/Counter 0 or 1 in Mode 1

OSC ÷12 Replace ‘x’ with either ‘0’ or ‘1’.

C/T*=0
Interrupt
THx TLx
TFx
(8 bits) (8 bits)
C/T*=1
Tx PIN Overflow
Control

GATE
Most useful!
INTx* pin

TRx
Lecture 16-17: Stack, Interrupts, Timers 29
Copyright © 2009-2022, Jesus Calvino-Fraga. Not to be copied, used, or
revised without explicit written permission from the copyright owner.

Timer/Counter 0 or 1 in Mode 2

OSC ÷12 Replace ‘x’ with either ‘0’ or ‘1’.

C/T*=0
Overflow Interrupt
TLx
TFx
(8 bits)
C/T*=1
Tx PIN Control

THx
GATE
(8 bits)
INTx* pin

TRx
Lecture 16-17: Stack, Interrupts, Timers 30
Copyright © 2009-2022, Jesus Calvino-Fraga. Not to be copied, used, or
revised without explicit written permission from the copyright owner.

15
 Timer/Counter 0 in Mode 2
myprogram:
; After reset, the stack pointer register is set to 07h
; We may need space for variables, so move the SP
mov SP, #7fH
; Enable timer 0
mov a, TMOD
anl a, #0f0H
orl a, #00000010B ; GATE=0, C/T*=0, M1=1, M0=0: 8-bit auto reload timer
mov TMOD, a
mov TH0, #080H ; Set the interrupt rate
setb TR0 ; Enable timer 0
setb ET0 ; Enable timer 0 interrupt
setb EA
forever:
.
.
. 12
.
Rate = × (100 H − TH 0)
OSC
.
. 12
Rate = × (100 H − 80 H ) = 46.08µ s
jmp forever 33.3333MHz

Lecture 16-17: Stack, Interrupts, Timers 31

Copyright © 2009-2022, Jesus Calvino-Fraga. Not to be copied, used, or
revised without explicit written permission from the copyright owner.

Timer/Counter 2 (Page 3-12 of

MCS51 manual)
• It is a 16-bit timer/counter.
• It has four modes of operation:
– Capture
– Auto-reload
– Baud rate generation
– Programmable clock out (not implemented in
CV-8052)

Lecture 16-17: Stack, Interrupts, Timers 32

Copyright © 2009-2022, Jesus Calvino-Fraga. Not to be copied, used, or
revised without explicit written permission from the copyright owner.

16
 T2CON: timer/counter 2 control register.
(Address C8H)
TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2* CP/RL2*

Bit Name Description

7 TF2 Timer/counter 2 overflow flag.

6 EXF2 Timer/counter 2 external flag.

5 RCLK Receive clock flag.

4 TCLK Transmit clock flag.

3 EXEN2 Timer/Counter 2 external enable.

2 TR2 Start/stop for timer/counter 2.

1 C/T2* Timer or Counter select.

0 CP/RL2* Capture/Reload Flag.

Lecture 16-17: Stack, Interrupts, Timers 33
Copyright © 2009-2022, Jesus Calvino-Fraga. Not to be copied, used, or
revised without explicit written permission from the copyright owner.

Timer/Counter 2 in capture mode

OSC ÷12 Overflow
C/T2*=0

TH2 TL2
TF2
(8 bits) (8 bits)
T2 PIN C/T2*=1
Control
Interrupt
TR2

RCAP2H RCAP2L

T2EX PIN
EXF2

EXEN2
Lecture 16-17: Stack, Interrupts, Timers 34
Copyright © 2009-2022, Jesus Calvino-Fraga. Not to be copied, used, or
revised without explicit written permission from the copyright owner.

17
 Timer/Counter 2 in auto-reload
mode
OSC ÷12 Overflow
C/T2*=0

TH2 TL2
TF2
(8 bits) (8 bits)
T2 PIN C/T2*=1
Control
TR2 Interrupt

RCAP2H RCAP2L

T2EX PIN
EXF2

EXEN2
Lecture 16-17: Stack, Interrupts, Timers 35
Copyright © 2009-2022, Jesus Calvino-Fraga. Not to be copied, used, or
revised without explicit written permission from the copyright owner.

Example: Time Delay Using a Timer

• To use a timer to implement a delay we
need to:
– Initialize the timer: use TMOD SFR.
– Load the timer: use THx and TLx.
– Clear the timer overflow flag: TFx=0;
– Start the timer: Use TRx.
– Check the timer overflow flag: Use TFx.
For the registers above ‘x’ is either
‘0’ for timer 0, or ‘1’ for timer 1.

Lecture 16-17: Stack, Interrupts, Timers 36

Copyright © 2009-2022, Jesus Calvino-Fraga. Not to be copied, used, or
revised without explicit written permission from the copyright owner.

18
 Time Delay Using a Timer
• Implement a 10 ms delay subroutine using
timer 0. Assume the routine will be
running in a CV-8052 soft processor.

First, we have to find the divider (TH0,

TL0) needed for a 10 ms delay…

Lecture 16-17: Stack, Interrupts, Timers 37

Copyright © 2009-2022, Jesus Calvino-Fraga. Not to be copied, used, or
revised without explicit written permission from the copyright owner.

Timer 0 in Mode 1

OSC ÷12 16-bit up counter!

C/T*=0
Interrupt
TH0 TL0
TF0
(8 bits) (8 bits)
C/T*=1
T0 PIN Overflow
Control

Overflow flag TF0

GATE changes to ‘1’ when
counter [TH0,TL0] goes
INT0* pin
from 0xffff to 0x0000

TRx
Lecture 16-17: Stack, Interrupts, Timers 38
Copyright © 2009-2022, Jesus Calvino-Fraga. Not to be copied, used, or
revised without explicit written permission from the copyright owner.

19
 Calculating TH0 and TL0
CLK 33.3333MHz
Rate= 12 = 12
216 − [THn,TLn] 65536 − [THn,TLn]
2.77777MHz 2.77777MHz
[THn,TLn]=65536 − = 65536 − = 37758
Rate (1/10ms)

Maximum delay achievable?

CLK
12 2.777777MHz
Rate= 16
=
2 − [THn,TLn] 65536 − [THn,TLn]
[THn,TLn]=0
2.777777MHz
Rate= = 42.39 Hz → 23.59ms
65536

Lecture 16-17: Stack, Interrupts, Timers 39

Copyright © 2009-2022, Jesus Calvino-Fraga. Not to be copied, used, or
revised without explicit written permission from the copyright owner.

Time Delay Using Timer 0

Wait10ms:
; Initialize the timer
mov a, TMOD
anl a, #11110000B ; Clear bits for timer 0, keep bits for timer 1
orl a, #00000001B ; GATE=0, C/T*=0, M1=0, M0=1: 16-bit timer
mov TMOD, a
clr TR0 ; Disable timer 0
; Load the timer [TH0, TL0]=65536-(2777777/(1/10E-3))
mov TH0, #high(37758)
mov TL0, #low(37758)
clr TF0 ;Clear the timer flag
setb TR0 ; Enable timer 0
Wait10ms_L0:
jnb TF0, Wait10ms_L0 ; Wait for overflow
ret

Lecture 16-17: Stack, Interrupts, Timers 40

Copyright © 2009-2022, Jesus Calvino-Fraga. Not to be copied, used, or
revised without explicit written permission from the copyright owner.

20
 Time Delay Using Timer 0
; Let the Assembler do the calculation for us!
XTAL equ 33333333
FREQ equ 100 ; 1/100Hz=10ms
RELOAD_TIMER0_10ms equ 65536-(XTAL/(12*FREQ))

Wait10ms:
; Initialize the timer
mov a, TMOD
anl a, #11110000B ; Clear bits for timer 0, keep bits for timer 1
orl a, #00000001B ; GATE=0, C/T*=0, M1=0, M0=1: 16-bit timer
mov TMOD, a
clr TR0 ; Disable timer 0
mov TH0, #high(RELOAD_TIMER0_10ms )
mov TL0, #low(RELOAD_TIMER0_10ms )
clr TF0 ;Clear the timer flag
setb TR0 ; Enable timer 0
Wait10ms_L0:
jnb TF0, Wait10ms_L0 ; Wait for overflow
ret

Lecture 16-17: Stack, Interrupts, Timers 41

Copyright © 2009-2022, Jesus Calvino-Fraga. Not to be copied, used, or
revised without explicit written permission from the copyright owner.

CV-8052 Pin Assignments

JP1 JP2

LCD_DATA[0] 1 2 LCD_DATA[1] P0.0 1 2 P0.1

LCD_DATA[2] 3 4 LCD_DATA[3] P0.2 3 4 P0.3
LCD_DATA[4] 5 6 LCD_DATA[5] P0.4 5 6 P0.5
LCD_DATA[6] 7 8 LCD_DATA[7] P0.6 7 8 P0.7
LCD_EN 9 10 LCD_RS P1.0 9 10 P1.1
5V 11 12 GND 5V 11 12 GND
LCD_RW 13 14 TXD P1.2 13 14 P1.3
LCD_ON 15 16 RXD P1.4 15 16 P1.5
FL_DQ[0] 17 18 FL_DQ[1] P1.6 17 18 P1.7
FL_DQ[2] 19 20 FL_DQ[3] P2.0 19 20 P2.1
FL_DQ[4] 21 22 FL_DQ[5] P2.2 21 22 P2.3
FL_DQ[6] 23 24 FL_DQ[7] P2.4 23 24 P2.5
FL_RST_N 25 26 FL_WE_N P2.6 25 26 P2.7
FL_OE_N 27 28 FL_CE_N P3.0 27 28 P3.1
3.3V 29 30 GND 3.3V 29 30 GND
TDO 31 32 TDI P3.2 31 32 P3.3
TCS 33 34 TCK P3.4 33 34 P3.5
Not used 35 36 Not used P3.6 35 36 P3.7
T0 37 38 T1 INT0 37 38 INT1
T2 39 40 T2EX Not Used 39 40 Not used

Lecture 16-17: Stack, Interrupts, Timers 42

Copyright © 2009-2022, Jesus Calvino-Fraga. Not to be copied, used, or
revised without explicit written permission from the copyright owner.

21
 I/O ports in the 8051/CV-8052
pomon
• The Input/Output (I/O) pins are accessed using
pimon
SFRs P0, P1, P2, P3. They are all bit
pzmon addressable.
• To use the I/O as output pins configure them
with the PxMOD register (not bit addressable).
‘1’ makes the pin an output. For example to set
P0.1 as output: have a use Andor
not bit
addressable

orl P0MOD, #00000010B

• Check the manual of the processor you are
using to configure the pins:

Lecture 16-17: Stack, Interrupts, Timers 43

Copyright © 2009-2022, Jesus Calvino-Fraga. Not to be copied, used, or
revised without explicit written permission from the copyright owner.

Always check the manual!

For the STM32Fxx:

For the STM32Lxx:

Not the
Same

Lecture 16-17: Stack, Interrupts, Timers 44

Copyright © 2009-2022, Jesus Calvino-Fraga. Not to be copied, used, or
revised without explicit written permission from the copyright owner.

22
 masks
bin

Always check the manual!

For the STM32Fxx: For the STM32Lxx:

Initialize pin PA0 as output in the STM32Fxx:

GPIOA->MODER |= 0x00000001;

Initialize pin PA0 as output in the STM32Lxx:

GPIOA->MODER = (GPIOA->MODER & 0xfffffffc) | 0x00000001;

Lecture 16-17: Stack, Interrupts, Timers 45

Copyright © 2009-2022, Jesus Calvino-Fraga. Not to be copied, used, or
revised without explicit written permission from the copyright owner.

profiling
Exercises
• A common way of passing parameters to a function is
via the stack. Modify the function WaitHalfSec so that it
receives the number of half-seconds to wait in the stack.
(Note: this problem is not as trivial as it sounds. You
may need to increment and/or decrement register SP to
solve this problem)
• Most C programs pass parameters to functions via the
stack. Also C programs use the stack to allocate
automatic variables (local variables defined within the
function). This works fine most of the time, but
sometimes a condition commonly known as “stack
overflow” occurs. Explain what causes “stack overflow”.

Lecture 16-17: Stack, Interrupts, Timers 46

Copyright © 2009-2022, Jesus Calvino-Fraga. Not to be copied, used, or
revised without explicit written permission from the copyright owner.

23
 Exercises
• Write an Interrupt service routine for timer 0 that
generates a 1 kHz square wave in pin P0.0 of
the CV-8052 processor.
• Write an interrupt service routine for timer 2 that
increments a two digit BCD counter displayed in
the 7-segment displays HEX1 and HEX0 of the
CV-8052 every second. Make sure that the ISR
for this question and the ISR from the previous
question can run concurrently in the same
processor.
Lecture 16-17: Stack, Interrupts, Timers 47
Copyright © 2009-2022, Jesus Calvino-Fraga. Not to be copied, used, or
revised without explicit written permission from the copyright owner.

Exercises
• Write a one second delay function using
timer 1. This function will run in a CV-
8052 with a 33.33MHz clock.
• Program profiling is used to find the usage
of resources by a piece of code (a
subroutine, for example). A profile value
often needed is execution time. Show
how to use timer 0 to find out the
execution time of a subroutine.

Lecture 16-17: Stack, Interrupts, Timers 48

Copyright © 2009-2022, Jesus Calvino-Fraga. Not to be copied, used, or
revised without explicit written permission from the copyright owner.

24
ex
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 Exercises
• From the examples given in this lecture,
explain how to use the timer overflow flag
to measure frequencies higher than 65535
Hz while using a 1-second time interval.

Lecture 16-17: Stack, Interrupts, Timers 49

Copyright © 2009-2022, Jesus Calvino-Fraga. Not to be copied, used, or
revised without explicit written permission from the copyright owner.

25