COMPUTER ORGANIZATION AND ARCHITECTURE

• Computer Architecture refers to those attributes of a system that have a direct impact on
the logical execution of a program. Examples:
o the instruction set
o the number of bits used to represent various data types
o I/O mechanisms
o memory addressing techniques
• Computer Organization refers to the operational units and their interconnections that
realize the architectural specifications. Examples are things that are transparent to the
programmer:
o control signals
o interfaces between computer and peripherals
o the memory technology being used
• So, for example, the fact that a multiply instruction is available is a computer architecture
issue. How that multiply is implemented is a computer organization issue.

• Architecture is those attributes visible to the programmer

o Instruction set, number of bits used for data representation, I/O mechanisms,
addressing techniques.
o e.g. Is there a multiply instruction?
• Organization is how features are implemented
o Control signals, interfaces, memory technology.
o e.g. Is there a hardware multiply unit or is it done by repeated addition?
• All Intel x86 family share the same basic architecture
• The IBM System/370 family share the same basic architecture
• This gives code compatibility
o At least backwards
• Organization differs between different versions

STRUCTURE AND FUNCTION

• Structure is the way in which components relate to each other

• Function is the operation of individual components as part of the structure
• All computer functions are:

o Data processing: Computer must be able to process data which may take a wide
variety of forms and the range of processing.
o Data storage: Computer stores data either temporarily or permanently.

o Data movement: Computer must be able to move data between itself and the
outside world.
o Control: There must be a control of the above three functions.
 Fig: Functional view of a computer

Fig: Data movement operation Fig: Storage Operation

Fig: Processing from / to storage Fig: Processing from storage to i/o

• Four main structural components: o Central processing unit (CPU)
 o Main memory
o I/O
o System interconnections
• CPU structural components:
o Control unit
o Arithmetic and logic unit (ALU)
o Registers
o CPU interconnections

Peripherals

Computer
Central
Computer Main
Processing
Memory
Unit
Systems

Interconnection

Communication lines
Fig: Computer: Top level structure Input

Output

CPU
Arithmetic
Computer
Registers and
I/O
System
CPU
Login Unit
Bus Internal CPU
Memory
Interconnection

Control unit

Fig: The central processing unit

 Control Unit

CPU
Sequencing
ALU

Internal Control Login

Bus Control Unit
Unit
Registers Registers and

Decoders

Control

Fig: The control unit Memory

COMPUTER COMPONENTS
• The Control Unit (CU) and the Arithmetic and Logic Unit (ALU) constitute the Central
Processing Unit (CPU)
• Data and instructions need to get into the system and results need to get out
o Input/output (I/O module)
• Temporary storage of code and results is needed
o Main memory (RAM)
• Program Concept
o Hardwired systems are inflexible
o General purpose hardware can do different tasks, given correct control signals
o Instead of re-wiring, supply a new set of control signals
COMPUTER FUNCTION
The basic function performed by a computer is execution of a program, which consists of a set of
instructions stored in memory.
• Two steps of Instructions Cycle:
o Fetch
o Execute

Fig: Basic Instruction Cycle

• Fetch Cycle
o Program Counter (PC) holds address of next instruction to fetch
o Processor fetches instruction from memory location pointed to by PC
o Increment PC
Unless told otherwise
o Instruction loaded into Instruction Register (IR)

• Execute Cycle
o Processor interprets instruction and performs required actions, such as:
Processor - memory
o data transfer between CPU and main memory
Processor - I/O
o Data transfer between CPU and I/O module
Data processing
o Some arithmetic or logical operation on data
Control
o Alteration of sequence of operations
o e.g. jump
Combination of above
Fig: Example of program execution (consists of memory and registers in hexadecimal)
• The PC contains 300, the address of the first instruction. The instruction (the value 1940 in
hex) is loaded into IR and PC is incremented. This process involves the use of MAR and
MBR.
• The first hexadecimal digit in IR indicates that the AC is to be loaded. The remaining
three hexadecimal digits specify the address (940) from which data are to be loaded.
• The next instruction (5941) is fetched from location 301 and PC is incremented.
• The old contents of AC and the contents of location 941 are added and the result is stored
in the AC.
• The next instruction (2941) is fetched from location 302 and the PC is incremented.
• The contents of the AC are stored in location 941.

Fig: Instruction cycle state diagram

BUS INTERCONNECTION
• A bus is a communication pathway connecting two or more devices
• Usually broadcast (all components see signal)
• Often grouped
o A number of channels in one bus
o e.g. 32 bit data bus is 32 separate single bit channels
• Power lines may not be shown
• There are a number of possible interconnection systems
• Single and multiple BUS structures are most common
• e.g. Control/Address/Data bus (PC)
• e.g. Unibus (DEC-PDP)
• Lots of devices on one bus leads to:
o Propagation delays
o Long data paths mean that co-ordination of bus use can adversely affect
performance
o If aggregate data transfer approaches bus capacity
• Most systems use multiple buses to overcome these problems
 • Data Bus
o Carries data
▪
Remember that there is no difference between “data” and “instruction” at this
level
o Width is a key determinant of performance
8, 16, 32, 64 bit
• Address Bus
o Identify the source or destination of data
o e.g. CPU needs to read an instruction (data) from a given location in memory
p Bus width determines maximum memory capacity of system
e.g. 8080 has 16 bit address bus giving 64k address space
• Control Bus
q Control and timing information
Memory read
Memory write
I/O read
I/O write
Transfer ACK
Bus request
Bus grant
Interrupt request
Interrupt ACK
Clock
Reset

Multiple Bus Hierarchies

• A great number of devices on a bus will cause performance to suffer

o Propagation delay - the time it takes for devices to coordinate the use of the bus
o The bus may become a bottleneck as the aggregate data transfer demand approaches
the capacity of the bus (in available transfer cycles/second)
• Traditional Hierarchical Bus Architecture
o Use of a cache structure insulates CPU from frequent accesses to main memory
o Main memory can be moved off local bus to a system bus
o Expansion bus interface
buffers data transfers between system bus and I/O controllers on expansion bus
insulates memory-to-processor traffic from I/O traffic
 Traditional Hierarchical Bus Architecture Example

PCI
• PCI is a popular high bandwidth, processor independent bus that can function as mezzanine
or peripheral bus.
• PCI delivers better system performance for high speed I/O subsystems (graphic display
adapters, network interface controllers, disk controllers etc.)
• PCI is designed to support a variety of microprocessor based configurations including both
single and multiple processor system.
• It makes use of synchronous timing and centralised arbitration scheme.
• PCI may be configured as a 32 or 64-bit bus.
• Current Standard
o up to 64 data lines at 33Mhz
o requires few chips to implement
o supports other buses attached to PCI bus
o public domain, initially developed by Intel to support Pentium-based systems
o supports a variety of microprocessor-based configurations, including multiple
processors
o uses synchronous timing and centralized arbitration
Note: Bridge acts as a data buffer so that the speed of the PCI bus may differ from that of the
processor’s I/O capability.

PCI Bus Lines

• Systems lines
o Including clock and reset
• Address & Data
o 32 time mux lines for address/data
o Interrupt & validate lines
• Interface Control
• Arbitration
o Not shared
o Direct connection to PCI bus arbiter
• Interrupt lines
o Not shared
• Cache support
• 64-bit Bus Extension
o Additional 32 lines
o Time multiplexed
o 2 lines to enable devices to agree to use 64-bit transfer
• JTAG/Boundary Scan
o For testing procedures

CPU REGISTERS
In computer architecture, a processor register is a very fast computer memory used to
speed the execution of computer programs by providing quick access to commonly used
values-typically, the values being in the midst of a calculation at a given point in time.

These registers are the top of the memory hierarchy, and are the fastest way for the system
to manipulate data. In a very simple microprocessor, it consists of a single memory
location, usually called an accumulator. Registers are built from fast multi-ported memory
cell. They must be able to drive its data onto an internal bus in a single clock cycle. The
result of ALU operation is stored here and could be re-used in a subsequent operation or
saved into memory.

Registers are normally measured by the number of bits they can hold, for example, an “8-bit
register” or a “32-bit register”. Registers are now usually implemented as a register file, but
they have also been implemented using individual flip-flops, high speed core memory, thin
film memory, and other ways in various machines.

The term is often used to refer only to the group of registers that can be directly indexed
for input or output of an instruction, as defined by the instruction set. More properly, these
are called the “architected registers“. For instance, the x86 instruction set defines a set of
eight 32-bit registers, but a CPU that implements the X86 instruction set will contain many
more hardware registers than just these eight.
There are several other classes of registers:

(a) Accumulator: It is most frequently used register used to store data taken from
memory. Its number varies from microprocessor to microprocessor.

(b) General Purpose registers: General purpose registers are used to store data and
intermediate results during program execution. Its contents can be accessed through
assembly programming.

(c) Special purpose Registers: Users do not access these registers. These are used by
computer system at the time of program execution. Some types of special purpose registers
are given below:

• Memory Address Register (MAR): It stores address of data or instructions to

be fetched from memory.
• Memory Buffer Register (MBR): It stores instruction and data received from
the memory and sent from the memory.
• Instruction Register (IR): Instructions are stored in instruction register. When
one instruction is completed, next instruction is fetched in memory for processing.
• Program Counter (PC): It counts instructions.

The instruction cycle is completed into two phases:

(a) Fetch Cycle and

(b) Execute Cycle.

There are two parts in instruction- opcode and operand. In fetch cycle opcode of instruction
is fetched into CPU. The opcode, at first, is reached to Data Register (DR), then to Instruction
Register (IR). Decoder accesses the opcode and it decodes opcode and type of operation is
declared to CPU and execution cycle is started.