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Digital Electronics
Assignment- Week 7
TYPE OF QUESTION: MCQ/MSQ
Number of questions: 15 Total mark: 15 X 1 = 15
QUESTION 1:
Which of the following are the characteristic equations of J-K and S-R Flip flop?
a. Qn+1 = JnQn’ + Kn’Qn and Qn+1 = Sn + Rn’Qn
b. Qn+1 = JnQn + Kn’Qn’ and Qn+1 = Sn + Rn’Qn
c. Qn+1 = JnQn + Kn’Qn’ and Qn+1 = Sn’ + Rn’Qn
d. Qn+1 = JnQn’ + Kn’Qn and Qn+1 = Sn’ + Rn’Qn

Correct answer: a
Detailed Solution:

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QUESTION 2:

Truth-Table of a hypothetical AB flip-flop is given next. Find its characteristic equation.

A B 𝑄𝑛+1

0 0 0

0 1 𝑄𝑛

1 0 𝑄𝑛′

1 1 1

a. Qn+1 = AQn + BQn’

b. Qn+1 = AQn’ + BQn
c. Qn+1 = A’Qn + BQn’
d. Qn+1 = AQn’ + B’Qn

Correct Answer: b

Detailed Solution:

Qn+1 = AQn’ + BQn

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QUESTION 3:

What will be the simplified expression in the next state Q+?

a. xQ
b. xʘQ’
c. xQ’
d. xʘQ

Correct Answer: a

Detailed Solution:
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QUESTION 4:

Which is correct for a gated D latch?

a. The output follows the input when enabled
b. The output toggles if one of the inputs is HIGH.
c. The output complement follows the input when enabled.
d. None of these

Correct Answer: a

Detailed Solution:

Inputs Outputs
Comments
D EN Qn Qn’

0 1 0 1 RESET

1 1 1 0 SET

X 0 Qn-1 Qn-1’ No change

QUESTION 5:

For a Master-slave J-K flip-flop, which statements are correct?

1. The toggle frequency is the maximum clock frequency at which the flip-flip will toggle reliably
2.The data input must precede the clock triggering edge transition time by some minimum time
3.The data input must remain fixed for a given time after the clock triggering edge transition
time for reliable operation
4.The rise time and fall time of the data is equal to the propagation delay time

a. 1, 2 and 3
b. 2, 3 and 4
c. 3, 4 and 1
d. 4, 1 and 2

Correct Answer: a
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Detailed Solution:

Refer to Lecture-32, DEC, NPTEL online certification courses.

QUESTION 6:

The circuit which is activated when the clock signal goes from low to high Is called ___

a. positive edge triggered

b. negative edge triggered
c. neutral edge triggered
d. dynamic edge triggered

Correct Answer: a

Detailed Solution: If the circuit is positive edge triggered, it will take input at exactly the time
in which the clock signal goes from low to high.
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QUESTION 7:

All the flip-flops in the following circuit are initially RESET after which clock signal is triggered
continuously. The output Y goes HIGH after every N clock pulse(s) and remains HIGH for M clock
period(s). The value of N and M respectively are: (Q,R,S,T are outputs of the D flip-flops).

a. 4, 1
b. 8, 1
c. 16, 1
d. 16, 2

Correct Answer: b
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Detailed Solution:
The states which the counter circuit assumes at different clock pulses are:

CLK Q R S T Y=T’Q’

- 0 0 0 0

1 1 0 0 0 0

2 1 1 0 0 0

3 1 1 1 0 0

4 1 1 1 1 0

5 0 1 1 1 0

6 0 0 1 1 0

7 0 0 0 1 0

8 0 0 0 0 1

9 1 0 0 0 0

Since it takes 8 steps, it is a modulo – 8 counter. Y = Q’T’ remains HIGH for one clock period for
every 8 clock cycles.

QUESTION 8:

If A = 1 and B = 1, and now B is replaced by a sequence 10101010…, the outputs P and Q will be

a. Fixed at P = 0 & Q = 0
b. Fixed at P = 0 & Q = 010101….
c. P = 101010…., & Q = 010101….
d. P = 010101…., & Q = 101010….
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Correct Answer: b

Detailed Solution:

A=1 B=1 P=0 Q=0

=1 =0 =0 =1
=1 =1 =0 =0
Fixed 0 010101….

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QUESTION 9:

Whose operations are faster among the following?

a. Combinational circuits
b. Sequential circuits
c. Latches
d. Flip-flops

Correct Answer: a

Detailed Solution:

Combinational circuits are often faster than sequential circuits. Since, the combinational circuits
do not require memory elements whereas the sequential circuits need memory devices to perform
their operations in sequence.
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QUESTION 10:

If initial state 𝑄0 𝑄1 𝑄2 = 010 and clock period = 40 ns; the transitions take place at rising edge.

For the given sequence generator:

The sequence till it repeats will be given as the following and calculate the repetition rate

010 101 100 110

001
a. and 5 x 106 times/sec

010 110 100 101

001
b. and 5 x 106 times/sec

010 110 100 101

001
c. and 4 x 106 times/sec

010 101 100 110

001
d. and 4 x 106 times/sec

Correct Answer: b
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Detailed Solution:

= = = 010 110 100 101

001
0 1 0 1 1 0 1 1 0

1 1 0 1 0 0 1 0 0 5 states are required till the sequence

repeats:
1 0 0 1 0 1 1 0 1
Repetition time = 5* 40 ns = 200 ns
1 0 1 0 0 1 0 0 1
So f = 1/200 ns = 5 x 106 times/sec
0 0 1 0 1 0 0 1 0

0 1 0 1 1 0 … … …

… … … … … …

QUESTION 11:

An X-Y flip-flop, whose X Y characteristics table is given

below, is to be implemented using a J-K flip-flop.
0 0 1

0 1

1 0

1 1 0

This can be done by making:

a. J=X,K=Y’
b. J=X’,K=Y
c. J=Y,K=X’
d. J=Y’,K=X
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Correct Answer: d

Detailed Solution:

The characteristic truth table of the given flip-flop is:

𝑋 𝑌 𝑄𝑛 𝑄𝑛+1 We can write the Boolean expression as follows:

0 0 0 1 𝑄𝑛+1 = 𝑓(𝑋, 𝑌, 𝑄𝑛 ) = ∑(0,1,3,4)

0 0 1 1 Simplifying this equation via a K-Map,

0 1 0 0

0 1 1 1

1 0 0 1

1 0 1 0 𝑄𝑛+1 = 𝑌 ′ 𝑄𝑛′ + 𝑋′𝑄𝑛

1 1 0 0 The characteristic equation of a JK flip flop is given by,

1 1 1 0 𝑄𝑛+1 = 𝐽𝑄𝑛′ + 𝐾′𝑄𝑛

Hence, comparing the two equations, we obtain, 𝐽 = 𝑌 ′ , 𝐾 = 𝑋.

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QUESTION 12:

In a JK flip-flop, we have J=Q' and K=1. Assume the flip-flop is initially cleared and then clocked for
6 pulses, what is the sequence of output

a. 000000
b. 101010
c. 111000
d. 111111

Correct Answer: b

Detailed Solution: Initially, Q=0

The sequence is 101010

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QUESTION 13:

What are the final values of Q1 and Q0 after 4 clock cycles, if initial values are 00 in the
sequential circuit shown below?

a. 11
b. 01
c. 10
d. 00

Correct Answer: d

Detailed Solution:

Initial: 00 States Q0 and Q1 are zero

Clock 1: 11 State Q0 changed to 1 because input T is 1 and previous state was 0 and State Q1
changed to 1 because input T is 1 and previous state was 0.

Clock 2: 01 State Q0 changed to 0 because input T is 1 and previous state was 1 and State Q1
remains same because clk value is 0.

Clock 3: 10 State Q0 changed to 1 because input T is 1 and previous state was 0 and State Q1
changed to 0 because input T is 1 and previous state was 1.

Clock 4: 00 State Q0 changed to 0 because input T is 1 and previous state was 1 and State Q1
remains same because clk value is 0.
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QUESTION 14:

The present output Q of an edge triggered JK flip flop is logic 0. If J=1, then Q(t+1) is

a. Cannot be determined
b. Logic 0
c. Logic 1
d. Race around condition

Correct Answer: c

Detailed Solution:

Q J K Q(t+1)

0 1 0 1

0 1 1 1

Irrespective of value of K, output will be 1.

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QUESTION 15:

The truth table for AB flip flop is shown below. Design the flip-flop using J-K flip flops.

A B

0 0

0 1

1 0 1

1 1 0

a. J=B, K=AʘB
b. J=B’, K=AB
c. J=B, K=AB
d. J=B’, K=AʘB

Correct Answer: d
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Detailed Solution:

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