SCHOOL OF SCIENCE AND HUMANITIES

DEPARTMENT OF COMPUTER SCIENCE

UNIT – I

Fundamentals Of Microprocessors – SBSB1516

Architecture of 8085 Microprocessor - Pin details of 8085 – Instruction cycle –

machine cycle – T-state -Timing diagrams for Op-code Fetch Cycle Memory Read, Memory
Write, I/O Read, I/O Write -Interrupts and its types.
INTRODUCTION TO 8085 MICROPROCESSOR
Computer's Central Processing Unit (CPU) built on a single Integrated Circuit (IC) is
called a microprocessor.
A digital computer with one microprocessor which acts as a CPU is called microcomputer.
It is a programmable, multipurpose, clock -driven, register-based electronic device that reads
binary instructions from a storage device called memory, accepts binary data as input and
processes data according to those instructions and provides results as output.
The microprocessor contains millions of tiny components like transistors, registers, and
diodes that work together.
Basic Terms used in Microprocessor
Here is a list of some basic terms used in microprocessor:
Instruction Set - The group of commands that the microprocessor can understand is called
Instruction set. It is an interface between hardware and software.
Bus - Set of conductors intended to transmit data, address or control information to different
elements in a microprocessor. A microprocessor will have three types of buses, i.e., data bus,
address bus, and control bus.
IPC (Instructions Per Cycle) - It is a measure of how many instructions a CPU is capable of
executing in a single clock.
Clock Speed - It is the number of operations per second the processor can perform. It can be
expressed in megahertz (MHz) or gigahertz (GHz). It is also called the Clock Rate.
Bandwidth - The number of bits processed in a single instruction is called Bandwidth.
Word Length - The number of bits the processor can process at a time is called the word
length of the processor. 8-bit Microprocessor may process 8 -bit data at a time. The range of
word length is from 4 bits to 64 bits depending upon the type of the microcomputer.
Data Types - The microprocessor supports multiple data type formats like binary, ASCII,
signed and unsigned numbers.
Features of Microprocessor
o Low Cost - Due to integrated circuit technology microprocessors are available at very
low cost. It will reduce the cost of a computer system.
o High Speed - Due to the technology involved in it, the microprocessor can work at
very high speed. It can execute millions of instructions per second.
o Small Size - A microprocessor is fabricated in a very less footprint due to very large
scale and ultra large scale integration technology. Because of this, the size of the
computer system is reduced.
o Versatile - The same chip can be used for several applications, therefore,
microprocessors are versatile.
o Low Power Consumption - Microprocessors are using metal oxide semiconductor
technology, which consumes less power.
o Less Heat Generation - Microprocessors uses semiconductor technology which will
not emit much heat as compared to vacuum tube devices.
o Reliable - Since microprocessors use semiconductor technology, therefore, the failure
rate is very less. Hence it is very reliable.
1.1.Architecture of 8085 Microprocessor
Microprocessor (up) is a clock driven semiconductor device. It can be manufactured by
using either a large scale integration (LSI) or very large scale integration (VLSI) technique.
The microprocessor is similar to CPU, but it includes all the logic circuitry, including the
control unit. The micro processor contains three segments namely arithmetic logic unit
(ALU) register array and control unit.
The microprocessor is capable of performing various computing functions and making
decisions to change the sequence of program execution
It is the central processing unit which coordinates all the functions of a computer. It generates
timing signals, sends and receives data to and from every peripheral used inside or outside the
computer.
Intel 8085 is an 8-bit, NMOS microprocessor designed by Intel in 1977.
It has following configuration:
o It is a 40 pin I.C. package fabricated on a single LSI chip.
o The Intel 8085 uses a single +5Vd.c. supply for its operation.
o Intel 8085 clock speed is about 3 MHz; the clock cycle is of 320ns.
o 8 bit data bus.
o Address bus is of 16-bit, which can address up to 64KB
o 16-bit stack pointer
o 16 bit PC (Program Counter)
o Six 8-bit registers are arranged in pairs :BC, DE, HL
8085 microprocessor consists of various functional blocks as listed below:
(i)Registers
o General Purpose Register
o Temporary Register
o Special Purpose Register
o Accumulator
o Flag Register
o Instruction Register
(ii) Arithmetic Logic Unit(ALU)
(iii)Instruction Decoder and Machine Cycle Encoder
(iv) Address Buffer
(v) Data/Address Buffer
(vi) Incrementer/Decrementer Address Latch
(vii) Interrupt Control
(viii) Serial I/O Control
(ix) Timing and Control Unit

S-Sign Flag
 After execution of any arithmetic and logical operation, if D7 of the result is 1, the
sign flag is set. Otherwise it is reset.
 D7 is reserved for indicating the sign, the remaining is the magnitude of number
 1157 is 1, the number will be viewed as negative number. If D7 is 0, the mumber will
be viewed as positive number.
Z-Zero Flag
If the result of arithmetic and logical operation is zero, then zero flag is set otherwise it is
reset.
AC-Auxiliary Carry Flag
In an arithmetic operation, when a carry is generated by digit D3, and passed onto digit D4,
the AC flag is set, otherwise it is reset.
P-Parity Flag
If the result of arithmetic and logical operation contains even number of I's then this flag will
be set and if it is odd number of I's it will be reset.
C-Carry Flag
If any arithmetic and logical operation result any carry then carry flag is set otherwise it is
reset
Instruction Register
When an instruction is fetched from the memory, it is loaded in the instruction register.
Program Counter (PC)
 This 16-bit register sequencing the execution of instructions.
 It is a memory pointer. Memory locations have 16-bit addresses.

 The function of the program counter is to point to the memory address of the next
instruction to be executed.
 When an opcode is being fetched, the program counter is incremented by one to point
to the next memory location.
Stack Pointer (SP)
 The stack pointer is also a 16-bit register used as a memory pointer.
 It points to a memory location in R/W memory, called the stack.
 The beginning of the stack is defined by loading a 16-bit address in the stack pointer
(register).
Arithmetic and Logic Unit (ALU)
 It is used to perform the arithmetic operations like addition, subtraction,
multiplication, division, increment and decrement and logical operations like AND,
OR and EX-OR.
Microprocessor
 It receives the data from accumulator and registers.
 According to the result it set or reset the flags.
Instruction Decoder
It gets the instruction from the instruction register and decodes the instruction. It
identifies the instruction to be performed.
Machine Cycle Encoder
The 8085 microprocessor executes different types of machine cycles. It gives the
information about which machine cycle is currently executing in the encoded form on the
SO.SI and IO/M lines.
Address Buffer
 The address bus is a group of 16 lines generally identified as A0 to A15.
 The address bus is unidirectional: bits flow in one direction-from the MPU to
peripheral devices.
Data Buffer
 The data bus is a group of eight lines used for data flow.
  These lines are bi-directional data flow in both directions between the MPU and
memory and peripheral devices.
 The eight data lines enable the MPU to manipulate 8-bit data ranging from 00 to FF
(28-256 numbers).
Incrementer/Decrementer Address Latch
This 16-bit register is used to increment or decrement the contents of program counter and
stack pointer.

Interrupt Control
Interrupts are signals coming from external devices to call the attention of the
microprocessor. The 8085 has five interrupt signals. They are TRAP: RST7.5, RST 6.5, RST
5.5 and INTR.
Serial I/O Control
The 8085 microprocessor provides two serial I/O controls.
(i) SID (Serial Input Data) This line is used to receive data bit by bit(serially).
(ii) SOD(Serial Output Data) - This line is used to send data bit by bit (serially).
Timing and Control Unit
This unit synchronizes all the microprocessor operations with the system clock. It also
generates the control signals necessary for communicating in between the microprocessor and
peripherals.

1.2. Pin diagram of 8085

8085 is a 40 pin IC. DIP package. All the signals can be classified into five groups.

1. Power supply and clock signals

2. Address bus

3. Data bus

4. Control and status signals

5. Interrupts and externally initiated signals

Power supply and Clock frequency signals

Vcc: +5 volt power supply

Vss: Ground terminal

X1, X2: Crystal or R/C network or LC network connections to set the frequency of internal
clock generator. The frequency is internally divided by two. Since the basic operating timing
frequency is 3 MHz. a 6 MHz crystal is connected externally.
CLK-Clock Output is used as the system clock for peripheral and devices interfaced with the
microprocessor.

Address Bus

A8-A15 -It carries the most significant 8 bits of the memory address or the 8 bits of the I/O
address

Multiplexed Address / Data Bus

ADO-AD7

 These multiplexed set of lines used to carry the lower order 8 bit address as well as
data bus.During the opcode fetch operation, in the first clock cycle, the lines deliver
the lower order address A0 - A7.
 In the subsequent 10/memory, read/write clock cycle the lines are used as data bus.
 The CPU may read or write out data through these lines.

Control and Status signals

ALE Address Latch Enable - This signal helps to capture the lower order address presented
on the multiplexed address / data bus.
RD (Read)- Read memory or IO device - This indicates that the selected memory location or
I/O device is to be read and that the data bus is ready for accepting data from the memory or
I/O device.

WR (Write) - Write memory or 10 device. - This indicates that the data on the data bus is to
be written into the selected memory location or I/O device.

IO/M (Input Output/Memory) - Select memory or an 10 device.

 This status signal indicates that the read/write operation relates to whether the
memory or I/O device.
 It goes high to indicate an I/O operation.
 It goes low for memory operations.

S0 and S1, These are status signals, similar to 10/M. These signalscan be used to identify
various machine cycle operations.

Interrupts and Externally initiated operations

They are the signals initiated by an external device to request the microprocessor to do a
particular task or work. There are five hardware interrupts called.
  TRAP
 RST 7.5
 RST 65
 RST 5.5
 INTR

The microprocessor acknowledges Interrupt Request by INTA' signal. In addition to

Interrupts, there are three externally initiated signals namely RESET, HOLD and
READY. To respond to HOLD request, it has one signal called HLDA.

1. INTR (Interrupt Request): This pin is used to request an interrupt from an external

device.

2. RST7.5, RST6.5, RST5.5: These are vectored interrupts with different priority levels.

3. TRAP: This is a non-maskable interrupt and has the highest priority.

4. INTA (Interrupt Acknowledge): This pin is used to acknowledge interrupts from

external devices.

INTA (active low output) - On receipt of an interrupt, the microprocessor acknowledges the
interrupt by the active low INTA (Interrupt Acknowledge) signal.

DMA Signals

HOLD - It indicates that another device is requesting the use of the address and data bus.
Having received HOLD request the microprocessor relinquishes the use of the buses as soon
as the current machine cycle is completed. Internal processing may continue. After the
removal of the HOLD signal the processor regains the bus.

HLDA - It is a signal which indicates that the hold request has been received after the
removal of a HOLD request, the HLDA goes low

Reset In

 This signal is used to reset the microprocessor.

 The program counter inside the microprocessor is set to zero.
 The buses are tri-stated.

Reset Out

 It indicates CPU is being reset.

 Used to reset all the connected devices when the microprocessor is reset.

READY
  Memory and I/O devices will have slower response compared to microprocessors.
 Before completing the present job such a slow peripheral may not be able to handle
further data or control signal from CPU.
 The processor sets the READY signal after completing the present job to access the
data
 The microprocessor enters into WAIT state while the READY pin is disabled.

Single Bit Serial I/O ports

SID - Serial input data line

SOD - Serial output data line

These signals are used for serial communication.

Features of 8085 Microprocessor

1. 8-bit Processor: Processes 8 bits of data at a time.

2. 16-bit Address Bus: Can address up to 64 KB of memory.

3. 5 MHz Clock Speed: Provides a decent processing speed for basic tasks.

4. Low Power Consumption: Ideal for embedded systems with minimal power needs.

5. Interrupt System: Features 5 interrupt pins for external signal response.

Limitations of 8085 Microprocessor

1. Limited Memory Addressing: Can address only up to 64KB of memory due to its 16-bit
address bus.

2. No Multiprocessing Support: Cannot connect multiple processors for parallel

processing.

3. Limited Instruction Set: Supports only 50 instructions, restricting its functionality for
complex tasks.

4. No Direct Memory Access: Lacks DMA (Direct Memory Access) support, which slows
data transfer between memory and peripherals.

5. Slower Processing: With a clock speed of up to 5 MHz, it is slower compared to modern

processors.

1.3. Instruction cycle in 8085 microprocessor

The instruction cycle of the 8085 microprocessor consists of four basic steps, which are:

1. Fetch: In this step, the microprocessor fetches the instruction from the memory

location pointed to by the program counter (PC). The PC is incremented by one after the
fetch operation.

2. Decode: Once the instruction is fetched, the microprocessor decodes it to determine the
operation to be performed and the operands involved.

3. Execute: In this step, the microprocessor performs the operation specified by the
instruction on the operands.

4. Store: Finally, the result of the execution is stored in the appropriate memory location or
register. Once the execution of an instruction is complete, the microprocessor returns to the
fetch step to fetch the next instruction to be executed. This cycle repeats until the program is
complete or interrupted.

Why need the Instruction cycle in 8085 microprocessor ?

The instruction cycle is a fundamental concept in the operation of the 8085 microprocessor
because it is the process by which the microprocessor fetches, decodes, and executes
instructions. The execution of a program in a microprocessor involves a sequence of
instructions, and each instruction is executed using the instruction cycle.

The instruction cycle is necessary in the 8085 microprocessor because it ensures that the
instructions are executed in the correct sequence and that the correct operation is performed
on the correct data. The fetch step ensures that the correct instruction is obtained from
memory, the decode step ensures that the correct operation is determined, and the execute
step ensures that the correct operation is performed on the correct data.

Furthermore, the instruction cycle allows the microprocessor to execute instructions at a very
high speed, which is critical in applications where real-time performance is required. By
efficiently executing instructions using the instruction cycle, the microprocessor can perform
complex tasks and computations quickly and accurately.
Time required to execute and fetch an entire instruction is called instruction cycle. It consists:

• Fetch cycle - The next instruction is fetched by the address stored in program counter (PC)
and then stored in the instruction register.

• Decode instruction - Decoder interprets the encoded instruction from instruction register.

• Reading effective address - The address given in instruction is read from main memory and
required data is fetched. The effective address depends on direct addressing mode or indirect
addressing mode.

• Execution cycle - consists memory read (MR), memory write (MW), input output read
(IOR) and input output write (IOW)

Uses of Instruction cycle in 8085 microprocessor :

Some of the key uses of the instruction cycle in the 8085 microprocessor include:

1. Execution of instructions: The instruction cycle is used to execute the instructions in a

program. Each instruction in the program is fetched, decoded, and executed using the
instruction cycle.

2. Control flow: The instruction cycle is used to control the flow of instructions in a program.
Once an instruction is executed, the microprocessor moves on to the next instruction in the
program.

3. Real-time processing: The instruction cycle allows the 8085 microprocessor to execute
instructions quickly and accurately, making it well-suited for real-time processing
applications where speed and accuracy are critical.

4. Resource management: The instruction cycle is used to manage the resources of the 8085
microprocessor, including the memory and registers. The fetch step retrieves instructions
from memory, while the store step writes results back to memory or registers.

5. Interrupt handling: The instruction cycle is used to handle interrupts in the 8085
microprocessor. When an interrupt occurs, the current instruction cycle is suspended, and the
microprocessor jumps to a separate interrupt routine to handle the interrupt.

Issues of Instruction cycle in 8085 microprocessor :

Some of the key issues of the instruction cycle in the 8085 microprocessor include:

1. Timing: The instruction cycle requires precise timing to ensure that each step is

executed correctly. If the timing is off, it can lead to incorrect results or cause the

microprocessor to malfunction.
2. Instruction set limitations: The 8085 microprocessor has a limited instruction set, which
can make it difficult to perform certain operations or tasks. This can lead to inefficient code
and slower execution times.

3. Data transfer: The instruction cycle is used to transfer data between memory and registers,
but this process can be slow and inefficient. This can be a problem when working with large
amounts of data or when real-time processing is required.

4. Interrupt handling: Although the instruction cycle is used to handle interrupts, it can be
challenging to ensure that the microprocessor returns to the correct point in the program after
handling an interrupt.

5. Instruction sequencing: The instruction cycle requires instructions to be executed in a

specific sequence, which can limit the flexibility of the microprocessor and make it difficult
to optimize code for specific tasks.

1.4.T-state

The time required by the microprocessor to complete an operation of accessing memory or

input/output devices is called machine cycle. One time period of frequency of microprocessor
is called t-state. A t-state is measured from the falling edge of one clock pulse to the falling
edge of the next clock pulse. Fetch cycle takes four t-states and execution cycle takes three t-
states.

1.5.Timing Diagram

A time diagram is a graphical representation. The 8085 instruction timing diagram represents
the execution time of each instruction in graphical format. Execution time is given in T-
states. The 8085 microprocessor has a set of control signals and data signals that play an
important role in the execution of instructions. In this article, I will explain in detail what a
timing diagram is and how to draw a timing diagram of different instructions

Clock Signal: The time required to execute an instruction is called a clock cycle.
Machine Cycle: The time required to access memory or input/output devices is called a
machine cycle. The 8085 has 5 basic machine cycles i.e., load opcode, read from memory,
write to memory, read I/O, and write I/O.

T-State: A machine cycle and an instruction cycle take several clock periods. The portion of
an operation performed in one system clock period is called a T-state.

Control Signals: The control signal controls the operations. Common signals are ALE
(address block enable), RD (read), WR (write), and IO/M (input/output) memory.

1.6. Machine Cycle in 8085 Microprocessor:

The five Machine Cycle in 8085 Microprocessor are :

1. Opcode Fetch Cycle

2. Memory Read

3. Memory Write

4. I/O Read

5. I/O Write

1. Opcode Fetch Cycle:

The first Machine Cycle of 8085 Microprocessor of every instruction is opcode fetch cycle in
which the 8085 finds the nature of the instruction to be executed. In this Machine Cycle in
8085, processor places the contents of the Program Counter on the address lines, and through
the read process, reads the opcode of the instruction.

Step 1 : (State T1) In T1 state, the 8085 places the contents of program counter on the address
bus. The high-order byte of the PC is placed on the A8 – A15 lines. The low-order byte of the
PC is placed on the AD0 – AD7 lines which stays on only during T1. Thus microprocessor
activates ALE (Address Latch Enable) which is used to latch the low-order byte of the
address in external latch before it disappears.

In T1, 8085 also sends status signals IO/M, S1, and S0. IO/M specifies whether it is a
memory or I/O operation, S1 status specifies whether it is read/write operation; S1 and S0
together indicates read, write, opcode fetch, machine cycle operation, or whether it is in
HALT state.

In opcode fetch machine cycle status signals are : IO/M = 0, S1 = 1, S0 = 1.

Step 2 : (State T2) In T2, low-order address disappears from the AD0 – AD7 lines. (However
A0 – A7 remain available as they were latched during T1). In T2, 8085 sends RD signal low
to enable the addressed memory location. The memory device then places the contents of
addressed memory location on the data bus (AD0 – AD7).

Step 3 : (State T3) During T3, 8085 loads the data from the data bus in its Instruction
Register and raises RD to high which disables the memory device.

Step 4 : (State T4) In T4, microprocessor decodes the opcode, and on the basis of
theinstruction received, it decides whether to enter state T5 or to enter state T1 of the next
Machine Cycle of 8085 Microprocessor. One byte instructions those operate on eight bit
data(8 bit operand) are executed in T4.

For example : MOV A, B, ANA D, ADD B, INR L, DCR C, RAL and many more.

Note : For one byte instructions which operate on eight bit data, data is always available in
the internal memory of 8085 i.e. registers.

Step 5 : (State T5 and T6) State T5 and T6, when entered, are used for internal
microprocessor operations required by the instruction. During T5 and T6 , 8085 performs
stack write, internal 16 bit; and conditional return operations depending upon the type of
instruction. One byte instructions those operate on sixteen bit data (16 bit operand) are
executed in T5 and T6. For example DCX H, PCHL, SPHL, INX H, etc.

2.Memory Read Cycle:

The 8085 executes the memory read cycle to read the contents of R/W memory or ROM. The
length of this machine cycle is 3-T states (T1 – T3). In this Machine Cycle in 8085, processor
places the address on the address lines from the stack pointer, general purpose register pair or
program counter, and through the read process, reads the data from the addressed memory
location the figure shows the timing diagram for memory read machine cycle. Memory read
machine cycle issimilar to the opcode fetch machine cycle. However, they use only states T1
to T3, and thestatus signal values (IO/M = 0, S1 = 1, S0 = 0) appropriate for memory read

machine cycle are issued in T1.

The following section describes the memory read machine cycle in step by step manner. Step
1 : (State T1) In T1 state, microprocessor places the address on the address lines from stack
pointer, general purpose register pair or program counter and activates ALE signal in order to
latch low-order byte of address. During T1, 8085 sends status signals : IO/M = 0, S1 = 1, and
S0 = 0 for memory read machine cycle.

Step 2 : (State T2) In T2, 8085 sends RD signal low to enable the addressed memory
location. The memory device then places the contents of addressed memory location on the
data bus (AD0 -AD7).

Step 3 : (State T3) During T3, 8085 loads the data from the data bus into specified register (F,
A, B, C, D, E, H, and L) and raises RD to high which disables the memory device.

3.Memory Write Cycle:

The 8085 executes the memory write cycle to store the data into data memory or stack
memory. The length of this machine cycle is 3T states. (T1 – T3). In this Machine Cycle of
8085 Microprocessor, processor places the address on the address lines from the stack pointer
or general purpose register pair and through the write process, stores the data into the
addressed memory location. Fig. 1.17 shows the timing diagram for memory write machine
cycle. The memory write timing diagram is similar to the memory read timing diagram,
except that instead of RD, WR signal goes low during T2 and T3. The status signals for
memory write cycle are : IO/M = 0, S1 = 0, S0 = 1.
Step 1 : (State T1) In T1 state, the 8085 places the address on the address lines from stack
pointer or general purpose register pair and activates ALE signal in order to latch low-order
byte of address. During T1, 8085 sends status signals

IO/M = 0, S1 = 0 and S0 = 1 for memory write machine cycle.

Step 2 : (State T2) In T2, 8085 places data on the data bus and sends WR signal low for
writing into the addressed memory location.

Step 3 : (State T3) During T3, WR signal goes high, which disables the memory device and
terminates the write operation.

4, 5. I/O Read and I/O Write cycles:

The I/O read and I/O write machine cycles are similar to the memory read and memory write
machine cycles, respectively, except that the 10/M signal is high for I/O read and I/O write
machine cycles. High IO/M signal indicates that it is an I/O operation. The figure show the
timing diagrams for I/O read and I/O write cycles, respectively.
shows the timing diagram of the interrupt acknowledge machine cycle and execution of RST
instruction. The interrupt acknowledge cycle is similar to the opcode fetch cycle, with two
exceptions

1.7.Interrupts in 8085 Microprocessor

In the 8085 microprocessor, interrupt is a process in which control of the program transfers
from the main program to the starting location defined by interrupt. It is a process by which
some external device or peripheral informs microprocessor to become ready for data
communication by accepting the made request. Hence, it is a signal that temporarily suspends
the normal execution of a program and redirects the control to a specific interrupt service
routine (ISR). Interrupts allow the microprocessor to respond to external events, such as user
input, system events, or hardware signals without the need for constant polling.

Types of Interrupt Signals in the 8085 Microprocessor

There are five interrupt signals in the 8085 microprocessor:

TRAP: The TRAP interrupt is a non-maskable interrupt that is generated by an external

device, such as a power failure or a hardware malfunction. The TRAP interrupt has the
highest priority and cannot be disabled.

RST 7.5: The RST 7.5 interrupt is a maskable interrupt that is generated by a software
instruction. It has the second highest priority.

RST 6.5: The RST 6.5 interrupt is a maskable interrupt that is generated by a software
instruction. It has the third highest priority.
RST 5.5: The RST 5.5 interrupt is a maskable interrupt that is generated by a software
instruction. It has the fourth highest priority.

INTR: The INTR interrupt is a maskable interrupt that is generated by an external device,
such as a keyboard or a mouse. It has the lowest priority and can be disabled.

When microprocessor receives any interrupt signal from peripheral(s) which are requesting
its services, it stops its current execution and program control is transferred to a sub-routine
by generating CALL signal and after executing sub-routine by generating RET signal again
program control is transferred to main program from where it had stopped. When
microprocessor receives interrupt signals, it sends an acknowledgement (INTA) to the
peripheral which is requesting for its service.

Interrupts can be classified into various categories based on different parameters:

Hardware and Software Interrupts: When microprocessors receive interrupt signals

through pins (hardware) of microprocessor, they are known as Hardware Interrupts. There are
5 Hardware Interrupts in 8085 microprocessor. They are: INTR, RST 7.5, RST 6.5, RST 5.5,
TRAP Software Interrupts are those which are inserted in between the program which means
these are mnemonics of microprocessor. There are 8 software interrupts in 8085
microprocessor. They are: RST 0, RST 1, RST 2, RST 3, RST 4, RST 5, RST 6, RST 7.

Vectored and Non-Vectored Interrupts: Vectored Interrupts are those which have fixed
vector address (starting address of sub-routine) and after executing these, program control is
transferred to that address. Vector Addresses are calculated by the formula 8 * TYPE.Non-
Vectored Interrupts are those in which vector address is not predefined. The interrupting
device gives the address of sub-routine for these interrupts. INTR is the only non-vectored
interrupt in 8085 microprocessor.

Maskable and Non-Maskable Interrupts: Maskable Interrupts are those which can be
disabled or ignored by the microprocessor. These interrupts are either edge-triggered or level-
triggered, so they can be disabled. INTR, RST 7.5, RST 6.5, RST 5.5 are maskable interrupts
in 8085 microprocessor. Non-Maskable Interrupts are those which cannot be disabled or
ignored by microprocessor. TRAP is a non-maskable interrupt. It consists of both level as
well as edge triggering and is used in critical power failure conditions.

Priority of Interrupts: When microprocessor receives multiple interrupt requests

simultaneously, it will execute the interrupt service request (ISR) according to the priority of
the interrupts.
Issues of Interrupts in 8085 microprocessor:

Priority conflicts: The 8085 microprocessor supports multiple interrupt signals with different
priorities. If multiple interrupts occur simultaneously, it can lead to priority conflicts and
result in incorrect operation or system failure. Therefore, the priority levels of each interrupt
signal need to be carefully designed and tested to avoid conflicts.

Race conditions: Race conditions can occur when multiple processes try to access the same
resources, such as registers or memory locations, simultaneously. This can lead to incorrect
results or system failure. Therefore, interrupt handlers need to be carefully designed to avoid
race conditions, such as by disabling interrupts during critical operations.

Interrupt latency: Interrupt latency is the time delay between when an interrupt occurs and
when the corresponding ISR starts executing. Interrupt latency can affect the system's
responsiveness and real-time performance. Therefore, interrupt handlers need to be designed
to minimize interrupt latency, such as by using fast interrupt service routines and optimizing
the interrupt handling process.

Interrupt nesting: Interrupt nesting occurs when an interrupt occurs while the
microprocessor is executing an ISR for another interrupt. Interrupt nesting can lead to
complex interrupt handling and priority conflicts. Therefore, interrupt handlers need to be
carefully designed to avoid interrupt nesting, such as by disabling lower-priority interrupts
during critical operations.

Interrupt overhead: Interrupt overhead is the additional processing time and resources
required to handle interrupts. Interrupt overhead can affect the system's performance and
efficiency, especially if the system experiences a high volume of interrupts. Therefore,
interrupt handlers need to be designed to minimize interrupt overhead, such as by optimizing
the interrupt handling process and reducing unnecessary operations.