1/19/2025

하드웨어 연동 검증
(HW-Assisted Verification or HW
Acceleration)

2025

Ando Ki, Ph.D.

[email protected]

Copyright (c) by Ando Ki 1

What to do

Host program

Interface User design

CON_FMC
FPGA

LCD
CIS

Copyright (c) by Ando Ki 2

1
 1/19/2025

Table of contents
 What to do  CON-FMC
 Background ► Connect to your FPGA board through USB
3.0
► Semiconductor chip development
► Programming interfaces
► General form of hardware test/verification
► Simple API: C and C++
► Basic types of tests and verification
technologies ► Programming interfaces: AMBA AXI BFM
► Sim, Accel, Emul, and prototype  기본 플랫폼 (basis platform)
► 필요한 패키지들
► 환경 설정 팁
► 기본플랫폼 사용

Copyright (c) by Ando Ki 3

Semiconductor chip development

HDL gate level

Specification algorithm HDL coding synthesis fabrication chip
simulation simulation

Integration
test

Copyright (c) by Ando Ki 4

2
 1/19/2025

General form of hardware test/verification

 A test-bench is a layer of code that is
created to apply input patterns (stimulus) to
the DUT (design under test) and to
determine whether the DUT produces the
outputs expected.
Test-bench

Reference
model
 A test-vector is a set of values for all the
Golden
model
expected input ports (stimuli) and expected
Stimulus Post-
generator processor values for the output ports of a module
DUT under test.

Test-vector
 A test-bench that is created to apply inputs,
sample the outputs of the DUT, and
compare the outputs with the expected
(golden) results is called a self-checking
test-bench.

Copyright (c) by Ando Ki 5

Basic types of tests and verification technologies

 Basic types of tests  Verification technologies
► Compliance testing ► Simulation technologies
 Verify that the design complies with the  Event-based simulator
specification  Cycle-based simulator
► Corner case testing  Transaction-based verification
 Try to find complex scenarios or corner cases  HW/SW co-verification
→ most likely to break the design  Hardware acceleration
► Random testing  Emulation systems
 Rapid prototyping systems
 Create scenarios that engineers do not
anticipate → uncover most obscure bugs in  Fault simulation
the design  Code coverage
 AMS simulation
► Real code testing
 Assertion-based simulation
 Uncover errors due to misunderstood spec. or
erroneous spec. Static technologies
Lint checking
► Regression testing
Static timing verification
 Verify that the existing baseline of functionality
is maintained Formal technologies
Theorem proving technique
Formal model checking
Formal equivalence checking
Copyright (c) by Ando Ki 6

3
 1/19/2025

Sim, Accel, Emul, and prototype

1) Simulation
 Software simulation or simulation in short
 Hardware assisted acceleration or TB DUT
acceleration in short Software simulator
 Emulation 2) Acceleration

 Prototyping TB DUT

Software
simulator Hardware
Real HW Simulator Accelerator Emulator Prototype
3) Emulation
Speed Real time ~10cps ~100kcps ~1Mcps ~10Mcps
Target
DUT
Visibility Poor Excellent Excellent Excellent Poor Board
Debug Poor Excellent Excellent Good Poor Hardware Software
Setup time Very long Very short Short Medium Long 4) Prototype

Coverage High Low Medium Medium Medium Target

DUT
Board
Cost Very high Low Medium High Medium
Hardware (FPGA)
Refer to ‘Applied Formal Verification’ by D.L. Perry and H.D. Foster, McGraw-Hill, 2005.

Copyright (c) by Ando Ki 7

차례

1. What to do
2. Background
• Semiconductor chip development
• General form of hardware test/verification
• Basic types of tests and verification technologies
• Sim, Accel, Emul, and prototype
3. CON-FMC
• Connect to your FPGA board through USB 3.0
• Programming interfaces
• Simple API: C and C++
• Programming interfaces: AMBA AXI BFM
4. 기본 플랫폼 (basis platform)
• 필요한 패키지들
• 환경 설정 팁
Copyright (c) by Ando Ki
• 기본플랫폼 사용 8

4
 1/19/2025

Connect to your FPGA board through USB 3.0

Host program

Interface User design

CON_FMC
FPGA

LCD
CIS

Copyright (c) by Ando Ki 9

Programming interfaces
 Standard C/C++ interface  Python interface

Python User design

application
Application User design
Python wrapper
(pyconfmc)
CON-FMC API
(conapi)
CON-FMC API
libusb API Firmware (conapi)
(libusb-1.0) (confx3)
CON-FMC board libusb API
Device driver (libusb-1.0)
(usbfs/WinUSB) CON-FMC IF CON-FMC board
Device driver CON-FMC IF
(usbfs/WinUSB)

CON-FMC
FGPA CON-FMC
FGPA

Copyright (c) by Ando Ki 10

10

5
 1/19/2025

Simple API: C and C++

 Minimum code: C  API’s

GNU GCC supporting

Copyright (c) by Ando Ki 11

11

Programming interfaces: AMBA AXI BFM

 Standard C/C++ interface  Python interface

User design with Python User design with

Application AMBA AXI application AMBA AXI
interface interface

BFM AXI API Python module

(pyconbfmaxi)
AMBA AXI

CON-FMC API Python wrapper

(conapi) (pyconfmc)
Firmware
libusb API (confx3) CON-FMC API
(libusb-1.0) CON-FMC board (conapi)
Device driver BFM AXI libusb API
(usbfs/WinUSB) (libusb-1.0)
CON-FMC board
Device driver BFM AXI
(usbfs/WinUSB)

CON-FMC
FGPA
CON-FMC
FGPA

Copyright (c) by Ando Ki 12

12

6
 1/19/2025

Programming interfaces: AMBA AXI BFM

 Minimum code: C  AMBA AXI BFM API’s
void BfmWrite( con_Handle_t handle
#include "conapi.h"
, unsigned int addr
#include "trx_axi_api.h"
, unsigned int *data
, unsigned int size
#define MEM_WRITE(A, B) BfmWrite(handle, (unsigned int)(A), &(B), 4, 1)
, unsigned int length);
#define MEM_READ(A, B) BfmRead (handle, (unsigned int)(A), &(B), 4, 1)
void BfmRead ( con_Handle_t hande
, unsigned int addr
unsigned int card_id=0;
, unsigned int *data
con_Handle_t handle=NULL;
, unsigned int size
, unsigned int length);
int main(int argc, char *argv[]) {
unsigned int addr, dataW, dartR;
conInit(card_id, CON_MODE_CMD, CONAPI_LOG_LEVEL_INFO);
User design with
Application AMBA AXI
MEM_WRITE(addr, dataW); interface

MEM_READ (addr, dataR); BFM AXI API

AMBA AXI
CON-FMC API
(conapi)
conRelease(handle); libusb API
Firmware
(confx3)
return 0; (libusb-1.0) CON-FMC board

} Device driver
(usbfs/WinUSB)
BFM AXI

CON-FMC
FGPA

Copyright (c) by Ando Ki 13

13

차례

1. What to do
2. Background
• Semiconductor chip development
• General form of hardware test/verification
• Basic types of tests and verification technologies
• Sim, Accel, Emul, and prototype
3. CON-FMC
• Connect to your FPGA board through USB 3.0
• Programming interfaces
• Simple API: C and C++
• Programming interfaces: AMBA AXI BFM
4. 기본 플랫폼 (basis platform)
• 필요한 패키지들
• 환경 설정 팁
Copyright (c) by Ando Ki
• 기본플랫폼 사용 14

14

7
 1/19/2025

기본 플랫폼 (basis platform)

 PC
► Ubuntu 20.04 LTS
Memory testing AXI Memory
program ► GCC 9.4.0
AXI bus
BFM AXI
► PyTorch 1.13 with Python 3.10
USB for
communication
 FPGA
Ubuntu CON-FMC
► Avnet ZedBoard
FPGA  Xilinx Zynq-7000 AP SoC XC7Z020-CLG484
JTAG-USB: FPGA ZedBoard
configuration  512MB DDR3
► Xilinx Vivado 2021.2
 Host interface
JTAG-USB ► Future Designs Systems CON-FMC
 USB 3.0

usb host interface

through CON-FMC

Copyright (c) by Ando Ki 15

15

기본 플랫폼 (basis platform)

 Basic platform This uses 256MB out of 512MB.
► BFM: USB-AXI You can add more clocks to improve performance, if you can.
► AXI4-Bus
► BRAM 8KB at 0xC000_0000
► DDR3 256MB at 0x1000_0000
► All runs at 80Mhz

USB BFM BRAM

(8KB @
0xC000_000)
all runs at 80Mhz

AXI4 bus

PS DDR3
(Transpa (256MB @
rent) 0x1000_0000)

Copyright (c) by Ando Ki 16

16

8
 1/19/2025

필요한 패키지들 (1/3)

 Xilinx Vivado 2021.2
⚫ https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools/archive.html
► JTAG USB driver
 Run ‘install_drivers’
⚫ $ cd /tools/Xilinx/Vivado/2018.3/data/xicom/cable_drivers/lin64/install_script/install_drivers
⚫ $ sudo ./install_drivers
 Unplug JTAG-USB cable from the board and plug again
 Check usb
⚫ $ lsusb
❖ Bus 001 Device 004: ID 0403:6014 Future Technology Devices International, Ltd FT232H ....

 Avnet ZedBoard File

► 1. Download Avnet Board File (zedboard directory)
 https://github.com/Avnet/bdf
► 2. Copy 'zedboard' directory to the following.
 /tools/Xilinx/Vivado/2021.2/data/boards/board_files
⚫ zedboard/1.4
❖ board.xml, changelog.txt, part0_pins.xml, preset.xml, zed_board.jpg

Copyright (c) by Ando Ki 17

17

필요한 패키지들 (2/3)

 CON-FMC package
► https://github.com/github-fds/confmc.x86_64.linux.2020.06
► 위 GitHub 사이트의 ‘doc’ 디렉토리 아래 ‘User Manual’ 문서 ‘3. Software installation’ 참고.
 $ git clone https://github.com/github-fds/confmc.x86_64.linux.2020.06
 $ cd confmc.x86_64.linux.2020.06/
 $ sudo ./coninstall.sh [socmgr@soc3w19] make run
./lenet ./images/0.png
libusb: error [_get_usbfs_fd] libusb couldn't open USB device /dev/bus/usb/001/005: Permission denied
 In order to install “libusb” libusb: error [_get_usbfs_fd]
cannot initialize CON-FMC
libusb requires write access to USB device nodes.

./lenet ./images/1.png
► on Ubuntu libusb: error [_get_usbfs_fd] libusb couldn't open USB device /dev/bus/usb/001/005: Permission denied
libusb: error [_get_usbfs_fd] libusb requires write access to USB device nodes.
 $ sudo apt-get install libusb-1.0.0-dev cannot initialize CON-FMC

► Update udev without reboot (to deal with 'permission denied')

 $ sudo udevadm control --reload-rules Deep Learning IP
 $ sudo udevadm trigger Computer
on FPGA through
USB
► connect CON-FMC board and turn on the power
 $ lsusb
⚫ Bus 001 Device 005: ID 04b4:00f3 Cypress Semiconductor Corp.

Copyright (c) by Ando Ki 18

18

9
 1/19/2025

필요한 패키지들 (3/3)

 CON-FMC BFM AXI IF package
► It is required to use CON-FMC BFM AXI IF along with Vivado IP Integrator
► http://www.future-ds.com/en/products.html#CON_FMC
 Follow instructions described in ‘BFM AXI IF’ document

 1. Get 'BFM AXI IF' package for a specific board

 2. Untar 'bfm_axi_if.z7.tar.gz' to CON-FMC directory
⚫ $ tar xvfz bfm_axi_if.z7.tar.gz
⚫ $ sudo tar xvfz bfm_axi_if.z7.tar.gz\ --directory $(CONFMC_HOME)/hwlib/trx_axi/lib
❖ /opt/confmc/2020.06/hwlib/trx_axi/lib/bfm_axi_if.z7
• src, xgui, bfm_axi_if.xpr, component.xml

Do not use Hangul directory name or file name for Vivado project.

Copyright (c) by Ando Ki 19

19

환경 설정 팁
 Add following code in the '.bashrc' at the home directory

set_vivado() { set_confmc() {
if [ -z "$1" ]; then if [ -z "$1" ]; then
version=2021.2 version=2020.06
else else
version=$1 version=$1
fi fi
if [ -f /tools/Xilinx/Vivado/${version}/settings64.sh ]; then if [ -f /opt/confmc/${version}/settings.sh ]; then
source /tools/Xilinx/Vivado/${version}/settings64.sh source /opt/confmc/${version}/settings.sh
else else
echo "Error could not find ${version}" echo "Error could not find ${version}"
return -1 return -1
fi fi
return 0 return 0
} }

Copyright (c) by Ando Ki 20

20

10
 1/19/2025

기본플랫폼 사용
 Directory structure  Make sure following
► Vivado environment ($ set_vivado)
► CON-FMC environment ($ set_confmc)
project_basis_platform
► JTAG-USB connected
hw

Zed.Confmc
► CON-FMC USB connected
xdc
 Building HW and programing the FPGA
► $ cd ....project_basis_platform/hw/Zed.Confmc
► $ make
1 2 3 ► tcl> syn_impl
sw.native Makefile run_vivado.tcl design_axi_ddr.tcl ► ... program FPGA using Hardware manager
test_mem
 Building program and running the program
► $ cd ....project_basis_platform/sw/test_mem
4
► $ make
Makefile
► $ make download compile program
src
► $ make program PS initialize (FSBL)
5
► $ make run
PL programming (BIT)
main.c
Run the program

Copyright (c) by Ando Ki 21

21

References

❑ 기안도, 시스템 집적 반도체 설계검증 환경과 기법, 홍릉과학출판사, 2008.

❑ Chong-Min Kyung, Ando Ki et.al., ‘Chapter: SoC Prototyping and Verification’ in
‘Essential Issues in System-on-a-Chip Design’, edited by Youn-Long Lin, Springer-Verlag,
2006.
❑ D.L. Perry and H.D. Foster, Applied Formal Verification, Chapter 2 Verification process, by
McGraw-Hill, 2005.
❑ D.L. Perry and H.D. Foster, Applied Formal Verification, Chapter 3 Current Verification
Techniques, McGraw-Hill, 2005.

❑ Future Design Systems, CON-FMC API, FDS-TD-2018-04-004, 2018.

❑ Future Design Systems, TRX_AXI: AMBA AXI Transactor for GPIF2MST, FDS-TD-2018-04-
008, 2019.

Copyright (c) by Ando Ki 22

22

11
 1/19/2025

㈜퓨쳐디자인시스템
(34112) 대전광역시 유성구 대덕대로 593 (도룡동386-2,3번지) 대덕테크비즈센터(TBC) 504
호(042) 864-0211 | [email protected] | www.future-ds.com/ko/
Future Design Systems, Inc.
504 TBC (Daedeok Tech Biz Center), 593 DaeDeokDae-Ro, Yuseong-Gu, Daejeon 34112, Korea
+82-042-864-0211 | [email protected] | www.future-ds.com/en/
FUTURE
Design Systems

23

12