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Digital System Laboratory Roll No: - Maximum Marks: 10 Name: Duration: 30 Mins Answer All The Following Questions

The document is a Digital System Laboratory exam with questions related to Verilog HDL code, including output prediction, multiplexer design, and arithmetic operations. It consists of multiple-choice questions and coding tasks, requiring knowledge of digital systems and hardware description languages. The total marks for the exam are 10, and the duration is 30 minutes.

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Kumar Bellikatti
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5 views5 pages

Digital System Laboratory Roll No: - Maximum Marks: 10 Name: Duration: 30 Mins Answer All The Following Questions

The document is a Digital System Laboratory exam with questions related to Verilog HDL code, including output prediction, multiplexer design, and arithmetic operations. It consists of multiple-choice questions and coding tasks, requiring knowledge of digital systems and hardware description languages. The total marks for the exam are 10, and the duration is 30 minutes.

Uploaded by

Kumar Bellikatti
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Digital System Laboratory

Roll No: _ _________________________________ Maximum Marks: 10


Name: Duration: 30 Mins
Answer all the following questions

1. Find the output of the following code


(1M)
Code: -
1| ‘timescale 10 ns / 1 ns
2| module time_test2 ;
3| reg check ;
4| parameter p1 = 1.9999 ;
5| parameter p2 = 0.1 ;
6| initial begin
7| $monitor ( $realtime , ," check = ", check );
8| #p1 check = 0 ;
9| #p1 check = 1 ;
10| #p2 check = 0 ;
11| #p2 check = 1 ;
12| end
13| endmodule

A. #2 check=0
#4 check=1
B. #2 check=0
#4 check=1
#4.1 check=0
#4.2 check=1
C. Error in the code
D. #1 check=0
#2 check=1

2. On successful execution of the following code, what are the values of the following?
A) out1: ________________
B) out2: ________________
(1M)

Code: -

1| module mynet ( output out1 , out2 );

2| wire win1 , win2 , wout1 ;


3| wire w1 ,w2 ,w3 , wout2 ;
4| assign win2 = 1’b0 ;
5| assign win1 = 1’b1 ;
6| assign wout1 = win1 ;
7| assign wout1 = win2 ;
8| assign out1 = wout1 ;
9| // //////////////////////////////////////////////////////
10| assign w3 = 1’b0 ;
11| assign w2 = 1’b0 ;
12| assign w1 = 1’b1 ;
13| assign wout2 = w1 ;
14| assign wout2 = w2 ;
15| assign wout2 = w3 ;
16| assign out2 = wout2 ;
17| endmodule
3. Write Verilog HDL code for 8x1 multiplexer, assume inputs are of N-bit size and the bit-size of each select line is 1-
bit. Input variable names are A0, A1, A2, A3, A4, A5, A6, A7 and select line names are S2, S1, S0; (2M)
4. Write an HDL Verilog code for Y = C + (A*B); assume that the below modules are available in the work directory.
(3M)

Note: Make use of the Add_Nbit and MUL module to write the verilog code for Y= C + (A*B);
5. Write an HDL Verilog code for Y = A*B; where A and B are of 2-bit binary unsigned numbers. (3M)

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