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Important COSS Formula

The document discusses various concepts related to data storage and processing, including RAID levels, cache mapping techniques, and performance metrics like MIPS and Amdahl's Law. It outlines different RAID configurations and their redundancy methods, as well as cache replacement algorithms and pipelining in CPU architecture. Additionally, it touches on the importance of spatial and temporal locality in memory access patterns.

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nilesh jagdale
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3 views5 pages

Important COSS Formula

The document discusses various concepts related to data storage and processing, including RAID levels, cache mapping techniques, and performance metrics like MIPS and Amdahl's Law. It outlines different RAID configurations and their redundancy methods, as well as cache replacement algorithms and pipelining in CPU architecture. Additionally, it touches on the importance of spatial and temporal locality in memory access patterns.

Uploaded by

nilesh jagdale
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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OHamming Co de i

Length o Syndrome wond K-bis, engih o data is M- b5,


k has a Kange behween o b2-1

Mognehc Disk DxN Ci


OAxeal Dnsiby 2 Recoxding-Denaiky x TXack Density
(oits /inch) (bik/inch) Ctacks inch

+(No.o 2anes xSectox size).

x#suxfaces/platux(#platexs/disk)
(U Data frans fe Rat
8yeoce cton x RPS x Sector/track

8) RAID_ Levels
RAIDO - Non -Kedund ant Cstxipping)
RAIDI - MiMoRin
RAID2 - Parallel accas (Redundancy thxough Hamning code)
RAID3 - Parallel access CBit-intole awed paxity
RALDY - Block-level paxity
D5- Blo ck - tevel distxibuted paxity Indapandent acceAs
RALD5-
AALD6 - Dua Redundanc (RAID 4, 5,6 )

Tempoxal Spahal Lo caliyi


Tempoxa: Hoxe'pxo duct andi fox(ia0;i4n,' ie)
Vaxiablea cxhibit g6od tempoxal pro duct =ai:
localihy , as tfese axe xefoencad JeguenHy throughout eXOcuhian.
Spaial: Hexe alil exhiois g00d Spahal Locality aa alamens
o aay all ae acessed sequenially.
H Raho . No. ol his
(#o) hik +#o mis)
access hme Hit aho cache access hme)
+1-hit xaho)(cache t main memoHy
access ime))
-hitxaho miss raio

O Direct Mapping
iajmod m i " cache line numbex
j> main memoy block numbur
m no.o} ines io cache.
Tag Line Wod

Blo ck numben

Line sizeBlock size 2 w Wotd bis


Noo) in Cache si2e (byt),
Cache size (byte, na bih.
Blo ek size

PHain
P memoxy addxess- a Addxuss bik
Tag bik a a-(+w)
>

2 Addxus bits -( Line bikt Word bik)

DAssocìahve Mappingi Wod


Tag

Main memoxy bytes -’azAddxess bik.


8lock site 9 byteo - Wa Woxd bik.
Tag Gik ) a- w2 Addxess bis - loxd biks.

) Set Associahve set Woxd


Mappingi TOA
t
le jmad_ k ie cache set t
J 2Main memoxy blo ck
kYno.o line in a st
y- way st-asso ciahve 2 4 lines/st.
Block sie 2 w Wod bis.
Cache si2e
No. o ines in cach e
Blo ck siee.
e t t e a e No. ol sek, No.o} lino in cache
No. o tinet/set (t way setaasoc
No. o setk
a2 Address bibk.
ATag bit a-(s+)
Addkess bits -(Setbikt Woxdbik)

Al unik ae in byh

J Gh82 byteo, MB» 2byts KB 22 butea.

( Cache Replaeement Alg axilhnsi


RE- Replace the block Tfewex
LFU
that is_ least equenty usd bik
LIE two 0x MOxe pesent, xeplace the o0 that has been
in the cache the longest).
0LRU- Replace the block hat has ke-not been used the longest.
u)ELfo- Replace the block which entued cache earliegt.

Laxqex cache size’ Lowx miss Nate


Smale block si2e ’ Hìghax miss. xate.

(9CeI, MIPS
CeI(yclea/Insfxuchan)> Instxuchon
Count
x Avg #oß elockinstuchon
cycles

CPU hme 2 Instuchon Couht X CPL


Clock ote (H2)

MIPS Clock xate (He) Instuchon count


Execuhon Hme x 10
10 Amdhal's Laus i
1f P is he propoxion o a pxogam that can be
made paxallel and u-D is mhe propott5en that cannot
be paralel;eed (emains seqenhial), hn e max. Speedup
that con be achieved usin

Speed-up >
As N’ o, Max Speedup -P)
CISC Instuchion foxmat i
Opco de SoLxCA OpLMan d Deshnaion opocan d Displacament

O Pipelining
OSpace- Time Diagtami
2 3 q lo
u DI EI
I2 FI DÊ Fo Wo
13 FI DI Fo EL

clock_poxiod ?2 max (T LL uoit 2 us oK clock


ycles.
3 latch delay Cdelay beween tue stage).

) Time taken ta completentaaks by k-stage pipelin


TimA taken by non-pipelined pOCLOSOM -

nk
. . Speed up Su
T E+(n-j k+(n-)
when n’ 0, S ’k
Acual speed up
Ideal speedup.
Sioce,S ’ k when n 0, k is Ideal speedup.
2
nk
k.[k+{n-) k+(n-)

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