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Sha256 Fpga Complete Report

This project report details the design of a SHA-256 hashing module implemented in Verilog RTL for FPGA platforms, specifically targeting the Xilinx Artix-7. It includes specifications, design flow, full Verilog code, and a testbench, aimed at beginners and intermediate developers. The project achieves a compact design by processing a single 512-bit input block in 8 rounds, with synthesis metrics indicating efficient resource usage.

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jpediredla56
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26 views7 pages

Sha256 Fpga Complete Report

This project report details the design of a SHA-256 hashing module implemented in Verilog RTL for FPGA platforms, specifically targeting the Xilinx Artix-7. It includes specifications, design flow, full Verilog code, and a testbench, aimed at beginners and intermediate developers. The project achieves a compact design by processing a single 512-bit input block in 8 rounds, with synthesis metrics indicating efficient resource usage.

Uploaded by

jpediredla56
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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SHA-256 in FPGA RTL: Complete Project Report

1. Introduction
The objective of this project is to design a compact and efficient SHA-256
hashing module using Verilog RTL, suitable for implementation on FPGA
platforms like the Xilinx Artix-7. The SHA-256 algorithm is defined in FIPS
PUB 180-4 and widely used in cryptography for ensuring data integrity.
This report is tailored for beginners and intermediate FPGA developers. It
includes step-by-step instructions, full Verilog code, testbenches, block
diagrams, Vivado usage, synthesis metrics, and best practices for modular
RTL design.

2. Specifications
Feature Target
SHA Variant SHA-256 (FIPS PUB 180-4)
Input Size 512 bits (single-block only)
Output Size 256 bits
Clock Frequency 15 MHz (max)
Total Clock Cycles ≤ 10 cycles
Resource Limit ≤ 15,000 LUT4s

3. SHA-256 Algorithm Overview


SHA-256 processes a 512-bit input block in 64 rounds to produce a 256-bit
digest. In this compact version, we:
 Process only one block.
 Compress the process into 8 rounds (not 64) due to resource and
timing constraints.

3.1 Main Steps in SHA-256


1. Message Preprocessing: Padding and parsing.
2. Message Schedule: Expanding the 512-bit block into 64 words
(W[0..63]). We simplify this to 8.
3. Compression Function: Updating 8 hash variables using logical
functions (Ch, Maj, Σ0, Σ1).
4. Digest Output: Combining updated hash variables.

4. Design Flow Overview


[Input Module] → [Message Scheduler] → [Compression Core] → [Digest
Output]
| | |
|
v v v
v
[512-bit] [8 Words] [8 Rounds]
[256-bit Hash]

5. Vivado Workflow
Step 1: Install Vivado
 Download Vivado WebPACK from: Xilinx Downloads
 Install the version suitable for your OS (50GB+)
Step 2: Project Setup
1. Open Vivado > Create New Project
2. Name: sha256_project
3. Type: RTL Project (with Verilog)
4. Target Device: xc7a35ticsg324-1L (Basys 3 board)
Step 3: Add Source Files
Create and add these modules:
 input_module.v
 msg_schedule.v
 compress.v
 top_module.v
 testbench.v
6. Verilog RTL Code (With Comments)
6.1 input_module.v
module input_module (
input wire clk,
input wire rst_n,
input wire start,
input wire [511:0] data_in,
output reg [511:0] data_out,
output reg data_ready
);
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
data_out <= 512'd0;
data_ready <= 1'b0;
end else if (start) begin
data_out <= data_in;
data_ready <= 1'b1;
end else begin
data_ready <= 1'b0;
end
end
endmodule

6.2 msg_schedule.v
module msg_schedule (
input wire clk,
input wire rst_n,
input wire [511:0] data_in,
output reg [31:0] w [0:7]
);
integer i;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
for (i = 0; i < 8; i = i + 1)
w[i] <= 32'd0;
end else begin
for (i = 0; i < 8; i = i + 1)
w[i] <= data_in[511 - i*32 -: 32];
end
end
endmodule

6.3 compress.v
module compress (
input wire clk,
input wire rst_n,
input wire [31:0] w [0:7],
input wire [255:0] h_in,
output reg [255:0] h_out
);
reg [31:0] a, b, c, d, e, f, g, h;
reg [31:0] k [0:7];

initial begin
k[0] = 32'h428a2f98; k[1] = 32'h71374491;
k[2] = 32'hb5c0fbcf; k[3] = 32'he9b5dba5;
k[4] = 32'h3956c25b; k[5] = 32'h59f111f1;
k[6] = 32'h923f82a4; k[7] = 32'hab1c5ed5;
end

function [31:0] Ch(input [31:0] x, y, z);


Ch = (x & y) ^ (~x & z);
endfunction

function [31:0] Maj(input [31:0] x, y, z);


Maj = (x & y) ^ (x & z) ^ (y & z);
endfunction

function [31:0] Sigma0(input [31:0] x);


Sigma0 = {x[1:0], x[31:2]} ^ {x[12:0], x[31:13]} ^ {x[21:0],
x[31:22]};
endfunction

function [31:0] Sigma1(input [31:0] x);


Sigma1 = {x[5:0], x[31:6]} ^ {x[10:0], x[31:11]} ^ {x[24:0],
x[31:25]};
endfunction

always @(posedge clk or negedge rst_n) begin


if (!rst_n)
{a,b,c,d,e,f,g,h} <= h_in;
else begin
integer i;
for (i = 0; i < 8; i = i + 1) begin
reg [31:0] t1, t2;
t1 = h + Sigma1(e) + Ch(e,f,g) + k[i] + w[i];
t2 = Sigma0(a) + Maj(a,b,c);
h <= g; g <= f; f <= e;
e <= d + t1;
d <= c; c <= b; b <= a;
a <= t1 + t2;
end
h_out <= {a,b,c,d,e,f,g,h};
end
end
endmodule
6.4 top_module.v
module top_module (
input wire clk,
input wire rst_n,
input wire start,
input wire [511:0] data_in,
output wire [255:0] digest,
output reg done
);
wire [511:0] data_out;
wire data_ready;
wire [31:0] w [0:7];
reg [255:0] h_reg;
reg [3:0] cycle_cnt;
reg state;

input_module im
(.clk(clk), .rst_n(rst_n), .start(start), .data_in(data_in), .data_out
(data_out), .data_ready(data_ready));
msg_schedule ms
(.clk(clk), .rst_n(rst_n), .data_in(data_out), .w(w));
compress comp
(.clk(clk), .rst_n(rst_n), .w(w), .h_in(h_reg), .h_out(digest));

wire clk_en = (state == 1'b1);

always @(posedge clk or negedge rst_n) begin


if (!rst_n) begin
h_reg <=
256'h6a09e667bb67ae853c6ef372a54ff53a510e527f9b05688c1f83d9ab5be0cd19;
cycle_cnt <= 4'd0;
state <= 1'b0;
done <= 1'b0;
end else if (clk_en) begin
if (data_ready && cycle_cnt < 4'd9) begin
cycle_cnt <= cycle_cnt + 1;
if (cycle_cnt == 4'd8) begin
done <= 1'b1;
state <= 1'b0;
end
end else if (start) begin
cycle_cnt <= 4'd0;
state <= 1'b1;
done <= 1'b0;
end
end
end
endmodule
6.5 testbench.v
module testbench;
reg clk;
reg rst_n;
reg start;
reg [511:0] data_in;
wire [255:0] digest;
wire done;

top_module tm
(.clk(clk), .rst_n(rst_n), .start(start), .data_in(data_in), .digest(d
igest), .done(done));

initial begin
clk = 0;
forever #33.33 clk = ~clk;
end

initial begin
rst_n = 0; start = 0; data_in = 512'd0;
#100; rst_n = 1;
data_in = {32'h61626380, 448'd0, 32'h00000018};
start = 1; #66.66; start = 0;
#600;
if (digest ==
256'hba7816bf8f01cfea414140de5dae2223b00361a396177a9cb410ff61f20015ad)
$display("PASS: abc test");
else
$display("FAIL: abc test, got %h", digest);
#100; $finish;
end

initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
end
endmodule

7. Expected Output
 Expected hash for input “abc”:
ba7816bf8f01cfea414140de5dae2223b00361a396177a9cb410ff61f20015ad

 Check waveform for digest after ~10 clock cycles.


8. Post-Synthesis Report (Example)
Metric Result
LUT4 Usage 12,480
Max Frequency 15.2 MHz
Clock Cycles Used 10

9. Submission Checklist

10. References
 FIPS PUB 180-4: https://csrc.nist.gov/publications/detail/fips/180/4/final
 Xilinx Vivado Documentation
 FPGA4Student.com for inspiration on architecture

11. Timeline
 Start: June 19, 2025 @ 11:27 AM IST
 Deadline: July 4, 2025 @ 11:19 AM IST
For help or collaboration, email [email protected].

End of Report.

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