Computer Architecture I

Unit 1

Register Transfer Language and Microoperations

Third Stage

Asst.Lec. HAYDER ALI HUSSEIN

Computer Engineering Department/ AL-Farabi University College

 Outline
Looping
• Register transfer language
• Bus and Memory transfers (Three-State Bus Buffers, Memory Transfer)
• Arithmetic Micro-operations
• Logic Micro-operations
• Shift Micro-operations
• Arithmetic logical shift unit
Register transfer language
Section - 3
Register
 Computer Registers are designated by capital letters.
 For example,
 MAR – Memory Address Register
 PC – Program Counter
 IR – Instruction Register
 R1 – Processor Register

𝑅1 7 6 5 4 3 2 1 0
Register R Showing individual bits
15 0 15 8 7 0

𝑅𝟐 PC (H) PC (L)
Numbering of bits Divided into two parts
Register Transfer Language
 Information transfer from one register to  The symbolic notation used to describe the
another is designated in symbolic form by microoperation transfers among registers is
means of a replacement operator is known called a register transfer language.
as Register Transfer.  The term "register transfer" implies the
 The statement availability of hardware logic circuits that
𝑅2 ← 𝑅1 can perform a stated microoperation and
transfer the result of the operation to the
 denotes a transfer of the content of same or another register.
register 𝑅1 into register 𝑅2.
 A register transfer language is a system for
expressing in symbolic form the
R1 1 1 0 1 microoperation sequences among the
registers of a digital module.

R2 1 1 0 1
Register Transfer with Control Function
 Normally, we want the transfer to occur only under a predetermined control condition using
if-then statement.
If (P = 1) then (𝑅2←𝑅1)
 where P is a control signal generated in the control section.
 A control function is a boolean variable that is equal to 1 or 0. The control function is
included in the statement as follows:
𝑃 ∶ 𝑅2 ← 𝑅1
t t+1
Clock
Control P Load
𝑅2
circuit
n
Load
𝑅1
Transfer occurs here
Bus and Memory transfers
Section - 4
Common Bus System for 4 registers
 A typical digital computer has many registers, and paths must
be provided to transfer information from one register to
another. Register A
 The number of wires will be excessive if separate lines are 3 2 1 0
used between each register and all other registers in the
system.
 A more efficient scheme for transferring information between
registers in a multiple-register configuration is a common bus 3 2 1 0 3 2 1 0
system.
Register B Register C
 A bus structure consists of a set of common lines, one for
each bit of a register, through which binary information is
transferred one at a time.
 One way of constructing a common bus system is with
multiplexers.
 The multiplexers select the source register whose binary
information is then placed on the bus.
Common Bus System for 4 registers
4-line
0
S1 common
0 bus
S0 A3 A2 A1 A0

4x1 4x1 4x1 4x1

MUX 3 MUX 2 MUX 1 MUX 0
3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0

D2 C2 B2 A2 D1 C1 B1 A1 D0 C0 B0 A0

D2 D1 D0 C 2 C1 C0 B2 B1 B0 A2 A1 A0

3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0
Register D Register C Register B Register A
Common Bus System for 4 registers
 The construction of a bus system for four registers is explained earlier.
 Each register has four bits, numbered 0 through 3.
 The bus consists of four 4 x 1 multiplexers each having four data inputs, 0 through 3, and two
selection inputs, S1 and S0.
 The diagram shows that the bits in the same significant position in each register are
connected to the data inputs of one multiplexer to form one line of the bus.
 The two selection lines S1 and S0 are connected to the selection inputs of all four
multiplexers.
 The selection lines choose the four bits of one register and transfer them into the four-line
common bus.
 When S1S0 = 00, the 0 data inputs of all four multiplexers are selected and applied to the
outputs that form the bus.
 This causes the bus lines to receive the content of register A since the outputs of this register
are connected to the 0 data inputs of the multiplexers.
Common Bus System for 4 registers
 Table shows the register that is selected by the
bus for each of the four possible binary values of
the selection lines.
 In general, a bus system will multiplex k registers Register
S1 S0
of n bits each to produce an n-line common bus. Selected
 The number of multiplexers needed to construct 0 0 A
the bus is equal to n, the number of bits in each 0 1 B
register.
1 0 C
 The size of each multiplexer must be k x 1 since it
multiplexes k data lines. 1 1 D
 For example, a common bus for eight registers of
16 bits requires
Multiplexers - 16 of (8 x 1)
Select Lines - 3
Tri-state Buffer (3 state Buffer)
 A three-state gate is a digital circuit that exhibits three states.
 Two of the states are signals equivalent to logic 1 and 0 as in a conventional gate.
 The third state is high impedance state which behaves like an open circuit, which means that
the output is disconnected and does not have logic significance.
 The control input determines the output state. When the control input C is equal to 1, the
output is enabled and the gate behaves like any conventional buffer, with the output equal
to the normal input.
 When the control input C is 0, the output is disabled and the gate goes to a high-impedance
state, regardless of the value in the normal input.

Normal Input A Output Y = A if C =1

High-impedance if C = 0

Control Input C
Common Bus System using Decoder and Tri-state Buffer
Bus line for bit 0
A0

B0

C0

D0

0
1
S1
Select 1
0 2x4
S0
Decoder 1
2
Enable E
3
Common Bus System using Decoder and Tri-state Buffer
 The construction of a bus system with three-state buffers is demonstrated in previous figure.
 The outputs of four buffers are connected together to form a single bus line.
 The control inputs to the buffers determine which of the four normal inputs will
communicate with the bus line.
 The connected buffers must be controlled so that only one three-state buffer has access to
the bus line while all other buffers are maintained in a high impedance state.
 One way to ensure that no more than one control input is active at any given time is to use a
decoder, as shown in the figure: Bus line with three state-buffers.
 When the enable input of the decoder is 0, all of its four outputs are 0, and the bus line is in
a high-impedance state because all four buffers are disabled.
 When the enable input is active, one of the three-state buffers will be active, depending on
the binary value in the select inputs of the decoder.
Arithmetic Micro-operations
Section - 5
Arithmetic Microoperations
 Arithmetic microoperations perform arithmetic operations on numeric data stored in
registers.
Symbolic Description
Designation Add Microoperation
𝑅3 ← 𝑅1 + 𝑅2 Contents of 𝑅1 plus 𝑅2 transferred to 𝑅3 𝑅3 ← 𝑅1 + 𝑅2
𝑅3 ← 𝑅1 − 𝑅2 Contents of 𝑅1 minus 𝑅2 transferred to 𝑅3
𝑅2 ← 𝑅2 Complement the contents of 𝑅2 (1’s
complement) Subtract Microoperation
𝑅2 ← 𝑅2 + 1 2’s complement the contents of 𝑅2 (negate) 𝑅3 ← 𝑅1 − 𝑅2
𝑅3 ← 𝑅1 + 𝑅2 + 1 𝑅1 plus the 2’s complement of 𝑅2 (subtraction) 𝑅3 ← 𝑅1 + 𝑅2 + 1
𝑅1 ← 𝑅1 + 1 Increment the content of 𝑅1 by one
𝑅1 ← 𝑅1 − 1 Decrement the content of 𝑅1 by one
4-bit Binary Adder
 The digital circuit that generates the arithmetic sum of two binary numbers of any length is
called a binary adder.
 Example
0 1 1 1 1 0 1 1
B3 A3 B2 A2 B1 A1 B0 A0

1 1 1 0
C 1 1 1 0 C3 C2 C1 C0
FA FA FA FA
R1 1 1 0 1 A
R2 + 0 1 1 1 B
Sum 1 0 1 0 0 C4 S3 S2 S1 S0
1 0 1 0 0
 The binary adder is constructed with full-adder circuits connected in cascade, with the
output carry from one full-adder connected to the input carry of the next full-adder.
 The figure shows the interconnections of four full-adders (FA) to provide a 4-bit binary adder.
 The augends bits of A and the addend bits of B are designated by subscript numbers from
right to left, with subscript 0 denoting the low-order bit.
 The carries are connected in a chain through the full-adders.
 The input carry to the binary adder is C0 and the output carry is C4.
 The S outputs of the full-adders generate the required sum bits.
 An n-bit binary adder requires n full-adders.
 The output carry from each full-adder is connected to the input carry of the next-high-order
full-adder.
 The n data bits for the A inputs come from one register (such as R1), and the n data bits for
the B inputs come from another register (such as R2). The sum can be transferred to a third
register or to one of the source registers (R1 or R2), replacing its previous content.
4-bit Binary Adder-Subtractor
when M = 0 the circuit is an Adder When M = 0, we have When M = 1, we have
when M = 1 the circuit becomes a Subtractor C0 = 0 & B ⊕ 0 = B C0 = 1 & B ⊕ 1 = B’

B3 A3 B2 A2 B1 A1 B0 A0
1 0
1 0 1 0 1 0 1 0 M

B 3’ B3 B 2’ B2 B 1’ B1 B 0’ B0
C3 C2 C1 C0
FA FA FA FA

C4 S3 S2 S1 S0
4-bit Binary Incrementer
 The increment microoperation adds one to a number in a register.
1 1 0 1
A3 A2 A1 A0 1
0 0 1

x y x y x y x y
C 0 0 1
R1 1 1 0 1 HA HA HA HA
+ 1
Sum 1 1 1 0 C S C S C S C S

C4 S3 S2 S1 S0
0 1 1 1 0
4-bit Arithmetic Circuit
 The arithmetic micro operations can be implemented in one composite arithmetic circuit.
 The basic component of an arithmetic circuit is the parallel adder.
 By controlling the data inputs to the adder, it is possible to obtain different types of
arithmetic operations.
 The output of binary adder is calculated from arithmetic sum.
𝑫=𝑨+𝒀+𝑪𝒊𝒏
Decrement using 2’s complement
1 1 1
1 1 0 1 1 1 0 1
1 2’s complement
+ 1 1 1 1 𝑫𝒆𝒄𝒓𝒆𝒎𝒆𝒏𝒕 = 𝑨 + 𝟏𝟏𝟏𝟏 + 𝟎
-
1 1 0 0 1 1 1 0 0
Discard carry
4-bit Arithmetic Circuit
Decremented content of A
D0 D1 D2 D3 Cout
0
C0 C1 C1 C2 C2 C3 C3 C4
FA FA FA FA
X0 Y0 X1 Y1 X2 Y2 X3 Y3
1 1 1 1
4x1 4x1 4x1 4x1
MUX MUX MUX MUX
S1 S0 0 1 2 3 S1 S0 0 1 2 3 S1 S 0 0 1 2 3 S1 S0 0 1 2 3

0 0
Cin A0 B0 A1 B1 A2 B2 A3 B3
1 S 1 S0 1
4-bit Arithmetic Circuit
Hardware implementation consists of:
 4 full-adder circuits that constitute the 4-bit adder and four multiplexers for choosing
different operations.
 There are two 4-bit inputs A and B.
 The four inputs from A go directly to the X inputs of the binary adder. Each of the four inputs
from B is connected to the data inputs of the multiplexers. The multiplexer’s data inputs also
receive the complement of B.
 The other two data inputs are connected to logic-0 and logic-1.
 Logic-0 is a fixed voltage value (0 volts for TTL integrated circuits)
 Logic-1 signal can be generated through an inverter whose input is 0.
 The four multiplexers are controlled by two selection inputs, S1 and S0.
 The input carry Cin goes to the carry input of the FA in the least significant position. The other
carries are connected from one stage to the next.
 4-bit output D0…D3
4-bit Arithmetic Circuit
 When S1S0 = 00
 If Cin = 0 then D = A + B; Add
 If Cin = 1 then D = A + B + 1; Add with carry
 When S1S0 = 01
ഥ; Subtract with borrow
 If Cin = 0 then D = A + B
ഥ + 1; A + 2’s complement of B i.e. A - B
 If Cin = 1 then D = A + B
 When S1S0 = 10
 Input B is neglected and all 0’s are inserted to Y inputs
D = A + 0 + Cin
▪ If Cin = 0 then D = A; Transfer A
▪ If Cin = 1 then D = A + 1; Increment A
 When S1S0 = 11
 Input B is neglected and all 1’s are inserted to Y inputs
D = A - 1 + Cin
▪ If Cin = 0 then D = A - 1; 2’s compliment
▪ If Cin = 1 then D = A; Transfer A
4-bit Arithmetic Circuit
 Arithmetic Circuit Function

S1 S0 Cin Y D = A + Y + Cin Microoperation

0 0 0 B D=A+B Add
0 0 1 B D=A+B+1 Add with carry
0 1 0 B’ D = A + B’ Subtract with borrow
0 1 1 B’ D = A + B’ + 1 Subtract
1 0 0 0 D=A Transfer
1 0 1 0 D=A+1 Increment A
1 1 0 1 D=A–1 Decrement A
1 1 1 1 D=A Transfer A
Logic Micro-operations
Section - 6
Logic Microoperations
 Logic micro operations specify binary operations for strings of bits stored in registers.
 These operations consider each bit of the register separately and treat them as binary
variables.
 Example

𝑃: 𝑅1 ← 𝑅1 ⨁ 𝑅2

R1 1 0 1 0
R2 ⨁ 1 1 0 0
R1 after P = 1 0 1 1 0
Logic Microoperations

Boolean Microoperation Name

Boolean Microoperation Name Function
Function 𝐹8 = (𝑥 + 𝑦)′ 𝐹 ←𝐴∨𝐵 NOR
𝐹0 = 0 𝐹←0 Clear
𝐹9 = (𝑥 ⊕ 𝑦)′ 𝐹 ←𝐴⊕𝐵 Exclusive-NOR
𝐹1 = 𝑥𝑦 𝐹 ←𝐴⋀𝐵 AND
𝐹10 = 𝑦′ 𝐹 ← 𝐵ത Complement B
𝐹2 = 𝑥𝑦′ 𝐹 ← 𝐴 ⋀ 𝐵ത
𝐹3 = 𝑥 𝐹←𝐴 Transfer A 𝐹11 = 𝑥 + 𝑦′ 𝐹 ← 𝐴 ∨ 𝐵ത

𝐹4 = 𝑥′𝑦 𝐹 ← 𝐴ҧ ⋀ 𝐵 𝐹12 = 𝑥′ 𝐹 ← 𝐴ҧ Complement A

𝐹5 = 𝑦 𝐹←𝐵 Transfer B 𝐹13 = 𝑥′ + 𝑦 𝐹 ← 𝐴ҧ ∨ 𝐵
𝐹6 = 𝑥 ⊕ 𝑦 𝐹 ← 𝐴 ⊕ 𝐵 Exclusive-OR 𝐹14 = (𝑥𝑦)′ 𝐹 ←𝐴∧𝐵 NAND
𝐹7 = 𝑥 + 𝑦 𝐹 ←𝐴∨𝐵 OR 𝐹15 = 1 𝐹 ← 𝑎𝑙𝑙 1′ s Set to all 1’s
Hardware Implementation of Logic Circuit

S1
S0 S1 S0 Output Operation
Ai 0 0 𝐸 =𝐴 ∧𝐵 AND
0
Bi
4x1 0 1 𝐸 = 𝐴 ∨ 𝐵 OR
1 Ei
MUX 1 0 𝐸 =𝐴⨁𝐵 XOR

2 1 1 𝐸 = 𝐴ҧ Complement

3
Applications of Logic Microoperations
1. Selective Set Operation
 The selective-set operation sets to 1 the bits in register A where there are corresponding 1's
in register B.
 It does not affect bit positions that have 0's in B.
 The OR microoperation can be used to selectively set bits of a register.

1 0 1 0 A before

1 1 0 0 B (logic operand)

1 1 1 0 A after
Applications of Logic Microoperations
2. Selective Complement Operation
 The selective-complement operation complements bits in register A where there are
corresponding 1's in register B.
 It does not affect bit positions that have 0's in B.
 The exclusive - OR microoperation can be used to selectively set bits of a register.

1 0 1 0 A before

1 1 0 0 B (logic operand)

0 1 1 0 A after
Applications of Logic Microoperations
3. Selective Clear Operation
 The selective-clear operation clears to 0 the bits in register A only where there are
corresponding 1's in register B.
 It does not affect bit positions that have 0's in B.
 The corresponding logic microoperation is A ← A ∧ B’.

1 0 1 0 A before

1 1 0 0 B (logic operand)

0 0 1 0 A after
Applications of Logic Microoperations
4. Mask Operation
 The mask operation is similar to the selective-clear operation except that the bits of register
A are cleared only where there are corresponding 0’s in register B.
 The mask operation is an AND microoperation.

1 0 1 0 A before

1 1 0 0 B (logic operand)

1 0 0 0 A after
Applications of Logic Microoperations
5. Insert Operation
 The insert operation inserts a new value into a group of bits.
 This is done by first masking and then ORing them with required value.
 The mask operation is an AND microoperation and the insert operation is an OR
microoperation.

Mask Insert
A 0110 1010 A 0000 1010
B 0000 1111 B 1001 0000
A 0000 1010 A 1001 1010
Applications of Logic Microoperations
6. Clear Operation
 The clear operation compares the words in register A and register B and produces an all 0’s
result if the two numbers are equal.
 This operation is achieved by an exclusive-OR microoperation.

1 0 1 0 A

1 0 1 0 B

0 0 0 0 A←A⊕B
Shift Micro-operations
Section - 7
Shift Microoperations
 Shift microoperations are used for serial transfer of data.
 Used in conjunction with arithmetic, logic and other data processing operations.
 The content of the register can be shifted to the left or the right.
 The first flip-flop receives its binary information from the serial input.
 The information transferred through the serial input determines the type of shift.

Types of
Shift

Logical Circular Arithmetic

Types of Shift
1. Logical Shift
 A logical shift is one that transfers 0 through the serial input.

shl - logical shift left shr - logical shift right

R1 1 1 0 1 R1 1 1 0 1

R1 1 0 1 0 R1 0 1 1 0
Types of Shift
2. Circular Shift
 A circular shift (also known as a rotate operation) circulates the bits of the register around
the two ends without loss of information.
 This is accomplished by connecting the serial output of the shift register to its serial input.

cil - circular shift left cir - circular shift right

R1 1 1 0 1 R1 1 1 0 1

R1 1 0 1 1 R1 1 1 1 0
Types of Shift
3. Arithmetic Shift
 An arithmetic shift is a micro-operation that shifts a signed binary number to the left or
right.
 An arithmetic shift-left multiplies a signed binary number by 2.
 An arithmetic shift-right divides the number by 2.
ashl - arithmetic shift left ashr - arithmetic shift right

R1 1 1 0 1 R1 1 1 0 1

R1 1 0 1 0 R1 1 1 1 0
4 - bit Combinational Circuit Shifter
0 – Shift right
Select 1 – Shift left
0
S 0 H0
IR 0 MUX
1
1
A0
1 S H0 H1 H2 H3
A1 S
1 H1
0 0 MUX 0 IR A0 A1 A2
A2 1
1 1 A1 A2 A3 IL
A3 S 1 H2
0 MUX
1

S
0 MUX
0 H3
IL 1
4 - bit Combinational Circuit Shifter
 The 4-bit shifter has four data inputs, A0 through A3 and four data outputs, H0 through H3.
 There are two serial inputs, one for shift left (IL) and the other for shift right (IL).
 When the selection input S = 0, the input data are shifted right (down in the diagram).
 When S = 1, the input data are shifted left (up in the diagram).
 The two serial inputs can be controlled by another multiplexer to provide the three possible
types of shifts.
Arithmetic logical shift unit
Section - 8
4 - bit Arithmetic Logic Shift Unit
 Instead of having individual registers performing the micro operations directly, computer
systems employ a number of storage registers connected to a common operational unit
called an arithmetic logic unit, abbreviated ALU.
 To perform a microoperation, the contents of specified registers are placed in the inputs of
the common ALU.
 The ALU performs an operation and the result of the operation is then transferred to a
destination register.
 The arithmetic, logic, and shift circuits introduced in previous sections can be combined into
one ALU with common selection variables.
4 - bit Arithmetic Logic Shift Unit
S3
S2
S1 Ci
S0
One stage of Di
arithmetic
circuit
Select

0 4x1 Fi
Ci +1 1 MUX
2
3
One stage of Ei
Bi logic circuit
Ai
Ai-1 shr
Ai+1 shl
4 - bit Arithmetic Logic Shift Unit

S3 S2 S1 S0 Cin Operation Function S3 S2 S1 S0 Cin Operation Function

0 0 0 0 0 F=A Transfer A 0 0 1 1 1 F=A Transfer A
0 0 0 0 1 F=A+1 Increment A 0 1 0 0 x F=𝐴⋀𝐵 AND
0 0 0 1 0 F=A+B Addition 0 1 0 1 x F=𝐴∨𝐵 OR
0 0 0 1 1 F=A+B+1 Add with 0 1 1 0 x F = A ⊕B XOR
carry
Subtract with
0 0 1 0 0 F = A + B’ 0 1 1 1 x F = A’ Complement A
borrow
1 0 x x x F = shr A Shift right A into
0 0 1 0 1 F = A + B’ + 1 Subtraction FShift left A into F
1 1 x x x F = shl A
0 0 1 1 0 F=A–1 Decrement
Questions asked in GTU exam
1. What do you mean by register transfer? Explain in detail. Also discuss three-state bus buffer.
2. List and explain types of shift operations on accumulator.
3. Define RTL. Explain how register transfer takes place in basic computer system
4. What is multiplexing? Explain the multiplexing of control signals in ALU.
5. Explain how complement number system is useful in computer system. Discuss any one
complement number system with example.
6. Draw the block diagram of 4-bit arithmetic circuit and explain it in detail.
7. Explain shift micro operations and Draw neat and clean diagram for 4-bit combinational circuit
shifter.
8. Explain hardware implementation of common bus system using three state buffers. Mention
assumptions if required.
9. Explain 4-bit adder-subtractor with diagram.
10. Explain floating point representation.
11. What is a Digital Computer System? Explain the role of binary number system in it.
12. Design a digital circuit for 4-bit binary adder.
Questions asked in GTU exam
13. Represent (8620)10 in (1) binary (2) Excess-3 code and (3) 2421 code.
14. Explain selective set, selective complement and selective clear.
15. How negative integer number represented in memory? Explain with suitable example.
16. Explain Micro operation.
17. What does this mean: R2 ← R1?
18. What does this mean: T0: R4 ← R0?
19. What is a Bus?
20. What is an ALU?
21. Represent the following conditional control statement(s) by two register transfer
statements with control function. If (P=1) then (R1 ← R2) else if (Q=1) then (R1 ← R3)
22. State true or false: In binary number system, B - A is equivalent to B + A' + 1.
23. Draw a diagram of 4-bit binary incrementer and explain it briefly.