CHAPTER 7

Processor Structure and Function:

Central Processing Unit (CPU)
 Topics
7.1) CPU Structure
7.2) Register Structure
7.3) Instruction Cycle
7.1) CPU Structure
Its function is to control the operation of the computer and
performs its data processing functions.

CPU

Computer Arithmetic
Registers and
I/O Logic Unit
System CPU
Bus
Internal CPU
Memory Interconnection

Control
Unit

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 CPU

Arithmetic • Early days – single CPU

Registers and • Modern days – increasing
Logic Unit
use of multiple processors
in a single computer
Internal CPU
Interconnection • CPU 3 basic components:
 Control unit
 Arithmetic and logic
Control
Unit
unit (ALU)
 Registers

The Central Processing Unit (CPU)

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 Structure – the control unit
CPU

Arithmetic
Registers and
Logic Unit

Internal CPU Controls the movement

Interconnection of data and instructions
into and out of the CPU
and control the
Control
Unit operation of the ALU
and the computer as a
whole.

The Central Processing Unit (CPU)

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 Control Unit
 Several approaches to the
implementation of the
Sequencing
Logic control unit.
 Most commonly used is
microprogrammed
Control Unit
Registers and implementation
Decoders  Microprogrammed control
unit operates by executing
microinstructions that define
Control
Memory
the functionality of the
control unit.
 Figure shows the structure of
control unit.

• Microprogram - a sequence of microinstruction

• Microinstruction – an instruction that controls data flow and sequencing in a
processer

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 Structure – the ALU
CPU
Performs
computer data
Arithmetic
Registers and
Logic Unit
processing
Internal CPU functions
Interconnection

Control
Unit

The Central Processing Unit (CPU)

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 7.2) Register Structure
CPU
• As a temporary storage in
Arithmetic CPU
Registers and • Also known as high speed
Login Unit
memory
Internal CPU • Its function is to
Interconnection temporarily hold data and
instructions that are taken
from other components
Control (example MM, I/O U,
Unit
cache etc) to be
processed in the CPU.

The Central Processing Unit (CPU)

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The registers in the processor perform 2 roles:

1. User-visible registers – enable the machine- or

assembly language programmer to minimize main
memory references by optimizing use of registers. (will
be discussed in chapter 8-9)

2. Control and status registers – used by the control

unit to control the operation of the processor and by
privileged, operating system program to control the
execution of program.
(eg: PC, MAR, MBR and IR)

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 Figure illustrates top
level view of
computer
components and
suggests the
interactions among
them.

Computer Components: Top-Level View

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7.3) Instruction Cycle

 The function of computers is to execute programs.

 Programs comprise a set of instructions and data
that is stored in the main memory.
 Every instruction will be taken and executed by the
CPU one by one until all of them are executed.

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Instruction Cycle (cont.)
The process of executing a single instruction is called
Instruction Cycle which can be divided into:
1. Fetch Cycle
read the next instruction from MM into the CPU.
Operation code (to
2. Execute Cycle represent the operation)

interpret the opcode and perform the indicated operation.

Basic Instruction Cycle

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 fetch

execute

fetch
Fetch Cycle
 The process of fetching an instruction from MM into the
CPU
 4 registers are involved:
i. PC (Program Counter)
- Temporary hold the address of an instruction (in MM) that
has to be fetched and executed in the CPU
ii. MAR (Memory Address Register)
- A register that connected to the MM through the address bus.
- Temporary hold the address of an instruction from the PC.
- The content in PC will be transferred into the MAR and then
to the address bus and to the location in MM that pointed by
the address given.

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iii. MBR (Memory Buffer Register)
- A register that connected to the MM through the data bus
- Used to temporary hold instruction or data taken from the MM or
data that will be moved into the MM or other computer components
after being processed by the CPU.

iv. IR (Instruction Register)

- Used to temporary hold instruction (operation code) before it is
being decoded by the Instruction
Decoder inside the control unit.

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Generally the process in the
Fetch Cycle can be depicted by:
MAR ← PC (specify address in MM for
the next read/write)
MBR ← M (MAR) (data to be
written/received from memory)
PC ← PC + 1 (hold address to be
fetched next. CPU increment the PC after
each instruction)
IR ← (MBR) (fetched instruction is
loaded into register)

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Address of the Connected to MM
instruction MAR  PC
PC PC+1

Address bus

Data bus

Hold instruction
before it is
decoded Hold
IR (MBR) instruction/data
taken from MM to
be written to MM
MBR  M(MAR)
Execute Cycle
 The process of executing the instruction that has been fetched
earlier in fetch cycle.

 The followings are steps that are involve in execute cycle:

1. Instruction decoding (to determine the operation that has
to be performed by the CPU)
2. Operand (data) fetching
3. Data Processing
4. Store Result

 The sequences of operations that happen in execution cycle

differ according to the type of instruction.

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 2
1 ALU
X (Data) 3
(Data) R1

MM CPU

Example: ADD R1, X

This instruction adds the content in the R1
register with the content in the MM at location
X and the result is stored in the R1 register, i.e.:
R1 ← R1 + M (X)
(Observe the diagram above)

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 Before the addition operation is performed in the ALU, the
required data is taken and moved into a register in the CPU
 The data in R1 is already in the CPU (R1 is one of the
registers in CPU)
 The addition operation is performed in ALU and the result is
stored in the R1 register

 The process which takes place in the Execution Cycle for

instruction ADD R1,X can be depicted by:
MAR ← IR (address X)
MBR ← M (MAR)
R1 ← R1 + MBR

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 Instruction Cycle State Diagram
• A more detailed look at the basic instruction cycle.
• The figure is in the form of a state diagram.
• For any given instruction cycle, some states may be null
and others may be visited more than once.

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Example of Program Execution Increment
Load (next
data from instruction)
address
940
A single
register
MAR
MBR Load data to
Accumulator
(AC)

Add with
the
contents
of 941

Add

Store in
941

store
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Exercise
Main Memory

0001 Load AC from I/O device 5

0010 Add contents in AC with data from address 940
0011 Store AC to I/O device 6
0100 …
.
.
.
940 2

I/O Module

device 5 device 6
3
.
.
.