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Day 1

The document contains Verilog HDL code for a simple module named 'top_module' that assigns inputs to outputs. It also includes a test bench 'top_module_tb' that simulates various input combinations and monitors the output values over time. The simulation runs through all possible combinations of three binary inputs (a, b, c) and displays the corresponding outputs (w, x, y, z).

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gireshramg
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6 views2 pages

Day 1

The document contains Verilog HDL code for a simple module named 'top_module' that assigns inputs to outputs. It also includes a test bench 'top_module_tb' that simulates various input combinations and monitors the output values over time. The simulation runs through all possible combinations of three binary inputs (a, b, c) and displays the corresponding outputs (w, x, y, z).

Uploaded by

gireshramg
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Day 1:

Verilog HDL Code:

module top_module(input a,b,c, output w,x,y,z);

assign w=a;

assign x=b;

assign y=b;

assign z=c;

endmodule

Test Bench Code:

module top_module_tb;

reg a, b, c;

wire w, x, y, z;

top_module uut (

.a(a),

.b(b),

.c(c),

.w(w),

.x(x),

.y(y),

.z(z)

);

initial begin

$monitor("Time=%0t | a=%b b=%b c=%b | w=%b x=%b y=%b z=%b",

$time, a, b, c, w, x, y, z);

a = 0; b = 0; c = 0; #10;
a = 0; b = 0; c = 1; #10;

a = 0; b = 1; c = 0; #10;

a = 0; b = 1; c = 1; #10;

a = 1; b = 0; c = 0; #10;

a = 1; b = 0; c = 1; #10;

a = 1; b = 1; c = 0; #10;

a = 1; b = 1; c = 1; #10;

$finish;

end

endmodule

Results:

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