Dr.

Subhasish Mahapatra
Sr. Assistant Professor
School of Electronics Engineering (SENSE)
VIT-AP University
E-Mail: [email protected]
 CONTENT

 Interrupt

Dr. Subhasish Mahapatra

Sr. Assistant Professor, SENSE
8085 and 8086 Microprocessors 2
Dr. Subhasish Mahapatra
Sr. Assistant Professor, SENSE
8085 and 8086 Microprocessors 3
 INTERRUPT

 Interrupt is a process where an external device can get the attention of the microprocessor.

 The process starts from the I/O device

 The process is asynchronous

 Interrupts can be classified into two types:

 Maskable (can be delayed)

 Non-Maskable (can not be delayed)

 Interrupts can also be classified into:

 Vectored (the address of the service routine is hard-wired)

 Non-vectored (the address of the service routine needs to be supplied externally)

Dr. Subhasish Mahapatra

Sr. Assistant Professor, SENSE
8085 and 8086 Microprocessors 4
 INTERRUPT

 The 8085 has 5 interrupt inputs

 INTR input
Interrupt
 The INTR input is the only non-vectored interrupt Maskable Vectored
name
 INTR is maskable using the EI/DI instruction pair INTR Yes No
 RST 5.5, RST 6.5, RST 7.5 are all automatically RST 5.5 Yes Yes
RST 6.5 Yes Yes
vectored
RST 7.5 Yes Yes
 RST 5.5, RST 6.5, and RST 7.5 are all maskable TRAP No Yes
 TRAP is the only non-maskable interrupt in the
8085
 TRAP is also automatically vectored

Dr. Subhasish Mahapatra

Sr. Assistant Professor, SENSE
8085 and 8086 Microprocessors 5
 INTERRUPT

 When the Microprocessor receives an interrupt signal, it suspends the currently executing
program and jumps to an Interrupt Service Routine (ISR) to respond to the incoming
interrupt.

 Each interrupt will most probably have its own ISR.

 Responding to an interrupt may be immediate or delayed depending on whether the

interrupt is maskable or non-maskable and whether interrupts are being masked or not.

 There are two ways of redirecting the execution to the ISR depending on whether the
interrupt is vectored or non-vectored.
 The vector is already known to the Microprocessor
 The device will have to supply the vector to the Microprocessor

Dr. Subhasish Mahapatra

Sr. Assistant Professor, SENSE
8085 and 8086 Microprocessors 6
 INTERRUPT

Interrupt Vectors and the Vector Table

 An interrupt vector is a pointer to where the ISR is stored in memory.
 All interrupts (vectored or otherwise) are mapped onto a memory area called the Interrupt
Vector Table (IVT).
 The IVT is usually located in memory page 00 (0000H- 00FFH).
 The purpose of the IVT is to hold the vectors that redirect the microprocessor to the
right place when an interrupt arrives.
 The IVT is divided into several blocks. Each block is used by one of the interrupts to hold
its “vector”

Dr. Subhasish Mahapatra

Sr. Assistant Professor, SENSE
8085 and 8086 Microprocessors 7
 INTERRUPT

Non-Vectored Interrupt Process

1. The interrupt process should be enabled using the EI instruction.
2. The 8085 checks for an interrupt during the execution of every instruction.
3. If there is an interrupt, the microprocessor will complete the executing instruction, and start a
RESTART sequence.
4. The RESTART sequence resets the interrupt flip flop and activates the interrupt acknowledge signal
(INTA).
5. Upon receiving the INTA signal, the interrupting device is expected to return the op-code of one of the 8
RST instructions.
6. When the microprocessor executes the RST instruction received from the device, it saves the address of
the next instruction on the stack and jumps to the appropriate entry in the Interrupt Vector Table (IVT).

Dr. Subhasish Mahapatra

Sr. Assistant Professor, SENSE
8085 and 8086 Microprocessors 8
 INTERRUPT

Non-Vectored Interrupt Process

6. The IVT entry must redirect the microprocessor to the actual service
routine.
7. The service routine must include the instruction EI to re-enable the
interrupt process.
8. At the end of the service routine, the RET instruction returns
the execution to where the program was interrupted.

 The 8085 recognizes 8 RESTART instructions: RST0 - RST7.

 each of these would send the execution to a predetermined hard-
wired memory location

Dr. Subhasish Mahapatra

Sr. Assistant Professor, SENSE
8085 and 8086 Microprocessors 9
 INTERRUPT

Multiple Interrupts & Priorities

 The microprocessor can only respond to one signal on INTR at a time.
 Therefore, the signal from only one of the devices is allowed to reach the microprocessor.
 It is required to assign some priority to the different devices and allow their signals to reach
the microprocessor according to the priority.
 The solution is to use a circuit called the priority encoder (74366).
 This circuit has 8 inputs and 3 outputs.
 The inputs are assigned increasing priorities according to the increasing index of the input.
 Input 7 has highest priority and input 0 has the lowest.
 The 3 outputs carry the index of the highest priority active input.

Dr. Subhasish Mahapatra

Sr. Assistant Professor, SENSE
8085 and 8086 Microprocessors 10
 INTERRUPT

Multiple Interrupts & Priorities

Dr. Subhasish Mahapatra

Sr. Assistant Professor, SENSE
8085 and 8086 Microprocessors 11
 INTERRUPT

8085 Maskable/Vectored Interrupts

 The 8085 has 3 Masked/Vectored interrupt inputs: RST 5.5, RST 6.5, RST 7.5
 They are all maskable.
 They are automatically vectored according to the following table:

 The vectors for these interrupts fall in between the vectors of RST instructions. That is why, the
name is RST 5.5 (between RST 5 and RST 6).
 RST 7.5 is positive edge sensitive. RST 6.5 and RST 5.5 are level sensitive.

Dr. Subhasish Mahapatra

Sr. Assistant Professor, SENSE
8085 and 8086 Microprocessors 12
 INTERRUPT

RST 5.5, RST 6.5, RST 7.5

 These three interrupts are masked at two levels:
 Through the Interrupt Enable flip flop and
the EI/DI instructions.
 The interrupt Enable flip flop controls the
whole maskable interrupt process.
 Through individual mask flip flops that
control the availability of the individual
interrupts.
 These flip flops control the interrupts
individually.

Dr. Subhasish Mahapatra

Sr. Assistant Professor, SENSE
8085 and 8086 Microprocessors 13
 INTERRUPT

8085 Maskable/Vectored Interrupt Process

1. The interrupt process should be enabled using the EI instruction.
2. The 8085 checks for an interrupt during the execution of every instruction.
3. If there is an interrupt, and if the interrupt is enabled using the interrupt mask, the microprocessor
will complete the executing instruction, and reset the interrupt flip flop.
4. The microprocessor then executes a call instruction that sends the execution to the appropriate
location in the interrupt vector table.
5. When the microprocessor executes the call instruction, it saves the address of the next instruction
6. on the stack and jumps to the specific service routine. The service routine must include EI
instruction to re-enable the interrupt process.
7. At the end of the service routine, the RET instruction returns the execution where the program was
interrupted.

Dr. Subhasish Mahapatra

Sr. Assistant Professor, SENSE
8085 and 8086 Microprocessors 14
 INTERRUPT

SIM (Set Interrupt Mask) Instruction

Dr. Subhasish Mahapatra

Sr. Assistant Professor, SENSE
8085 and 8086 Microprocessors 15
 INTERRUPT

Example: Set the interrupt masks so that RST 5.5 is enabled, RST 6.5 is masked, and RST 7.5 is
enabled.
 First, determine the contents of the accumulator

Dr. Subhasish Mahapatra

Sr. Assistant Professor, SENSE
8085 and 8086 Microprocessors 16
 INTERRUPT

RIM Instruction

Dr. Subhasish Mahapatra

Sr. Assistant Professor, SENSE
8085 and 8086 Microprocessors 17
 INTERRUPT

RIM Instruction
 Since the 8085 has five interrupt lines, interrupts may occur during an ISR and remain
pending.
 Using the RIM instruction, the programmer can read the status of the interrupt lines and
find if there are any pending interrupts.
 The advantage is being able to find about interrupts on RST 7.5, RST 6.5, and RST 5.5 without
having to enable low level interrupts like INTR.

Dr. Subhasish Mahapatra

Sr. Assistant Professor, SENSE
8085 and 8086 Microprocessors 18
 INTERRUPT

RIM Instruction:

 Read Interrupt Mask

 Load the accumulator with an 8-bit pattern showing the status of each interrupt pin and mask.

Dr. Subhasish Mahapatra

Sr. Assistant Professor, SENSE
8085 and 8086 Microprocessors 19
 INTERRUPT

Example: Set the mask to enable RST 6.5 without modifying the masks for RST 5.5 and RST 7.5.

Dr. Subhasish Mahapatra

Sr. Assistant Professor, SENSE
8085 and 8086 Microprocessors 20
 INTERRUPT

TRAP
 TRAP is the only non-maskable Interrupt.
 It does not need to be enabled because it can not be disabled.
 It has the highest priority amongst interrupts.
 It is edge and level sensitive.
 It needs to be high and stay high to be recognized.
 Once it is recognized, it won't be recognized again until it goes low, then high again.
 TRAP is usually used for power failure and emergency shutoff.

Dr. Subhasish Mahapatra

Sr. Assistant Professor, SENSE
8085 and 8086 Microprocessors 21
 INTERRUPT

Internal Interrupt Priority

 Internally, the 8085 implements an interrupt priority scheme.
– The interrupts are ordered as follows:
 TRAP
 RST 7.5
 RST 6.5
 RST 5.5
 INTR
– However, TRAP has lower priority than the HOLD signal used for DMA.

Dr. Subhasish Mahapatra

Sr. Assistant Professor, SENSE
8085 and 8086 Microprocessors 22
 INTERRUPT

Dr. Subhasish Mahapatra

Sr. Assistant Professor, SENSE
8085 and 8086 Microprocessors 23
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Dr. Subhasish Mahapatra

Sr. Assistant Professor, SENSE
8085 and 8086 Microprocessors 24