SAMI 2018 • IEEE 16th World Symposium on Applied Machine Intelligence and Informatics • February 7-10 • Košice, Herl’any,

Slovakia

Hardware Design of Cryptographic Accelerator

Michal Huliþ, Liberios Vokorokos, Norbert Ádám, Peter FeciĐak
Department of Computers and Informatics, Faculty of Electrical Engineering and Informatics,
Technical University of Košice, Letná 9, 042 00 Košice, Slovak Republic,
E-mail: {michal.hulic, liberios.vokorokos, norbert.adam, peter.fecilak}@tuke.sk

Abstract — The goal of this paper is representation of the applications for e-passport [7], the hardware
computing unit focused on implementation hardware implementation of this algorithm on the development
cryptography accelerator. After analysis of assigned boards according to [8] and [9], or the implementation of
problem, there are next chapters dedicated to available the RSA algorithm using the Chinese remainder theorem,
solutions, comparison of them, the issues of cryptography on parallel architecture [10]. This article discusses the
and computer security, FPGA device in which the designed implementation of the RSA algorithm in the FPGA chip
solution is verified and tested, the chapters dedicated to and thus contributes to the widening of the application
cryptography algorithm RSA. Chapters of synthesis have possibilities of this algorithm [11].
the specifically implemented and designed solution in In the following chapters, the hardware implementation
programming languages of lower and higher level. In
of RSA algorithm is approached. The description of RSA
evaluation and conclusion chapter there are measurements
algorithm and FPGA device is presented in the second
on software and hardware level and comparison among
chapter. The next three chapters deals with the design of
them.
cryptography accelerator. The achieved results and their
comparison to the results of the similar project are located
I. INTRODUCTION in the final evaluation.
Cryptography is based on unidirectional mathematical II. RSA ALGORITHM
functions. The characteristic feature of which is that they
allow a fairly fast encryption of the input and guarantee The RSA algorithm was published in 1978 by three
that decryption of the message is a process of authors. Ron Rivest, Adi Shamir and Leonard Adleman
computationally demanding (and with certain encryption have designed an algorithm as an asymmetric cipher,
conditions - impossible). Well-known cryptographic which is based on Euler's formula, and which is usable
algorithms are DES, 3DES, IDEA, AES or Diffie- both for encrypting messages and for signing documents.
Hellman, El Gamal and RSA algorithms (initials Rivest, Encryption proceeds as follows. Anyone wanting to
Shamir, Adleman) [1] [2]. send a private message M to another user encrypts
The first four mentioned algorithms belong to a group (enciphers) the message before transmitting it by
of symmetric ciphers. The principle of symmetric recipient’s public key. The message could be send over an
encryption is that both the sender and the recipient of the unsecured network, such as the Internet. Anyone who was
message share the secret key to which the message was "eavesdropping" on the communication would only see
encrypted by the sender and the recipient decrypts it. It is the encrypted message. Because they would not know
clear that prior to the first exchange of messages, the how to decrypt it successfully, the message would make
partners must agree on a common secret key, either by no sense to them. As such, privacy can be ensured in
way of a personal meeting or by sending it through a electronic communication. The recipient uses own private
credible secure channel. DES (Data Encryption Standard) key to decrypt the message from sender [1].
algorithm was patented in December 1976 in the US.
A. The process of creating public and private key
Although the DES cipher was broken in 1993 [3], it is
still possible to find the application of this algorithm. The 1) Two randomly generated large different prime
advantage of this algorithm is the possibility of hardware numbers p, q are selected.
implementation as it is presented in publications [4], [5].
2) Calculate
The second group of mentioned cryptographic
algorithms belong to the group called asymmetric
algorithms. The RSA algorithm is one of the most n = p×q (1)
widespread public key algorithms. The name was given by
the authors - Ron Rivest, Adi Shamir and Leonard
Adleman, who created their algorithm in 1977. The RSA 3) Calculate
algorithm can be used for both encryption and digital
signatures. Two large prime numbers are randomly
generated by the RSA, from which the public key is φ (n) = (p - 1)(q - 1) (2)
deduced during the calculation process. From this, the
private key is calculated by the mathematical operation.
RSA encryption with a key less than 1024 bit is not 4) A random integer is selected
considered safe anymore [6].
The implementation of the RSA algorithm on the 1 < e < φ ( n) where GCD (e, φ ( n)) = 1 (3)
FPGA device is also widely applied as demonstrated by

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 M. Huliþ et al. • Hardware Design of Cryptographic Accelerator

5) Calculate exponentially inverse to e mod ij(n). By recognizing the

numbers p and q it is possible to calculate ij(n). From this
1 < d < φ ( n) where ed ≡ 1 (mod φ ( n)) (4) title it is a priority for the attacker to factorize the number
n to reveal the numbers p and q. However, large-number
6) The public and private key becomes Public key factoring is computationally challenging, and the best-
represents (n, e), the private key represents (n, d). suited algorithms are very slow [16]. Brute force attack is
also less effective than factorization [17][18]. However, if
It is absolutely crucial that the integers p and q for an attacker knows the message context M, it can encrypt
safety reasons are generated, different, random and a public key e and if it matches, the attacker can detect
sufficiently large primes for the subsequent factoring the original message M. To find if the given p and q
attempt. It is also necessary to perform the test if the numbers are correct prime numbers, are verified by the
numbers are prime numbers according to the respective Fermat theorem and the Rabin-Miller algorithm. RSA is
algorithm [12]. In the literature, Fermatov, Miller-Rabin, not safe if we always use the same number e several
Frobenius, or Solovay-Strassen test are commonly used times. We use the Euclidean algorithm for determining d
as the primary numbers tests. Based on equation (4), the where e.d = 1 mod ij (n). The number e may be small for
private key exponent is computed as follows rapid calculation, especially numbers 3 and 65537 are
used for their rapid calculation [19].
d ≡ e-1 (mod φ (n)) (5)
III. DESCRIPTION OF THE USED SOURCES
The encryption and decryption process is described by
the following procedure. The implementing language of the selected algorithms
became the descriptive VHDL language. The tested target
platform is the FPGA device KC705 from Xilinx.
B. The procedure for encrypting and decrypting the The board includes, in addition to the FPGA chip,
message M. xc7k325tffg900-2 from the Kintex 7 series, 1 GB DDR3
1) Select message M to be encrypted. SODIMM 800 MHz / 1600 Mbps memory, SD
connector, USB JTAG, PCI Express, SFP connector,
2) Find the public key, the person X, by which we ethernet connector, HDMI connector, I2C bus or GTX
encrypt the message. The key is represented by (n, e). receiver and transmitter, providing a wide range of
options for communicating with the outside world. A
3) Represent the message as an integer between 0 and complete list of integrated components boards and a
(n-1). Large messages can be broken up into a number of description of their parameters can be found in document
blocks. Each block would then be represented by an [20].
integer in the same range [0, (n-1)].
4) Encryption is based on computation

C = M e (mod n) (6)

5) The encrypted text is sent to the person X through

whom we have encrypted the message with a public key
(n,e).

6) Decryption is then performed using the private key

(n, d) which belongs to the person X and the decryption Fig. 1 FPGA device Kintex 7 KC705 [8]
itself is presented like
TABLE I.
M = Cd (mod n) (7) AMMOUNT OF HARDWARE UNITS AVAILABLE – part I
CLB
Logic Cells DSP48 Slices
Flip Flops
The security of the RSA algorithm guarantees the Available for 7K325T chip 326 080 840 407 600
difficulty of factoring the large n natural numbers into
prime numbers, resulting in the use of a sufficiently long
TABLE II.
key (4096 bits or more) [13]. While adhering to the p and AMMOUNT OF HARDWARE UNITS AVAILABLE – part II
q numbers generation principles when correctly selecting
LUT BRAM_36k Slices
e without knowing the private key, the decryption process
requires a huge computational power [14]. The number n Available for 7K325T chip 203 800 445 50 950
is public, but the factorization of the numbers p and q is
very hard to determine. The hardware resources provided by the xc7k325tffg900-
Breaking the RSA cipher [15] is to find the d number 2 chip represent the following components [21]:
from the public key (n,e). The attacker knows that d is

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 SAMI 2018 • IEEE 16th World Symposium on Applied Machine Intelligence and Informatics • February 7-10 • Košice, Herl’any, Slovakia

• CLB - Configurable Logic Blocks are the main execution units (Figure 4). We can also choose the Linux
logic resources of the chip. They allow to create MMU configuration. The basic configuration defines a
both combinational and sequential logic circuits. reasonable ratio between power, occupied area, and
The 7-series configurable logic block (CLB) working frequency. For working with the soft-processor, it
provides advanced, high-performance FPGA is necessary to add additional components to the design
logic: real 6-input look-up table (LUT) and link them to the processor as shown in Figure 3.
technology, dual LUT5 (5-input LUT) option,
Distributed Memory and Shift Register Logic
capability, dedicated high-speed carry logic for
arithmetic functions, wide multiplexers for
efficient utilization.
• Slice - each Kintex 7 CLB chip contains only
CLICEL and SLICEM slices that contain four
LUTs (in function of function generators) and
nine flip-flops type FF (eight flip-flops),
multiplexers and a carry logic flip-flop, a top-up Fig. 3 Basic configuration
adder (carry logic), and the ability to create
distributed RAM or shift registers. However,
only SLICEMs can use their LUTs as distributed
RAM or SRLs.
• LUT - Look-Up-Table is a logical structure
designed as a function generator. Its main task is
to implement logical functions. The function
generators can implement any arbitrarily defined
x-input Boolean function (x-input look-up table).
• BRAM –The block RAM in Xilinx® 7 series
FPGAs stores up to 36 Kbits of data and can be
configured as either two independent 18 Kb
RAMs, or one 36 Kb RAM [22]. Fig. 4 Settings of the soft processor according to the selected preference

IV. IMPLEMENTATION
V. DESIGN OF CRYPTOGRAHY ACCELERATOR
Algorithm implementation is based on the soft
processor design for the FPGA chip. A soft processor is VHDL is the Very High Speed Integrated circuit
also known as a softcore microprocessor. It is essentially hardware description language for the programming
the core of a microprocessor that can be implemented language that is used to describe the hardware. It is used
using logical synthesis. It can be implemented on for designing and simulating digital integrated circuits
schedules containing programmable logic like CLPD or and programmable gate arrays as CLPD and in our case
FPGA devices [23]. The key benefits of using a soft FPGA. The basics of constructing VHDL is an entity and
processor include the processor's configurability, as architecture. The first mentioned component defines the
opposed to a hard processor as a CPU, which has its component's interface. The architecture contains three
hardware architecture fixed and unchanged [24]. The styles of description, namely structural, behavioral and
number of soft processors per FPGA chip is limited by dataflow descriptions. The VHDL language allows you to
the size of this FPGA chip. The basic IP block of the describe the circuit on gate, RTL and algorithmic level.
Microblaze soft processor is shown in the following The language is strongly typed and has the means to
figure [25]. describe parallelization, connectivity and explicit
expression of time. The VHDL language is used for
simulation as well as for the description of integrated
circuits [22].
Cryptographic Accelerator Modules have been
designed in the Vivado Design Suite - HLx Editions
2016.3 application using both block design options as
Fig. 2 Soft processor MicroBlaze [11] well as VHDL and C descriptions of individual modules.
• Microblaze – Softprocessor for communication
The properties of the Microblaze soft-processor can be between the user and the designed RSA module.
modified using the processor configuration settings [26].
• Clocking Wizard – generating the
The main partition is configuration for the minimum area
synchronization signal for each module of the
on the FPGA chip, which is characterized by the smallest
proposed system.
possible MicroBlaze core, without cache memory and
debug module (Figure 4). The maximum performance • Processor System Reset – provides for resetting
configuration defines a large cache memory, a debug the components of the designed system.
module, and a full computing unit (all execution units) • Axi Interconnect – the role of this module is to
(Figure 4). The maximum frequency configuration is link the components of the designed system
cache-free, without debug mode and uses a reduced set of

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 M. Huliþ et al. • Hardware Design of Cryptographic Accelerator

Fig. 5 Tested architecture

• Axi Timer – Provides recording / measurement

of RSA module performance. The latency
response time is measured.
• RSA_LUT – a hardware structure implementing
the RSA algorithm based on the Look Up Table.
• RSA_mul16s – Hardware structure
implementing the RSA algorithm using the input
data processing technique.

Two different versions of the RSA module were

implemented. The first version is based on spatial
parallelism, multiple copies of the hardware modules
(representing RSA steps) are provided in the LUT form
(RSA_LUT). The second version is based on pipelining
(RSA_mul16s). With pipelining, the steps of RSA
algoritm was broken into stages. Although each message
(message blocks) must pass through all stages, a different
message (message block) will be in each stage at any
given time so multiple messages can overlap.

VI. RESULTS OF TESTED ARCHITECTURE

By the pink color in Fig.6, is the RSA_LUT
component displayed, the RSA_mul16s yellow color.
Other Blue Modules are support modules for this circuit,
including the Microblaze soft processor. In view of the
proposed architecture, we are able to measure the
appropriate hardware load of the FPGA chip with the
values presented in Tab. 4.
TABLE III.
AMMOUNT OF HARDWARE UNITS USED

UNIT BRAM_18k DSP48E Flip flop LUT

Available 890 840 407600 203800

Used 0 32 2032 2407

Percentages 0 3 almost 0 1 Fig. 6 Resulting layout of components on FPGA chip

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 SAMI 2018 • IEEE 16th World Symposium on Applied Machine Intelligence and Informatics • February 7-10 • Košice, Herl’any, Slovakia

TABLE IV.
AMMOUNT OF HARDWARE UNITS USED
VHDL Verilog

Slice 0 0

TUL 1195 1130

FF 2327 2326

DSP 20 20

BRAM 0 0

SRL 473 473

Based on the measurements done on the mentioned

FPGA board in previous chapters, here we have the
relevant results in Tab. 5 with appropriate description.

TABLE V.
TIME DEPENDENCY ON SELECTED MESSAGE AND KEY Fig. 7 Time dependency in ms on key length and selected
LENGHT architecture
Message
256 bit 512 bit 1024 bit TABLE VI.
lenght/Key 128 bit key
key key key CONCURENT MEASUREMENTS
lenght CLB
Test. device Frequency
used
501 394 500 202 1000404
32 bit 48 527 ms RSA FPGA Xilinx
ms ms ms 36.3 MHz 28,350
ePass [7] VIRTEX-V
501 654 500 441 999689 RSA FPGA
unavailable 150 MHz 5950
64 bit 49 710 ms [8]
ms ms ms RSA FPGA 3s100evq100-
68.57 MHz 2366
501 156 498 533 1 512 527 [9] 4
128 bit 501 156 ms RSA FPGA
ms ms ms CRT Virtex-6
33MHz 236
1 000 2 002 3 502 131 paralel. FPGA
265 bit 499 725 ms Arch. [10]
643 ms 239 ms ms Xilinx 152.77
RSA_mul16s 2407
2 002 001 2 501 2 502 4 003 048 KC705 MHz
512 bit
ms 488 ms 441 ms ms
Xilinx 254.46
RSA_LUT 6711
3 001 928 5 003 8 005 8 006 811 KC705 MHz
1024 bit
ms 929 ms 381 ms ms

Our tested architectures had the greatest values of

Previous table V. shows increasing character with the frequency at level 152.77 MHz for RSA_mul16s
size of the key and the length of the message. Based on architecture and 254.46 MHz at RSA_LUT architecture.
the chosen architecture, the following chart presents The maximal usage of CLB was at provided FPGA board
increasing character with the chosen key length on the maximum 3 percentages. Our tested architecture
time consumption. In general, the bigger the message is, demonstrates the higher performance then other
the more time for calculation is needed. It means, with compared solutions.
increasing key length size the computation time is also
increasing. VII. CONCLUSION
Longer length of the message and the key make larger The RSA algorithm was implemented using C
demands on the amount of memory. For now, it is limited language in Vivado HLS 2016.3 Vivado Design Suite -
to the 1024 bits, due to the actual limitation with memory HLx Editions 2016.3. In the synthesis, two approaches to
on the specific FPGA device [20] which we used during RSA creation were applied. The first approach was based
testing our designed architecture. on the use of LUT in circuit synthesis, and the result of
The future scientific research will be aimed to solve the synthesis was RSA_LUT. The second approach was
this problem, how to increase the length of message and based on the application of the pipeline processing and
key bigger than 1024 bits. The main problem is with the synthesized module was named RSA_mul16s. The
multiplication two large numbers p and q while process name is derived from the 16-bit arithmetic-logical units
of computing n = p x q in RSA algorithm. Next research used to calculate the numbers in unsigned numbers.
will lead to find mathematical method how to calculate
numbers bigger than mentioned.

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 M. Huliþ et al. • Hardware Design of Cryptographic Accelerator

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