1) MOD 16 up down syn

Form :-
module T_FF_Form(
output reg Q,
output reg Qb ,
input T,

input clk
);
initial begin
Q=1;Qb=0;
end
always @(negedge clk )begin
if(T==0) begin
Q <=Q;Qb<=Qb;
end

else if(T==1) begin

Q <= ~Q; Qb<= ~Qb;
end
end
endmodule

module MOD_16_form(
output Qc0,
output Qc1,
output Qc2,
output Qc3,
input T1,

input clk,
input M
);
wire Qb0;
wire Qb1;
wire Qb2;
wire Qb3;

T_FF_Form F0(.Q(Qc0), .Qb(Qb0), .T(T1), .clk(clk));

T_FF_Form F1(.Q(Qc1), .Qb(Qb1), .T(M^Qc0), .clk(clk));
T_FF_Form F2(.Q(Qc2), .Qb(Qb2), .T((M&(~Qc1)&(~Qc0))|((~M)&Qc1&Qc0)), .clk(clk));
T_FF_Form F3(.Q(Qc3), .Qb(Qb3),
.T((M&(~Qc2)&(~Qc1)&(~Qc0))|((~M)&Qc2&Qc1&Qc0)), .clk(clk));
endmodule
 test :-
module MOD_16_sim(

);
wire Qc3;
wire Qc2;
wire Qc1;
wire Qc0;
reg T1;

reg clk;
reg M;
MOD_16_form uut(.Qc0(Qc0),.Qc1(Qc1),.Qc2(Qc2),.Qc3(Qc3),.T1(T1),.clk(clk),.M(M));
always #25 clk=~clk;
initial begin
clk=1;
T1=1;M=0;
#1000
$finish ;
end

endmodule

2) MOD 16 up down asyn

Form :
module T_FF_Form(
output reg Q,
output reg Qb,
input T,

input clk
);
initial begin
Q = 0; // Initialize Q
Qb = 1; // Initialize Qb (the complement of Q)
end

always @(negedge clk) begin

if (T == 0 ) begin
Q <= Q; // Hold state
Qb <= Qb;
end

else if (T == 1 ) begin
Q <= ~Q; // Toggle
 Qb <= ~Qb;
end
end
endmodule

module counter_form(
output Qc0,
output Qc1,
output Qc2,
output Qc3,
input M,
input T,

input clk
);

wire Qb0, Qb1, Qb2,Qb3;

// initial begin
// Qc = 3'b000; // Initialize the counter output
// end

// First JK flip-flop instance

T_FF_Form F1(
.Q(Qc0), .Qb(Qb0),
.T(T),
.clk(clk) // Use the main clock
);

// Second JK flip-flop instance

T_FF_Form F2(
.Q(Qc1), .Qb(Qb1),
.T(T),
.clk((~M&Qc0)|(M&Qb0)) // Clock is driven by Q[0]
);

// Third JK flip-flop instance

T_FF_Form F3(
.Q(Qc2), .Qb(Qb2),
.T(T),
.clk((~M&Qc1)|(M&Qb1)) // Clock is driven by Q[1]
);
T_FF_Form F4(
.Q(Qc3), .Qb(Qb3),
.T(T),
.clk((~M&Qc2)|(M&Qb2)) // Clock is driven by Q[1]
);
endmodule

test :

module test();

// Output wire for the counter

wire Qc3;
wire Qc2;
wire Qc1;
wire Qc0; // Renamed from Qc to maintain consistency with your main module

reg M;
// Clock and JK input registers
reg T;

reg clk;

// Instantiate the 3-bit up counter

counter_form uut(
.Qc0(Qc0),

.Qc1(Qc1),
.Qc2(Qc2),
.Qc3(Qc3),
.T(T),
.M(M),
.clk(clk)
);

// Initialize clock and run the simulation for 1000 time units
initial begin

// Initialize J and K for counting

M=1;
T = 1; // Set J to 1 for toggling
// Set K to 1 for toggling
clk = 0;

#1000; // Run simulation for 1000 time units

$finish; // End the simulation
end

// Toggle clock every 25 time units

always #25 clk = ~clk;
 endmodule

3) MOD 16 UP asyn
Form :-
module T_FF_Form(
output reg Q,
output reg Qb,
input T,

input clk
);
initial begin
Q = 0; // Initialize Q
Qb = 1; // Initialize Qb (the complement of Q)
end

always @(negedge clk) begin

if (T == 0 ) begin
Q <= Q; // Hold state
Qb <= Qb;
end

else if (T == 1 ) begin
Q <= ~Q; // Toggle
Qb <= ~Qb;
end
end
endmodule

module Counters_UP_3_form(
output Qc0,
output Qc1,
output Qc2,
output Qc3,
input T,

input clk
);

wire Qb0, Qb1, Qb2 ,Qb3;

// initial begin
// Qc = 3'b000; // Initialize the counter output
// end

// First JK flip-flop instance

 T_FF_Form F1(
.Q(Qc0), .Qb(Qb0),
.T(T),
.clk(clk) // Use the main clock
);

// Second JK flip-flop instance

T_FF_Form F2(
.Q(Qc1), .Qb(Qb1),
.T(T),
.clk(Qc0) // Clock is driven by Q[0]
);

// Third JK flip-flop instance

T_FF_Form F3(
.Q(Qc2), .Qb(Qb2),
.T(T),
.clk(Qc1) // Clock is driven by Q[1]
);
T_FF_Form F4(
.Q(Qc3), .Qb(Qb3),
.T(T),
.clk(Qc2) // Clock is driven by Q[1]
);

Endmodule

Test :-

module Counters_UP_sim();

// Output wire for the counter

wire Qc3;
wire Qc2;
wire Qc1;
wire Qc0; // Renamed from Qc to maintain consistency with your main module

// Clock and JK input registers

reg T;

reg clk;

// Instantiate the 3-bit up counter

Counters_UP_3_form uut(
.Qc0(Qc0),

.Qc1(Qc1),
 .Qc2(Qc2),
.Qc3(Qc3),
.T(T),

.clk(clk)
);

// Initialize clock and run the simulation for 1000 time units
initial begin

// Initialize J and K for counting

T = 1; // Set J to 1 for toggling
// Set K to 1 for toggling
clk = 0;
// #25
// J = 1;
// K = 1;
// Initialize the clock
#1000; // Run simulation for 1000 time units
$finish; // End the simulation
end

// Toggle clock every 25 time units

always #25 clk = ~clk;

endmodule

4) MOD 16 UP syn
Form :
module T_FF_Form(
output reg Q,
output reg Qb ,
input T,

input clk
);
initial begin
Q=1;Qb=0;
end
always @(negedge clk )begin
if(T==0) begin
Q <=Q;Qb<=Qb;
end
 else if(T==1 ) begin
Q <= ~Q; Qb<= ~Qb;
end
end
endmodule

module counter_form(
output Qc0,
output Qc1,
output Qc2,
output Qc3,
input T1,

input clk
);
wire Qb0;
wire Qb1;
wire Qb2;
wire Qb3;

T_FF_Form F0(.Q(Qc0), .Qb(Qb0), .T(T1), .clk(clk));

T_FF_Form F1(.Q(Qc1), .Qb(Qb1), .T(Qc0), .clk(clk));
T_FF_Form F2(.Q(Qc2), .Qb(Qb2), .T(Qc0 & Qc1), .clk(clk));
T_FF_Form F3(.Q(Qc3), .Qb(Qb3), .T(Qc0 & Qc1 & Qc2), .clk(clk));
endmodule

Test :-

module test(

);
wire Qc3;
wire Qc2;
wire Qc1;
wire Qc0;
reg T1;

reg clk;
counter_form uut(.Qc0(Qc0),.Qc1(Qc1),.Qc2(Qc2),.Qc3(Qc3),.T1(T1),.clk(clk));
initial begin
clk=0;
T1=1;
#1000
$finish ;
end
 always #25 clk=~clk;
endmodule

5) MOD 9 syn
Form :
module T_FF_Form(
output reg Q,
output reg Qb ,
input T,

input clk
);
initial begin
Q=1;Qb=0;
end
always @(negedge clk )begin
if(T==0) begin
Q <=Q;Qb<=Qb;
end

else if(T==1 ) begin

Q <= ~Q; Qb<= ~Qb;
end
end
endmodule

module counter(
output Qc0,
output Qc1,
output Qc2,
output Qc3,
//input T1,

input clk
);
wire Qb0;
wire Qb1;
wire Qb2;
wire Qb3;

T_FF_Form F0(.Q(Qc0), .Qb(Qb0), .T(~Qc3), .clk(clk));

T_FF_Form F1(.Q(Qc1), .Qb(Qb1), .T(Qc0), .clk(clk));
T_FF_Form F2(.Q(Qc2), .Qb(Qb2), .T(Qc0 & Qc1), .clk(clk));
 T_FF_Form F3(.Q(Qc3), .Qb(Qb3), .T((Qc0 & Qc1 & Qc2 )|(Qc3)), .clk(clk));
endmodule

Test :-
module test(

);
wire Qc3;
wire Qc2;
wire Qc1;
wire Qc0;
// reg T1;

reg clk;
counter uut(.Qc0(Qc0),.Qc1(Qc1),.Qc2(Qc2),.Qc3(Qc3),.clk(clk));
initial begin
clk=1;
//T1=1;
#1000
$finish ;
end
always #25 clk=~clk;
endmodule

6) MOD 9 asyn :-

Form :

module counter(
input clk,
output [3:0]q);
wire reset;
assign reset=q[3]&q[0];
t_ff t0(1,clk,reset,q[0]);
t_ff t1(1,q[0],reset,q[1]);
t_ff t2(1,q[1],reset,q[2]);
t_ff t3(1,q[2],reset,q[3]);

endmodule
module t_ff(
input t,clk,reset,
output reg q);
initial begin
q=0;
 end
always@(negedge clk or posedge reset)
begin
if(reset==1)
begin
q=0;
end
else
begin
if(t==0)
begin
q<=q;
end
if(t==1)
begin
q<=~q;
end
end
end

endmodule

tb:-

module test();
reg clk;
wire [3:0]q;
counter dut(.clk(clk),.q(q));
always #25 clk=~clk;

initial begin
clk=0;

#1000;
$finish;
end

endmodule
7) MOD 9 behave
Form ;
module counter(
input clk,rst,enable,
output reg [3:0]counter_output
);

always@ (posedge clk)

begin
if( rst | counter_output==4'b1000)
counter_output <= 4'b0000;
else if(enable)
counter_output <= counter_output + 1;
else
counter_output <= 0;
end
endmodule

test :-
module test;
// Inputs
reg clk;
reg rst;
reg enable;
// Outputs
wire [3:0] counter_output;

// Instantiate the Unit Under Test (UUT)

counter uut (
.clk(clk),
.rst(rst),
.enable(enable),
.counter_output(counter_output)
);
always
#25 clk= ~ clk;

initial begin
clk=1;
// Initialize Inputs
rst = 0;
enable = 0;
#100;
rst=0;
enable=1;
#100;
rst=0;
enable=1;

// Wait 100 ns for global reset to finish

#100;
end
endmodule
8) MOD 16 UP behave
Form :

module counter(
input clk,rst,enable,
output reg [3:0]counter_output
);

always@ (posedge clk)

begin
if( rst | counter_output==4'b1111)
counter_output <= 4'b0000;
else if(enable)
counter_output <= counter_output + 1;
else
counter_output <= 0;
end
endmodule

test :-

module mod_10_counter_test;
// Inputs
reg clk;
reg rst;
reg enable;
// Outputs
wire [3:0] counter_output;

// Instantiate the Unit Under Test (UUT)

counter uut (
.clk(clk),
.rst(rst),
.enable(enable),
.counter_output(counter_output)
);
always
#25 clk= ~ clk;

initial begin
clk=1;
// Initialize Inputs
rst = 0;
enable = 0;
#100;
rst=0;
enable=1;
#100;
rst=0;
enable=1;

// Wait 100 ns for global reset to finish

#100;
end
endmodule

9) MOD 16 UD behave :
Form :
module counter(
Clk,
reset,
UpOrDown, //high for UP counter and low for Down counter
Count
);

//input ports and their sizes

input Clk,reset,UpOrDown;
//output ports and their size
output [3 : 0] Count;
//Internal variables
reg [3 : 0] Count = 0;

always @(posedge(Clk) or posedge(reset))

begin
if(reset == 1)
Count <= 0;
else
if(UpOrDown == 0) //Up mode selected
if(Count == 15)
Count <= 0;
else
Count <= Count + 1; //Incremend Counter
else //Down mode selected
if(Count == 0)
Count <= 15;
else
Count <= Count - 1; //Decrement counter
end

endmodule
test :-

module test;

// Inputs
reg Clk;
reg reset;
reg UpOrDown;

// Outputs
wire [3:0] Count;

// Instantiate the Unit Under Test (UUT)

counter uut (
.Clk(Clk),
.reset(reset),
.UpOrDown(UpOrDown),
.Count(Count)
);

//Generate clock with 10 ns clk period.

initial Clk = 0;
always #25 Clk = ~Clk;

initial begin
// Apply Inputs
reset = 0;
UpOrDown = 0;
#300;
// UpOrDown = 1;
// #300;
// reset = 1;
// UpOrDown = 0;
// #100;
// reset = 0;
end

endmodule

10) seq_det_mealy_1010_over :-
form :-

module seq_det (
input clk,
 input rst,
input in,
output reg out
);
// Define states
parameter A = 2'b00, B = 2'b01, C = 2'b10, D = 2'b11;
reg [1:0] CS, NS;

// Sequential logic for state transition

always @(posedge clk or negedge rst) begin
if (!rst)
CS <= A; // Reset state
else
CS <= NS; // Update state
end

// Combinational logic for next state and output

always @(*) begin
// Default values
NS = A;
out = 1'b0;

case (CS)
A: begin
NS = (in == 1) ? B : A;
out = 1'b0;
end
B: begin
NS = (in == 0) ? C : B;
out = 1'b0;
end
C: begin
NS = (in == 1) ? D : A;
out = 1'b0;
end
D: begin
NS = (in == 0) ? C : B;
out = (in == 0) ? 1'b1 : 1'b0; // Output 1 for sequence 1010
end
default: begin
NS = A;
out = 1'b0;
end
endcase
end
endmodule

test :-
module test;

// Testbench signals
reg clk;
reg rst;
reg in;
wire out;

// Instantiate the sequence detector module

seq_det uut (
.clk(clk),
.rst(rst),
.in(in),
.out(out)
);

// Clock generation
initial begin
clk = 0;
forever #5 clk = ~clk; // Clock period: 10ns
end

// Test sequence
initial begin
// Initialize inputs
rst = 0;
in = 0;

// Apply reset
#7 rst = 1; // Assert reset after 7ns

// Test sequence: 1010

@(posedge clk) in = 1;
@(posedge clk) in = 0;
@(posedge clk) in = 1;
@(posedge clk) in = 0; // Output should be 1 here

// Test another overlapping sequence

@(posedge clk) in = 1;
@(posedge clk) in = 0; // Output should be 1 here

// Test no matching sequence

@(posedge clk) in = 1;
@(posedge clk) in = 1;
@(posedge clk) in = 0;
@(posedge clk) in = 1;
 @(posedge clk) in = 0; // Output should remain 0

// End simulation
#50 $stop;
end

// Monitor signals

endmodule

11) seq_det_mealy_1010_non_over :-
Form :-

module seq_det (
input clk,
input rst,
input in,
output reg out
);
// Define states
parameter A = 2'b00, B = 2'b01, C = 2'b10, D = 2'b11;
reg [1:0] CS, NS;

// Sequential logic for state transition

always @(posedge clk or negedge rst) begin
if (!rst)
CS <= A; // Reset state
else
CS <= NS; // Update state
end

// Combinational logic for next state and output

always @(*) begin
// Default values
NS = A;
out = 1'b0;

case (CS)
A: begin
NS = (in == 1) ? B : A;
out = 1'b0;
end
B: begin
 NS = (in == 0) ? C : B;
out = 1'b0;
end
C: begin
NS = (in == 1) ? D : A;
out = 1'b0;
end
D: begin
NS = (in == 0) ? A : B;
out = (in == 0) ? 1'b1 : 1'b0; // Output 1 for sequence 1010
end
default: begin
NS = A;
out = 1'b0;
end
endcase
end
endmodule
test :-

module test;

// Testbench signals
reg clk;
reg rst;
reg in;
wire out;

// Instantiate the sequence detector module

seq_det uut (
.clk(clk),
.rst(rst),
.in(in),
.out(out)
);

// Clock generation
initial begin
clk = 0;
forever #5 clk = ~clk; // Clock period: 10ns
end

// Test sequence
initial begin
// Initialize inputs
rst = 0;
in = 0;
 // Apply reset
#7 rst = 1; // Assert reset after 7ns

// Test sequence: 1010

@(posedge clk) in = 1;
@(posedge clk) in = 0;
@(posedge clk) in = 1;
@(posedge clk) in = 0; // Output should be 1 here

// Test another overlapping sequence

@(posedge clk) in = 1;
@(posedge clk) in = 0;
@(posedge clk) in = 1;
@(posedge clk) in = 0; // Output should be 1 here

// Test no matching sequence

@(posedge clk) in = 1;
@(posedge clk) in = 1;
@(posedge clk) in = 0;
@(posedge clk) in = 1;
@(posedge clk) in = 0; // Output should remain 0

// End simulation
#50 $stop;
end

// Monitor signals

endmodule

12) seq_det_moore_1010_over :-
form :-

module seq_det (
input clk,
input rst,
input in,
output reg out
);
// Define states
parameter A = 3'b000, B = 3'b001, C = 3'b010, D = 3'b011,E=3'b100;
reg [2:0] CS, NS;

// Sequential logic for state transition

always @(posedge clk or negedge rst) begin
 if (!rst)
CS <= A; // Reset state
else
CS <= NS; // Update state
end

// Combinational logic for next state and output

always @(*) begin
// Default values
NS = A;
out = 1'b0;

case (CS)
A: begin
NS = (in == 1) ? B : A;
out = 1'b0;
end
B: begin
NS = (in == 0) ? C : B;
out = 1'b0;
end
C: begin
NS = (in == 1) ? D : A;
out = 1'b0;
end
D: begin
NS = (in == 0) ? E : B;
out = (in == 0) ? 1'b1 : 1'b0; // Output 1 for sequence 1010
end
E: begin
NS = (in == 0) ? A : D;
out = 1'b0 ;// Output 1 for sequence 1010
end
default: begin
NS = A;
out = 1'b0;
end
endcase
end
endmodule

test :-

module test;

// Testbench signals
reg clk;
reg rst;
reg in;
wire out;

// Instantiate the sequence detector module

seq_det uut (
.clk(clk),
.rst(rst),
.in(in),
.out(out)
);

// Clock generation
initial begin
clk = 0;
forever #5 clk = ~clk; // Clock period: 10ns
end

// Test sequence
initial begin
// Initialize inputs
rst = 0;
in = 0;

// Apply reset
#7 rst = 1; // Assert reset after 7ns

// Test sequence: 1010

@(posedge clk) in = 1;
@(posedge clk) in = 0;
@(posedge clk) in = 1;
@(posedge clk) in = 0; // Output should be 1 here

// Test another overlapping sequence

@(posedge clk) in = 1;
@(posedge clk) in = 0; // Output should be 1 here

// Test no matching sequence

@(posedge clk) in = 1;
@(posedge clk) in = 1;
@(posedge clk) in = 0;
@(posedge clk) in = 1;
@(posedge clk) in = 0; // Output should remain 0
@(posedge clk) in = 1;
@(posedge clk) in = 0;
@(posedge clk) in = 1;
@(posedge clk) in = 0;
// End simulation
 #50 $stop;
end

// Monitor signals

endmodule

13) seq_det_moore_1010_non_over :-
form :-

module seq_det (
input clk,
input rst,
input in,
output reg out
);
// Define states
parameter A = 3'b000, B = 3'b001, C = 3'b010, D = 3'b011,E=3'b100;
reg [2:0] CS, NS;

// Sequential logic for state transition

always @(posedge clk or negedge rst) begin
if (!rst)
CS <= A; // Reset state
else
CS <= NS; // Update state
end

// Combinational logic for next state and output

always @(*) begin
// Default values
NS = A;
out = 1'b0;

case (CS)
A: begin
NS = (in == 1) ? B : A;
out = 1'b0;
end
B: begin
NS = (in == 0) ? C : B;
out = 1'b0;
end
C: begin
 NS = (in == 1) ? D : A;
out = 1'b0;
end
D: begin
NS = (in == 0) ? E : B;
out = (in == 0) ? 1'b1 : 1'b0; // Output 1 for sequence 1010
end
E: begin
NS = (in == 0) ? A : B;
out = 1'b0 ;// Output 1 for sequence 1010
end
default: begin
NS = A;
out = 1'b0;
end
endcase
end
endmodule

test :-

module test;

// Testbench signals
reg clk;
reg rst;
reg in;
wire out;

// Instantiate the sequence detector module

seq_det uut (
.clk(clk),
.rst(rst),
.in(in),
.out(out)
);

// Clock generation
initial begin
clk = 0;
forever #5 clk = ~clk; // Clock period: 10ns
end

// Test sequence
initial begin
// Initialize inputs
rst = 0;
 in = 0;

// Apply reset
#7 rst = 1; // Assert reset after 7ns

// Test sequence: 1010

@(posedge clk) in = 1;
@(posedge clk) in = 0;
@(posedge clk) in = 1;
@(posedge clk) in = 0; // Output should be 1 here

// Test another overlapping sequence

@(posedge clk) in = 1;
@(posedge clk) in = 0; // Output should be 1 here

// Test no matching sequence

@(posedge clk) in = 1;
@(posedge clk) in = 1;
@(posedge clk) in = 0;
@(posedge clk) in = 1;
@(posedge clk) in = 0; // Output should remain 0
@(posedge clk) in = 1;
@(posedge clk) in = 0;
@(posedge clk) in = 1;
@(posedge clk) in = 0;
// End simulation
#50 $stop;
end

// Monitor signals

endmodule

14) seq_gen_10110_behave :-
form :-

module form (
input clk,
input rst,

output reg out

);
// Define states
parameter A = 3'b000, B = 3'b001, C = 3'b010, D = 3'b011 ,E=3'b100;
 reg [2:0] CS, NS;

// Sequential logic for state transition

always @(posedge clk or negedge rst) begin
if (!rst)
CS <= A; // Reset state
else
CS <= NS; // Update state
end

// Combinational logic for next state and output

always @(*) begin
// Default values
NS = A;
out = 1'b0;

case (CS)
A: begin
NS = B;
out = 1'b1;
end
B: begin
NS = C ;
out = 1'b0;
end
C: begin
NS = D ;
out = 1'b1;
end
D: begin
NS = E;
out = 1'b1; // Output 1 for sequence 1010
end
E: begin
NS = A;
out = 1'b0; // Output 1 for sequence 1010
end
default: begin
NS = A;
out = 1'b0;
end
endcase
end
endmodule

tb:-

module tb;
 // Testbench signals
reg clk;
reg rst;

wire out;

// Instantiate the sequence detector module

form uut (
.clk(clk),
.rst(rst),

.out(out)
);

// Clock generation
initial begin
clk = 0;
forever #5 clk = ~clk; // Clock period: 10ns
end

// Test sequence
initial begin
// Initialize inputs
rst = 0;

// Apply reset
#7 rst = 1; // Assert reset after 7ns

// End simulation
#200 $stop;
end

// Monitor signals

endmodule

15) Seq_gen_10110_str:-
Form :-
module D_FF(
output reg Q,
output reg Qb,
input D,
input clk,
 input rst
);
initial begin
Q = 0;
Qb = 1;
end

always @(posedge clk or negedge rst) begin

if (!rst) begin
Q <= 0;
Qb <= 1;
end else begin
Q <= D;
Qb <= ~D;
end
end
endmodule

// Updated form module with reset functionality

module form(
output reg Q,
input clk,
input rst // Added reset input
);
wire Q1, Q2, Q3, Q4, Qb1, Qb2, Qb3, Qb4;
wire F;

// Combinational logic for F

assign F = (~Q1) | (~Q4);

// Instantiate D_FF modules with reset

D_FF F1 (.Q(Q1), .Qb(Qb1), .D(F), .clk(clk), .rst(rst));
D_FF F2 (.Q(Q2), .Qb(Qb2), .D(Q1), .clk(clk), .rst(rst));
D_FF F3 (.Q(Q3), .Qb(Qb3), .D(Q2), .clk(clk), .rst(rst));
D_FF F4 (.Q(Q4), .Qb(Qb4), .D(Q3), .clk(clk), .rst(rst));

// Update Q output on positive edge of clk

always @(posedge clk or negedge rst) begin
if (!rst) begin
Q <= 0;
end else begin
Q <= Q1;
end
end
endmodule
tb:-

module tb;

reg clk;
reg rst;
// reg reset;
wire Q;

form uut (
.Q(Q),
.clk(clk),
.rst(rst)
);

initial begin
clk = 1;
forever #5 clk = ~clk; // Clock period: 10ns
end

// Test sequence
initial begin
// Initialize inputs
rst = 0;
// in = 0;

// Apply reset
#7 rst = 1; // Assert reset after 7ns

#300;

$finish;
end

endmodule
16) USR_behave:-
Form :-
module form (
input clk, rst,
input [1:0] select, // select operation
input [3:0] pin, // parallel data in
input left_in, // serial left data in
input right_in, // serial right data in
output reg [3:0] pout, // parallel data out
output reg left_out, // serial left data out
output reg right_out // serial right data out
);
always @(posedge clk or negedge rst) begin
if (!rst)
pout <= 4'b0; // Clear pout on reset
else begin
case(select)
2'b01: pout <= {right_in, pout[3:1]}; // Right Shift
2'b10: pout <= {pout[2:0], left_in}; // Left Shift
2'b11: pout <= pin; // Parallel in
default: pout <= pout; // Retain current value
endcase
end
end

always @(posedge clk or negedge rst) begin

if (!rst) begin
left_out <= 1'b0; // Reset outputs
right_out <= 1'b0;
end else begin
left_out <= pout[0]; // Update left_out
right_out <= pout[3]; // Update right_out
end
end
endmodule

tb:-

module tb;
// Testbench signals
reg clk, rst;
reg [1:0] select;
reg [3:0] pin;
reg left_in, right_in;
wire [3:0] pout;
wire left_out, right_out;
// Instantiate the module under test
form uut (
.clk(clk),
.rst(rst),
.select(select),
.pin(pin),
.left_in(left_in),
.right_in(right_in),
.pout(pout),
.left_out(left_out),
.right_out(right_out)
);

// Clock generation
initial begin
clk = 0;
forever #5 clk = ~clk; // Generate a clock with a period of 10 time units
end

// Testbench logic
initial begin
// Initialize signals
rst = 0;
select = 2'b00;
pin = 4'b0000;
left_in = 0;
right_in = 0;

// Apply reset
#10 rst = 1;

// Test case 1: Parallel load

#10 select = 2'b11; pin = 4'b1010;
#10; // Wait for operation

// Test case 2: Right shift

#10 select = 2'b01; right_in = 1;
#10; // Wait for operation

// Test case 3: Left shift

#10 select = 2'b10; left_in = 1;
#10; // Wait for operation

// Test case 4: Default (retain value)

#10
pin = 4'b1011;
 select = 2'b11;
#10 select = 2'b00; // Wait for operation

// Test case 5: Reset during operation

#10 rst = 0;
#10 rst = 1;

// End simulation
#50 $stop;
end

// Monitor output values

initial begin
$monitor($time, " clk=%b, rst=%b, select=%b, pin=%b, left_in=%b, right_in=%b,
pout=%b, left_out=%b, right_out=%b",
clk, rst, select, pin, left_in, right_in, pout, left_out, right_out);
end
endmodule

17) USR_str:-
Form :-

module MUX_4_1(
input D0,
input D1,
input D2,
input D3,
input [1:0] Select,
output Y
);
assign Y = ((~Select[1]) & (~Select[0]) & D0) |
((~Select[1]) & Select[0] & D1) |
(Select[1] & (~Select[0]) & D2) |
(Select[1] & Select[0] & D3);
endmodule

module D_FF(
output reg Q,
input D,
input clk,
input rst
);
always @(posedge clk or posedge rst) begin
if (rst) begin
Q <= 0; // Reset state
end else begin
Q <= D; // Update state
 end
end
endmodule
module form(
input P0, P1, P2, P3, // Parallel inputs
input Sr, Sl, // Serial inputs (right and left)
input [1:0] Select, // Mode select
input clk,
input rst,
output Q0, Q1, Q2, Q3 // Parallel outputs
);
wire C0, T0, T1, T2, Y1, Y2, Y3, Y4;

// MUX control for shifting and parallel loading

MUX_4_1 M1 (.D0(C0), .D1(Sr), .D2(T0), .D3(P3), .Select(Select), .Y(Y1));
MUX_4_1 M2 (.D0(T0), .D1(C0), .D2(T1), .D3(P2), .Select(Select), .Y(Y2));
MUX_4_1 M3 (.D0(T1), .D1(T0), .D2(T2), .D3(P1), .Select(Select), .Y(Y3));
MUX_4_1 M4 (.D0(T2), .D1(T1), .D2(Sl), .D3(P0), .Select(Select), .Y(Y4));

// Flip-flops to store the values

D_FF F1 (.Q(C0), .D(Y1), .clk(clk), .rst(rst));
D_FF F2 (.Q(T0), .D(Y2), .clk(clk), .rst(rst));
D_FF F3 (.Q(T1), .D(Y3), .clk(clk), .rst(rst));
D_FF F4 (.Q(T2), .D(Y4), .clk(clk), .rst(rst));

// Assign the outputs to the flip-flop values

assign Q3 = C0;
assign Q2 = T0;
assign Q1 = T1;
assign Q0 = T2;
endmodule

tb:-

module tb;
reg P0, P1, P2, P3; // Parallel inputs
reg Sr, Sl; // Serial inputs (right and left)
reg [1:0] Select; // Mode select
reg clk, rst; // Clock and reset
wire Q0, Q1, Q2, Q3; // Parallel outputs

// Instantiate the USR

form uut (
.P0(P0), .P1(P1), .P2(P2), .P3(P3),
.Sr(Sr), .Sl(Sl),
.Select(Select),
.clk(clk),
 .rst(rst),
.Q0(Q0), .Q1(Q1), .Q2(Q2), .Q3(Q3)
);

// Clock generation
always #5 clk = ~clk;

initial begin
// Initialize inputs
clk = 0;
rst = 1;
P0 = 0; P1 = 0; P2 = 0; P3 = 0;
Sr = 0; Sl = 0;
Select = 2'b00;

// Apply reset
#10 rst = 0;

// Test Case 1: Serial-In Serial-Out (SISO)

Select = 2'b01; // SISO mode
Sr = 1; // Shift in '1'
#10;
Sr = 0; // Shift in '0'
#10;
Sr = 1; // Shift in '1'
#10;
Sr = 0; // Shift in '1'
#10;

// Test Case 2: Parallel-In Parallel-Out (PIPO)

Select = 2'b11; // PIPO mode
P3 = 0; P2 = 1; P1 = 0; P0 = 1; // Set parallel data
#10;

// Test Case 3: Parallel-In Serial-Out (PISO)

Select = 2'b10;
Sl = 1; // Shift in '1'
#10;
Sl = 1; // Shift in '0'
#10;
Sl = 0; // Shift in '1'
#10;
Sl = 1; // Shift in '1'
#10;

// Test Case 4: Serial-In Parallel-Out (SIPO)

Select = 2'b01; // SIPO mode, shifting right
 Sr = 1;
#10;

// Finish the simulation

#20;
$stop;
end
endmodule

18) SBA :-
Form :-

module fa( input a,b,c,

output sum,carry);
assign sum=a^b^c;
assign carry=(a&b)|(b&c)|(c&a) ;
endmodule

module d_ff( input clk, rst, d,

output reg q );
always @(posedge clk or negedge rst) begin
if (!rst)
q <= 0;
else
q <= d;
end
endmodule

module mux(input i0, i1, s,

output y );
assign y = (s & i0) | (~s & i1);
endmodule

module sr(input clk, rst, shift, si,

input [3:0] d,
output [3:0] q ,
output x);
wire w0, w1, w2, w3;

// First flip-flop (q[0] will get the serial input si)

mux m0(si, d[3], shift, w0);
d_ff d0(clk, rst, w0, q[3]);
 // Second flip-flop (q[1] will get the value of q[0])
mux m1(q[3], d[2], shift, w1);
d_ff d1(clk, rst, w1, q[2]);

// Third flip-flop (q[2] will get the value of q[1])

mux m2(q[2], d[1], shift, w2);
d_ff d2(clk, rst, w2, q[1]);

// Fourth flip-flop (q[3] will get the value of q[2])

mux m3(q[1], d[0], shift, w3);
d_ff d3(clk, rst, w3, q[0]);
assign x=q[0];

endmodule

module form(input clk,rst,control,si,

input [3:0]a,b,c,
output carry,z,
output [3:0]o);
wire [3:0]w1,w2;
wire cin;

sr s1(clk,rst,control,si,a,w1);
sr s2(clk,rst,control,si,b,w2);
fa f1(w1[0],w2[0],cin,z,carry);
d_ff d1(clk,rst,carry,cin);
sr s3(clk,rst,control,z,c,o);
endmodule

tb:-

module tb( );
reg clk,rst,control,si;
reg [3:0]a,b,c;
wire carry,z;
wire [3:0]o;
form uut(clk,rst,control,si,a,b,c,carry,z,o);
initial begin a=4'b1010;b=4'b1101; end
initial begin
clk=0;control=0;rst=0;c=4'b0000;
si=0;#5;rst=1;
si=0;#5;
control=1;
si=0;#5;
 si=0;#5;
#100
rst=0;control=0;a=4'b1101 ; b=4'b1011;
si=0;
#5;rst=1;
si=0;
#5;control=1;
#100

//rst=0;control=0;a=4'b1101 ; b=4'b0111;
//si=0;
//#5;rst=1;
//si=0;
//#5;control=1;
//#100
$finish;
end
always #5 clk=~clk;
endmodule

19) Shift_add_mult :-
Form :-

module sa (

input [3:0] M, Q,

input clk, rst,

output reg [7:0] Y

);
reg [3:0] a, q;

reg c;

integer i; // Loop variable

always @(posedge clk or negedge rst) begin

if (!rst) begin

a <= 4'b0000;

q <= 4'b0000;

c <= 1'b0;

Y <= 8'b00000000;
end
 else begin

a = 4'b0000; // Initialize accumulator

q = Q; // Load Q

c = 1'b0;

for (i = 0; i < 4; i = i + 1) begin

if (q[0]) begin

{c, a} = a + M; // Add M if LSB of q is 1

end

{c, a, q} = {c, a, q} >> 1; // Arithmetic Right Shift

end

Y = {a, q}; // Store final multiplication result

end

end

endmodule

tb:-

module tb();

reg clk, rst;

reg [3:0] M, Q;

wire [7:0] Y;

// reg [3:0] a, q;

// reg c;

// reg [2:0] count;

// Instantiate the DUT (Device Under Test)

sa uut (

.M(M), .Q(Q), .clk(clk), .rst(rst), .Y(Y)

);

// Generate Clock (10ns Period, 50% Duty Cycle)

always #5 clk = ~clk;

initial begin

// Enable waveform dumping for debugging

$dumpfile("waveform.vcd");

$dumpvars(0, tb);

// Initialize clock and reset

clk = 0;

rst = 0;
M = 4'b0000;

Q = 4'b0000;

// Hold reset for longer duration (ensure stable initialization)

#20 rst = 1;

// Apply first test vector (3 * 4 = 12)

M = 4'b0011; Q = 4'b0100;

#10; // Wait for multiplication to complete

rst = 0; #10;

rst = 1;

// Apply second test vector (11 * 6 = 66)

M = 4'b1011; Q = 4'b0110;

#10;
 #20

// Print Debug Information

$display("Result: %b (Expected 01000010)", Y);

// End simulation

// #100;

$finish;

end

endmodule

20) Restoring div :-

Form :-

module restoring(
input [3:0] Q, // Dividend
input [3:0] M,
input clk,rst, // Divisor
output reg [4:0] An, // Remainder
output reg [3:0] Qn // Quotient
);
reg [4:0] A, Mn;
//reg[4:0]c;

integer i;
always @(posedge clk or negedge rst) begin
if(!rst) begin
A<=5'b00000;
An<=5'b00000;
Qn <= 4'b0000;
Mn <= {1'b0, M};
end
else begin
A=5'b00000;
Qn = Q;
Mn = {1'b0, M};
for(i=0;i<4;i=i+1) begin
{A,Qn}={A,Qn}<<1;
A =A-Mn;
 if(A[4]==1'b1) begin
A=A+Mn;
Qn[0]=1'b0;
end
else begin
Qn[0]=1'b1;
end

end
An<=A;
end
end

// Qn=Q;

Endmodule

Tb:-

module tb;
reg clk, rst;
reg [3:0] Q, M;
wire [3:0] Qn;

wire [4:0] An; // Corrected to 5-bit

// Instantiate the restoring division module with correct port mapping

restoring uut (
.Q(Q),
.M(M),
.clk(clk),
.rst(rst),
.An(An),
.Qn(Qn)
);

// Clock generation
always #5 clk = ~clk;

initial begin
// Initialize signals
clk = 0;
rst = 0;
Q = 4'b0000;
M = 4'b0000;
 // Hold reset for at least 1 full clock cycle
#10 rst = 1;

// Apply test case: 15 / 4

Q = 4'b1110; // 15
M = 4'b0100; // 4

// Wait enough time for computation

#50; rst = 0;#5rst = 1;
Q=4'b1001;
M=4'b0101;#50

// End simulation
$finish;
end

// Monitor outputs
initial begin
$monitor("Time = %0t | Q = %b | M = %b | Qn = %b | An = %b",
$time, Q, M, Qn, An);
end
endmodule

21) Non restoring div :-

Form :-

module non_restoring(

input [3:0] Q, // Dividend

input [3:0] M,

input clk,rst,// Divisor

output reg [4:0] An, // Remainder

output reg [3:0] Qn // Quotient

);

reg [4:0] A, Mn;

reg[4:0]c;

integer i;

always @(posedge clk or negedge rst) begin

 if(!rst) begin

A<=5'b00000;

An<=5'b00000;

Qn <= 4'b0000;

Mn <= {1'b0, M};

end

else begin

A=5'b00000;

Qn = Q;

Mn = {1'b0, M};

for(i=0;i<4;i=i+1) begin

{A,Qn}={A,Qn}<<1;

if(A[4]==1'b0) begin

A=A-Mn;

end

else begin

A=A+Mn;

end

Qn[0]=~A[4];

end

if(A[4]==1'b1 ) begin

A=A+Mn;

end

An=A;

end

end

// Qn=Q;
Endmodule

Tb:-

module tb;

reg clk, rst;

reg [3:0] Q, M;

wire [3:0] Qn;

wire [4:0] An; // Corrected to 5-bit

// Instantiate the restoring division module with correct port mapping

non_restoring uut (

.Q(Q),

.M(M),

.clk(clk),

.rst(rst),

.An(An),

.Qn(Qn)

);

// Clock generation

always #5 clk = ~clk;

initial begin

// Initialize signals

clk = 0;

rst = 0;
 Q = 4'b0000;

M = 4'b0000;

// Hold reset for at least 1 full clock cycle

#10 rst = 1;

// Apply test case: 15 / 4

Q = 4'b1110; // 15

M = 4'b0100; // 4

// Wait enough time for computation

#50; rst = 0;#5rst = 1;

Q=4'b1001;

M=4'b0101;#50

// End simulation

$finish;

end

// Monitor outputs

initial begin

$monitor("Time = %0t | Q = %b | M = %b | Qn = %b | An = %b",

$time, Q, M, Qn, An);

end

endmodule

22) Booth mult :-

Form :-

module booth (

input [3:0] M, Q,

input clk, rst,

output reg [7:0] Y

);

reg [3:0] a, q;

reg qb;

integer i;

reg c; // Loop variable

always @(posedge clk or negedge rst) begin

if (!rst) begin

a <= 4'b0000;

q <= 4'b0000;

qb <= 1'b0;

Y <= 8'b00000000;

end

else begin

a = 4'b0000; // Initialize accumulator

q = Q; // Load Q

qb = 1'b0;

Y = 8'b00000000; // Initialize previous Q LSB

for (i = 0; i < 4; i = i + 1) begin

// Booth's algorithm conditions

if ((q[0] == 0 && qb == 0) || (q[0] == 1 && qb == 1)) begin

// No operation: just shift

qb = q[0];

{a, q} = {a, q} >> 1; // Arithmetic right shift

a[3] = a[2]; // Preserve sign bit during shift

end

else if (q[0] == 0 && qb == 1) begin

// Subtract M from accumulator

qb = q[0];

a = a + M;
 {a, q} = {a, q} >> 1;

a[3] = a[2]; // Preserve sign bit during shift

end

else if (q[0] == 1 && qb == 0) begin

// Add M to accumulator

qb = q[0];

a = a - M;

{a, q} = {a, q} >> 1;

a[3] = a[2]; // Preserve sign bit during shift

end

end

Y = {a, q};

end

end

endmodule

tb:-

module tb();

reg clk, rst;

reg [3:0] M, Q;

wire [7:0] Y;

// reg [3:0] a, q;

// reg c;

// reg [2:0] count;

// Instantiate the DUT (Device Under Test)

booth uut (

.M(M), .Q(Q), .clk(clk), .rst(rst), .Y(Y)

 );

// Generate Clock (10ns Period, 50% Duty Cycle)

always #5 clk = ~clk;

initial begin

// Enable waveform dumping for debugging

// Initialize clock and reset

clk = 0;

rst = 0;

M = 4'b0000;

Q = 4'b0000;

// Hold reset for longer duration (ensure stable initialization)

#20 rst = 1;

// Apply first test vector (3 * 4 = 12)

//M = 4'b1011; Q = 4'b0110;

M = 4'b0111; Q = 4'b0101;

#30; // Wait for multiplication to complete

rst = 0; #10;

rst = 1;

M = 4'b0101; Q = 4'b0100;

// // Apply second test vector (11 * 6 = 66)

 #30;

rst = 0; #10;

rst = 1;

M = 4'b1111; Q = 4'b0100; #30

// Apply second test vector (11 * 6 = 66)

rst = 0; #10;

rst = 1;

M = 4'b1001; Q = 4'b0101; #30

// Apply second test vector (11 * 6 = 66)

#10;

#30;

// Print Debug Information

// End simulation

// #100;

$finish;

end

endmodule

23) Modified booth :-

Form :-
module modified_booth(
input [4:0]M,Q,
input clk,rst,
output reg[11:0]Y
);
reg [5:0]A,Qc,Mc;
reg Qb;
 integer i,j;
always @(posedge clk or negedge rst) begin
if(!rst) begin
A <=6'b000000;
Qc <=6'b000000;
Mc <=6'b000000;
Qb <=1'b0;
Y <=12'b000000000000;
end
else begin
A =6'b000000;
Qc =Q;
Mc=M;
Qb =1'b0;
Y =12'b000000000000;
Qc[5]=Q[4];
Mc[5]=M[4];
for (i=0;i<3;i=i+1) begin
if((Qc[1]==0 && Qc[0]==0 && Qb==0 ) || (Qc[1]==1 && Qc[0]==1
&& Qb==1 ) ) begin
{A,Qc,Qb}={A,Qc,Qb}>>1;
{A,Qc,Qb}={A,Qc,Qb}>>1;
A[5]=A[3];
A[4]=A[3];

end
else if((Qc[1]==0 && Qc[0]==0 && Qb==1) || (Qc[1]==0 &&
Qc[0]==1 && Qb==0 ) ) begin
A=A+Mc;
{A,Qc,Qb}={A,Qc,Qb}>>1;
{A,Qc,Qb}={A,Qc,Qb}>>1;
A[5]=A[3];
A[4]=A[3];

end
else if((Qc[1]==1 && Qc[0]==0 && Qb==1) || (Qc[1]==1 &&
Qc[0]==1 && Qb==0 ) ) begin
 A=A-Mc;
{A,Qc,Qb}={A,Qc,Qb}>>1;
{A,Qc,Qb}={A,Qc,Qb}>>1;
A[5]=A[3];
A[4]=A[3];

end
else if((Qc[1]==0 && Qc[0]==1 && Qb==1) ) begin
A=A+2*Mc;
{A,Qc,Qb}={A,Qc,Qb}>>1;
{A,Qc,Qb}={A,Qc,Qb}>>1;
A[5]=A[3];
A[4]=A[3];

end
else if((Qc[1]==1 && Qc[0]==0 && Qb==0) ) begin
A=A-2*Mc;
{A,Qc,Qb}={A,Qc,Qb}>>1;
{A,Qc,Qb}={A,Qc,Qb}>>1;
A[5]=A[3];
A[4]=A[3];

end
end
Y={A,Qc};
end
end
endmodule

tb:-
module tb(

);
reg clk,rst;
// reg [5:0]A,Qc,Mc;
reg [4:0]M,Q;
wire [11:0]Y;
 modified_booth uut(
.M(M),
.Q(Q),
.clk(clk),
.rst(rst),
.Y(Y)
);
always #5 clk=~clk;
initial begin
clk=0;rst=0;M=5'b00000;Q=5'b00000;
#20 rst=1;
M=5'b01001 ;Q=5'b01110;
#30;
rst=0;#10;
rst=1;M=5'b11101;Q=5'b01100;
#30;
rst=0;#10;
rst=1;M=5'b10101;Q=5'b11100;
#30;
rst=0;#10;
rst=1;M=5'b01101;Q=5'b01100;
#30;
rst=0;#10;
rst=1;M=5'b01101;Q=5'b11100;
#30;$finish;
end
endmodule

24) Array_mult :-

Form :-
module fa( input a,b,c,output sum,carry);
assign sum=a^b^c;
assign carry=(a&b)|(b&c)|(c&a) ;
endmodule

module ha( input a,b , output sum,carry);

assign sum=a^b;
assign carry=(a&b);
endmodule

module array(
input[3:0]A,
input[3:0]B,
output [7:0]P
);
wire C0,C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,D0,D1,D2,D3,D4,D5;
assign P[0]=A[0]&B[0];
ha h1(A[1]&B[0],A[0]&B[1],P[1],C0);
fa f1(A[2]&B[0],A[1]&B[1],C0,D0,C1);
fa f2(A[3]&B[0],A[2]&B[1],C1,D1,C2);
ha h2(A[3]&B[1],C2,D2,C3);
ha h3(A[0]&B[2],D0,P[2],C4);
fa f3(A[1]&B[2],D1,C4,D3,C5);
fa f4(A[2]&B[2],D2,C5,D4,C6);
fa f5(A[3]&B[2],C3,C6,D5,C7);
ha h4(A[0]&B[3],D3,P[3],C8);
fa f6(A[1]&B[3],D4,C8,P[4],C9);
fa f7(A[2]&B[3],D5,C9,P[5],C10);
 fa f8(A[3]&B[3],C7,C10,P[6],P[7]);

endmodule

tb:-
module tb(

);
reg [3:0]A;
reg [3:0]B;
wire [7:0]P;
array uut(A,B,P);

initial begin
A=4'b1011;B=4'b0110;
#10;
A=4'b1111;B=4'b1010;
#50;
$finish;end

Endmodule

25) Floating point add cum sub :-

Form :- module add (

input [31:0] A, // IEEE 754 single-precision floating-point
number 1
input [31:0] B, // IEEE 754 single-precision floating-point
number 2
input op, // 0 for addition, 1 for subtraction
output reg [31:0] result
);

reg sign_A, sign_B, sign_res;

reg [7:0] exp_A, exp_B, exp_res;
reg [23:0] mant_A, mant_B, mant_res;
reg [24:0] sum_mant; // Extra bit for carry

always @(*) begin

// Extract sign, exponent, and mantissa
sign_A = A[31];
sign_B = B[31] ^ op; // Flip sign for subtraction
exp_A = A[30:23];
exp_B = B[30:23];
mant_A = {1'b1, A[22:0]}; // Add implicit 1 for normalized
values
mant_B = {1'b1, B[22:0]};

// Align exponents
if (exp_A > exp_B) begin
mant_B = mant_B >> (exp_A - exp_B);
exp_res = exp_A;
end else if (exp_B > exp_A) begin
mant_A = mant_A >> (exp_B - exp_A);
exp_res = exp_B;
end else begin
exp_res = exp_A;
end

// Perform addition/subtraction
if (sign_A == sign_B)
 sum_mant = mant_A + mant_B; // Addition
else
sum_mant = mant_A - mant_B; // Subtraction

// Normalization
if (sum_mant[24]) begin
sum_mant = sum_mant >> 1;
exp_res = exp_res + 1;
end else begin
while (sum_mant[23] == 0 && exp_res > 0) begin
sum_mant = sum_mant << 1;
exp_res = exp_res - 1;
end
end

// Determine result sign

sign_res = (sum_mant == 0) ? 0 : sign_A;

// Assign result
result = {sign_res, exp_res, sum_mant[22:0]};
end
endmodule

tb:- `timescale 1ns / 1ps

/////////////////////////////////////////////////////////////////
/////////////////
// Company:
// Engineer:
//
// Create Date: 15.03.2025 12:21:01
// Design Name:
// Module Name: tb
// Project Name:
// Target Devices:
 // Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
/////////////////////////////////////////////////////////////////
/////////////////

module tb;

reg [31:0] A, B;
reg op;
wire [31:0] result;

add uut (
.A(A),
.B(B),
.op(op),
.result(result)
);

initial begin
// Example: 3.5 + 2.5
A = 32'b01000000011000000000000000000000; // IEEE
754 of 3.5
B = 32'b01000000001000000000000000000000; // IEEE
754 of 2.5
op = 0; // Addition
#10;
 // Example: 5.75 - 2.25
A = 32'b01000000101110000000000000000000; // IEEE
754 of 5.75
B = 32'b01000000000100000000000000000000; // IEEE
754 of 2.25
op = 1; // Subtraction
#10;

$stop;
end

endmodule

26) ALU :- form :-

module alu (
input [3:0] A, // 4-bit input A
input [3:0] B, // 4-bit input B
input [3:0] ALU_Sel, // 4-bit selector for choosing the
operation
output reg [7:0] result // 8-bit result for multiplication
);

// Operations based on ALU_Sel value

always @ (A, B, ALU_Sel) begin
case(ALU_Sel)
4'b0000: result = A + B; // Addition
4'b0001: result = A - B; // Subtraction
4'b0010: result = A * B; // Multiplication (result
is 8-bit for overflow)
4'b0011: result = A / B; // Division (integer
division)
4'b0100: result = A % B; // Modulo (remainder
of A divided by B)
 4'b0101: result = A & B; // AND
4'b0110: result = A | B; // OR
4'b0111: result = A ^ B; // XOR
4'b1000: result = ~(A & B); // NAND
4'b1001: result = ~(A | B); // NOR
4'b1010: result = ~(A ^ B); // XNOR
default: result = 8'b00000000; // Default case
endcase
end

endmodule

tb:- module tb;

// Inputs to the ALU

reg [3:0] A;
reg [3:0] B;
reg [3:0] ALU_Sel;

// Output from the ALU

wire [7:0] result;

// Instantiate the ALU

alu uut (
.A(A),
.B(B),
.ALU_Sel(ALU_Sel),
.result(result)
);

// Apply test vectors

initial begin
// Test 1: Addition (A + B)
A = 4'b0011; // 3
B = 4'b0101; // 5
ALU_Sel = 4'b0000; // Addition
#10;
$display("Addition: %b + %b = %b", A, B, result);

// Test 2: Subtraction (A - B)
A = 4'b0110; // 6
B = 4'b0010; // 2
ALU_Sel = 4'b0001; // Subtraction
#10;
$display("Subtraction: %b - %b = %b", A, B, result);

// Test 3: Multiplication (A * B)
A = 4'b0011; // 3
B = 4'b0100; // 4
ALU_Sel = 4'b0010; // Multiplication
#10;
$display("Multiplication: %b * %b = %b", A, B, result);

// Test 4: Division (A / B)
A = 4'b0110; // 6
B = 4'b0011; // 3
ALU_Sel = 4'b0011; // Division
#10;
$display("Division: %b / %b = %b", A, B, result);

// Test 5: Modulo (A % B)
A = 4'b0110; // 6
B = 4'b0011; // 3
ALU_Sel = 4'b0100; // Modulo
#10;
$display("Modulo: %b %% %b = %b", A, B, result);

// Test 6: AND (A & B)

A = 4'b1101; // 13
B = 4'b1011; // 11
ALU_Sel = 4'b0101; // AND
#10;
$display("AND: %b & %b = %b", A, B, result);

// Test 7: OR (A | B)
A = 4'b1101; // 13
B = 4'b1011; // 11
ALU_Sel = 4'b0110; // OR
#10;
$display("OR: %b | %b = %b", A, B, result);

// Test 8: XOR (A ^ B)
A = 4'b1101; // 13
B = 4'b1011; // 11
ALU_Sel = 4'b0111; // XOR
#10;
$display("XOR: %b ^ %b = %b", A, B, result);

// Test 9: NAND (~(A & B))

A = 4'b1101; // 13
B = 4'b1011; // 11
ALU_Sel = 4'b1000; // NAND
#10;
$display("NAND: ~( %b & %b) = %b", A, B, result);

// Test 10: NOR (~(A | B))

A = 4'b1101; // 13
B = 4'b1011; // 11
ALU_Sel = 4'b1001; // NOR
#10;
$display("NOR: ~( %b | %b) = %b", A, B, result);
 // Test 11: XNOR (~(A ^ B))
A = 4'b1101; // 13
B = 4'b1011; // 11
ALU_Sel = 4'b1010; // XNOR
#10;
$display("XNOR: ~( %b ^ %b) = %b", A, B, result);

// End of simulation
$finish;
end

endmodule

27 ) vending :-

Form :- module vending (

input clk,
input rst,
input[3:0] inp,
output reg outp,
output reg[3:0] change
);
// Define states
parameter A = 2'b00, B = 2'b01, C = 2'b10;
reg [1:0] CS, NS;
// Sequential logic for state transition
always @(posedge clk or negedge rst) begin
if (!rst)
CS <= A; // Reset state
else
CS <= NS; // Update state
end
// Combinational logic for next state and output
always @(*) begin
// Default values
NS = A;
outp = 0;
change=0;
case (CS)
A: begin
if(inp==0) begin
NS=A;outp=0;change=0;
end
else if(inp==5) begin
NS=B;outp=0;change=0;
end
else if(inp == 10) begin
NS=C;outp=0;change=0;
end

end
B: begin
if(inp==0) begin
NS=A;outp=0;change=5;
end
else if(inp==5) begin
NS=C;outp=0;change=0;
end
else if(inp == 10) begin
NS=A;outp=1;change=0;
end
end
C: begin
if(inp==0) begin
NS=A;outp=0;change=10;
end
else if(inp==5) begin
NS=A;outp=1;change=0;
end
else if(inp == 10) begin
NS=A;outp=1;change=5;
end
end

default: begin
NS = A;
outp = 0;change=0;
end
endcase
end
endmodule

tb :- `timescale 1ns / 1ps

/////////////////////////////////////////////////////////////////
/////////////////
// Company:
// Engineer:
//
// Create Date: 18.03.2025 16:19:08
// Design Name:
// Module Name: tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
/////////////////////////////////////////////////////////////////
/////////////////

module tb;
// Testbench signals
reg clk;
reg rst;
reg[3:0] inp;
wire out;
wire[3:0]change;
// Instantiate the sequence detector module
vending uut (
.clk(clk),
.rst(rst),
.inp(inp),
.out(out),.change(change)
);
// Clock generation
initial begin
clk = 0;
forever #5 clk = ~clk; // Clock period: 10ns
end
// Test sequence
initial begin
// Initialize inputs
rst = 0;
inp = 0;
// Apply reset
#7 rst = 1; // Assert reset after 7ns
// Test sequence: 1010
@(posedge clk) inp = 5;
@(posedge clk) inp = 5;
@(posedge clk) inp = 5;
@(posedge clk) inp = 10;
@(posedge clk) inp = 10; // Output should be 1 here
#50
// End simulation
$stop;
end
// Monitor signals
Endmodule

27) TLC :-

Form :- module tlc (

input clk,
input rst,
input x,
output reg [1:0] Ho,
output reg [1:0] Co
);
// Define states
parameter A = 3'b000, B = 3'b001, C = 3'b010, D = 3'b011,
E = 3'b100;
reg [2:0] CS, NS;

// Sequential logic for state transition

always @(posedge clk or negedge rst) begin
if (!rst)
CS <= A; // Reset state
else
CS <= NS; // Update state
end

// Combinational logic for next state and output

always @(*) begin
// Default values
NS = A;
Ho = 2'b00;
Co = 2'b00;

case (CS)
A: begin
NS = (x == 1) ? B : A;
Ho = 2'b01; // Green for state A
Co = 2'b00; // No change in C for state A
end

B: begin
NS = C;
Ho = 2'b10; // Yellow for state B
Co = 2'b00; // No change in C for state B
end

C: begin
NS = D;
Ho = 2'b00; // Red for state C
Co = 2'b00; // No change in C for state C
end

D: begin
NS = (x == 1) ? D : E;
Ho = 2'b00; // Red for state D
Co = 2'b01; // Output 1 for sequence 1010
end

E: begin
NS = A;
Ho = 2'b00; // Red for state E
Co = 2'b10; // Output 1 for sequence 1010
end
 default: begin
NS = A;
Ho = 2'b00; // Red by default
Co = 2'b00; // No change by default
end
endcase
end
endmodule

tb :- module tb;

// Testbench signals
reg clk;
reg rst;
reg x;
wire [1:0] Ho;
wire [1:0] Co;

// Instantiate the tlc module

tlc uut (
.clk(clk),
.rst(rst),
.x(x),
.Ho(Ho),
.Co(Co)
);

// Clock generation
always begin
clk = 0;
forever #5 clk = ~clk;
end
 // Initial block for applying test cases
initial begin
// Initialize signals
rst = 0;
x = 0;
#10 rst=1;
x=0;
#20;
x=1;
#40;
x=0;
#30;

$finish;
end

endmodule