BECE204L MICROPROCESSORS AND

MICROCONTROLLERS
Dr. Sandeep Moparthi
Assistant Professor
School of Electronics Engineering

1
 ARM - Advanced RISC Machines
RISC- Reduce Instruction Set Computers

Module 6: ARM Processor Architecture

ARM Design Philosophy; Overview of ARM architecture; States
[ARM, Thumb, Jazelle]; Registers, Modes; Conditional Execution;
Pipelining; Vector Tables; Exception handling.
Reference:
• Muhammad Ali Mazidi, ARM Assembly Language Programming
& Architecture: 1, 2016, 2nd Edition, Microdigitaled.com

Course Outcomes:
CO5: Infer the architecture of ARM Processor
CO6: Develop the simple application using ARM processor.
TIMELINE (1/3)
 1985: Acorn Computer Group manufactures the first
commercial RISC microprocessor.
 1990: Acorn and Apple participation leads to the founding of
Advanced RISC Machines (A.R.M.).
 1991: ARM6, First embeddable RISC microprocessor.
 1992 – 1994: Various companies use ARM (Sharp, Samsung),
while in 1993 ARM7, the first multimedia microprocessor is
introduced.

3
TIMELINE (2/3)
 1995: Introduction of Thumb and ARM8.
 1996 – 2000: Alcatel, Huindai, Philips, Sony, use ΑRM, while
in 1999 ARM cooperates with Erickson for the development of
Bluetooth.
 2000 – 2002: ARM’s share of the 32 – bit embedded RISC
microprocessor market is 80%. ARM Developer Suite is
introduced.

4
TIMELINE (3/3)
Current low-end ARM core for applications like digital mobile
phones
 TDMI
 T: Thumb, 16-bit instruction set
 D: on-chip Debug support, enabling the processor to halt in response to
a debug request
 M: enhanced Multiplier, yield a full 64-bit result, high performance
 I: Embedded ICE hardware
ICE – in circuit emulator for debugging

 Von Neumann architecture (upto ARM7, then after it is Harvard

architecture)
 3&5-stage pipeline

5
 ARM Design Philosophy

• ARM Core uses a RISC architecture

• ARM licenses its cores and other companies make processors
based on ARM processor core based microcontrollers
• Von Neumann architecture- ARM7
• Harvard architecture- ARM9
• Reduce power consumption
• High code density
• Reduce the area of the die taken up by the embedded processor
• Incorporated hardware debug technology (ICE)
• One of the ARM’s most successful cores is the ARM7TDMI,
provides high code density and low power consumption.
 The RISC Design

• RISC is characterized by limited number of instructions

• A complex instruction is obtained as a sequence of simple
instructions.
• So, in RISC processor, software is complex but the processor
architecture is simple.
• Large number of registers are required.
• Pipelined instruction execution.

• Examples of RISC Processors: ARM, ATMEL AVR, MIPS,

Power PC etc.
 The CISC Design

• CISC is characterized by large instruction set.

• The aim of designing CISC processors is to reduce software
complexity by increasing the complexity of processor
architecture.
• Very small number of registers are available.
• Examples of CISC Processors: : Intel X86 family, Motorola
68000 series.
 RISC – Major design rules

1. Instructions

• Reduced Number of Instructions

• Execute in a single cycle
• The compiler synthesizes complicated operations
• Each instruction is a fixed length

2. Pipelines

• The processing of instructions is broken down into smaller units that

can be executed in parallel by pipelines
• Pipeline advances by one step on each cycle for maximum throughput
 RISC – Major design rules

3. Registers

• Have a large general purpose register set

• Any register can contain either data or address
• CISC has dedicated registers for specific purposes.

4. Load –Store Architecture

• Separate load and store instructions transfers data between the

register bank and external memory.
• Memory accesses are costly, so separating memory access from
data processing provides an advantage, because you can use data
items held in register banks multiple times without needing
multiple memory accesses.
 Overview of ARM Core Data Path

 Data items are placed in register file

• No data processing instructions directly manipulate data in
memory
 Instructions typically use two source registers and single
result/destination register
 A Barrel shifter on the data path can pre-process data before it
enters ALU
 Increment/Decrement logic can update register content for
sequential access independent of ALU
Multiply and Accumulate
 Current Program Status Register (flag register)

Q J

Condition code flags

J Bit
– N = Negative result from ALU
– J = 1: Processor in Jazelle state
– Z = Zero result from ALU
(Jazelle state supports JAVA byte code execution)
– C = ALU operation Carried out
T Bit
– V = ALU operation oVerflowed
– Architecture xT only
– Q = result Saturated/Overflowed
– T = 0: Processor in ARM state
Interrupt Disable bits.
– T = 1: Processor in Thumb state
– I = 1: Disables the IRQ.
Mode bits
– F = 1: Disables the FIQ.
– Specify the processor mode
ARM processor modes
 ARM Processor Modes

 The ARM has seven basic operating modes:

 User : unprivileged mode under which most tasks run

 FIQ : entered when a high priority (fast) interrupt is raised
 IRQ : entered when a low priority (normal) interrupt is raised
 Supervisor : entered on reset and when a Software Interrupt
instruction is executed. (OS Kernel operates)
 Abort : used to handle memory access violations
 Undefined : used to handle undefined instructions
 System : privileged mode using the same registers as user mode
 Processor modes

 Processor modes determine

• Which registers are active and
• Access rights to CPSR register itself
 Each processor mode is either
• Privileged: full read-write access to the CPSR
• Non-privileged: only read access to the control field of the CPSR
but read-write access to the condition flags
 ARM has seven modes
Privileged: abort, fast interrupt request, interrupt request,
supervisor, system and undefined
Non-privileged: user
• User mode is used for program and applications
 ARM Register Set
 General purpose registers hold either data or address
 All registers are of 32 bits
 In user mode, 16 data registers and 2 status registers are visible
 Data registers: r0 to r15
• Three registers r13, r14 and r15 perform special functions
• r13: stack pointer
• r14: link register (where, return address is stored whenever a
subroutine is called)
• r15: program counter
 Depending upon context r13 and r14 can also be used as general
purpose registers (GPR)
Any instruction which use r0 can as well be used with any other
GPR(r1-r13)
 In addition, there are two status registers
CPSR: Current Program Status Register
SPSR: Saved Program Status Register
ARM Register Set
Q J
Q J
User Registers replaced
by banked registers
 Banked Registers

 Register file contains 37 registers

• 20 registers are hidden from program at different times.
These registers are called banked registers
• Banked registers are available only when the processor is in
a particular mode
• Processor modes (other than system mode) have a set of
associated banked registers that are subset of 16
registers
• Maps one-to-one onto a user mode register
 SPSR (Stored Program Status Register)

• Each privileged mode (except system mode) has associated

with it a SPSR (Stored Program Status Register)
• This SPSR is used to save the state of CPSR (Current Program
Status Register) when the privileged mode is entered in order
to fully restore the user state when the user process is resumed.
 Mode changing

• Mode changes by writing directly to CPSR or by hardware when

the processor responds to exception (any condition that needs to
halt the normal sequential execution of instructions) or interrupt
• To return to user mode a special return instruction is used that
instructs the core to restore the original CPSR and banked
registers
 Conditional Execution

• An unusual feature of ARM instruction set is that

conditional execution applies not only to branches but to
all ARM instructions
• Example: ADDEQ r0, r1, r2
– Instruction will only be executed when the zero flag is set
to 1
 Advantages of conditional execution

• Reduces the number of branches

– Reduces the number of pipeline flushes
– Improves performance of the code
• Increases code density
• Whenever the conditional sequence is 3 instructions or fewer
(smaller and faster) to exploit conditional execution than to use
a branch
 Comparison of ARM assembly language program codes:
without & with conditional execution

without conditional With conditional execution

execution (using (using condition as suffix of
branching) instruction)
BNE: Branch if not equal EQ: equal
Equality condition will be checked with the corresponding flags
effected from previous CMP operation to execute the current
CMP instruction. CMP instruction effect the ZERO (Z) flag.
 Comparison of ARM assembly language program codes:
without & with conditional execution

#10 #10

With conditional execution

without conditional (using condition as suffix of
execution (using instruction)
branching)
BEQ: Branch if equal NE: Not equal
Not Equal condition will be checked with the corresponding flags
effected from previous CMP operation to execute the current ADD
instruction. CMP instruction effect the ZERO (Z) flag.
Comparison of ARM assembly language program codes:
without & with conditional execution

Note:

• In previous examples, conditional execution resulted in optimized code

(higher code density).
• However, code optimization is not guaranteed with conditional execution
in all cases.
• In some applications, both conditional execution and branching may give
same code density.
ARM Program example and comparison with
high level language construct
 Exception/Interrupt
& Interrupt vector table
 Exception/Interrupt
& Interrupt vector table
Interrupt/Exception priorities in ARM
ARM change its mode when particular exception occurs.
Interrupt/Exception handling
Interrupt/Exception handling
 ARM Memory organisation
Can be configured as little endian or big
endian
Little endian
Big endian
 Memory organization contd..
 "Little Endian" means that the low-order byte of the number
is stored in memory at the lowest address, and the high-order
byte at the highest address. (The little end comes first.) For
example, a 4 byte Long Int Byte3 Byte2 Byte1 Byte0 will be
arranged in memory as follows:
o Base Address+0 Byte0
o Base Address+1 Byte1
o Base Address+2 Byte2
o Base Address+3 Byte3

 Intel processors (those used in PC's) use "Little Endian" byte

order.
 Memory Organization contd..
 "Big Endian" means that the high-order byte of the
number is stored in memory at the lowest address,
and the low-order byte at the highest address. (The
big end comes first.) Our Long Int, would then be
stored as:
o Base Address+0 Byte3
o Base Address+1 Byte2
o Base Address+2 Byte1
o Base Address+3 Byte0
 Motorola processors (those used in Mac's) use "Big
Endian" byte order.
BECE204L MICROPROCESSORS
AND MICROCONTROLLERS
Dr. Sandeep Moparthi
Assistant Professor
School of Electronics Engineering

1
 ARM - Advanced RISC Machines
RISC- Reduce Instruction Set Computers

Module 7: ARM Instruction Set

ARM Instruction- data processing instructions, branch instructions,
load store instructions, SWI Instruction, Loading instructions,
conditional Execution, Assembly Programming.
Reference:
•Muhammad Ali Mazidi, ARM Assembly Language Programming
& Architecture: 1, 2016, 2nd Edition, Microdigitaled.com

Course Outcomes:
CO5: Infer the architecture of ARM Processor
CO6: Develop the simple application using ARM processor.
 Instructions
 Instructions process data held in registers and access memory
with load and store registers
 Classes of instructions:
o Data processing
o Branch instructions
o Load-store instructions
o Software interrupt instructions
o Program status register instructions
 ARM Data types

 Word is 32 bits long

 Word can be divided into four bytes
 ARM addresses can be 32 bit long
 Address refers to byte
o Address 4 starts at byte 4
 Can be configured at power up as little endian or big endian
mode
 Data processing instructions

 Manipulate data within registers

o MOVE instructions
o Arithmetic instructions
• Multiply instructions
o Logical instructions
o Comparison instructions
 Suffix S on data processing instructions updates flags in
CPSR
 Data processing instructions

• Operands are 32 bit wide; comes from registers or specified

as literal (immediate data) in the instruction itself
• Second operand send to ALU via barrel shifter
• 32-bit result placed in register; long multiply instruction
produces 64 bit result
 Data processing instructions
Move instruction
 MOV Rd, N
o Rd: Destination register
o N: can be an immediate value or source register
o Example: MOV r7, r5

o MVN Rd, N
o Move into Rd not of the 32-bit value from source
(takes the value of Operand2 , performs a bitwise logical
NOT operation on the value, and places the result into Rd)
 Data processing instructions
Using Barrel Shifter
 Enables shifting 32 bit operand in one of the source registers left
or right by a specific no. of positions within the cycle time of
instructions
 Basic barrel shifter operations
o Shift left, shift right, rotate right
 Facilitates fast multiply, division and increases code density
Example : MOV r7, r5, LSL #2
 Data processing instructions
Arithmetic instructions
 Implements 32 bit addition and subtraction
 3 operand form
Examples
ADD r0, r1, r2
SUB r0, r1, r2
Subtract value stored in r2 from that of r1 and store in r0
• No flag will be effected after arithmetic operation.
• Since there is no S appended at the end of arithmetic instruction,
this will not update/effect the status of corresponding flags after
the operation.
 Data processing instructions
Arithmetic instructions
 Implements 32 bit addition and subtraction
 3 operand form
Examples
ADDS r0, r1, r2
SUBS r1, r1, #1
Subtract 1 from r1 and store result in r1 and update Z and C
flags
S is appended at the end of arithmetic instruction. This will
update/effect the status of corresponding flags after the
operation.
ADC : Present addition along with previous carry;
SBC : Subtract with previous carry/barrow.
 Data processing instructions
Arithmetic instructions with barrel shifter
 Use of barrel shifter with arithmetic and logical instructions
increases the set of possible available operations
 Example
o ADD r0, r1, r1 LSL #1
Register r1 is shifted to the left by 1, then it is added with r1
and the result (3 times of r1) is stored in r0.
 Data processing instructions
Multiply instructions
• Multiply contents of a pair of registers
 Long multiply generates 64 bit result
Examples
 MUL r0, r1, r2
Multiplying two 32-bit numbers together gives rise to a 64-bit
number. The MUL instruction only stores the lower 32 bits of
the product in the specified destination.
 UMULL r0, r1, r2, r3 (r15 not allowed as operand.)
UMULL interprets the values from Rn and Rm as unsigned
integers. (r0 and r1 are the destinations of higher and lower 32-
bit of the 64-bit result, respectively.)
 Number of cycles taken for execution of multiply instruction
depends upon processor implementation
 Data processing instructions
Logical instructions
 Bit wise logical operations on the two source registers
o AND, OR , Ex-OR, bit clear
o Example : BIC r0, r1, r2
o r2 contains a binary pattern where every binary 1 in
r2 clears a corresponding bit location in register r1.
R0 = R1 and (~R2)
o Useful in manipulating status flags and interrupt masks
 Data processing instructions
Compare instructions
• Enables comparison of 32 bit values
– Updates CPSR flags but do not affect other registers
Examples
compare :
CMP R1, R2 Update CPSR on R1-R2
compare negated :
CMN R1, R2 Update CPSR on R1+R2
bit test :
TST R1, R2 Update CPSR on R1 and R2
test equal :
TEQ R1, R2 Update CPSR on R1 xor R2
 Addressing modes
• Register addressing mode-
– All operands are registers which carries data
• Immediate addressing mode
- One of the operand is immediate data
• Direct addressing mode (Not allowed in ARM)
- One of the operand is memory address
 Addressing modes (continued)
• Scaled Addressing modes
o Address is calculated using the base address register and a barrel
shift operation
There are different scaled addressing modes that can be used for load
and store operations.
o Register indirect addressing- the address is in a register.
LDR R0, [R1] @ address pointed to by R1
o Pre-indexed addressing - An offset address will be added to the
base address which is present in base register before the memory
access.
The form of this is LDR Rd, [Rn, Op2].
The offset can be positive or negative and can be an immediate
value or another register with an optional shift applied.
LDR R0, [R1, R2] @ address pointed to by R1 + R2
LDR R0, [R1, R2, LSL #2] @ address is R1 + (R2*4)
 Addressing modes (continued)
• Scaled Addressing modes (continued)
o Pre-indexed with write-back : this is indicated with an
exclamation mark (!) appended after the instruction. After the
completion of memory access, the base register will be updated
by adding the offset value.
LDR R0, [R1, #32]! @ address pointed to by R1 + 32,
then R1=R1 + 32

o Post-index with write-back : here, the offset value is written after

the square bracket. The address from the base register only is
used for the memory access, with the offset value added to the
base register after the memory access.
LDR R0, [R1], #32 @ read R0 from address pointed to by
R1, then R1:=R1 + 32
Pre or Post Indexed Addressing with STR (store)
instruction
 Pre-indexed: STR r0,[r1,#12]
Offset r0
Source
12 0x20c 0x5 0x5 Register
for STR
r1
Base
Register 0x200
0x200

Auto-update form: STR r0,[r1,#12]!

 Post-indexed: STR r0,[r1],#12

Updated r1 Offset
Base 0x20c 12
Register 0x20c
r0
Source
Original r1 0x5 Register
Base 0x5 for STR
0x200
Register 0x200
 LOAD/STORE instructions
 LOAD operation mans placing data in to register.
 STORE operation means placing data in to memory.
 LOAD/STORE instructions are used to transfers data between
memory and processor registers
• Single register transfer
• Data types supported are signed and unsigned words (32
bits), half-words (16 bits) and bytes
• Multiple-register transfer
• Transfers multiple registers between memory and the
processor in a single instruction
• Swap
• Swap content of a memory location with the contents of
the register
 LOAD/STORE instructions
Single Transfer instructions
 Load and Store data on a boundary alignment
• LDR, LDRH, LDRB;
• Load (word, half-word, byte)
• STR, STRH, STRB;
• Store (word, half-word, byte)
• Supports different addressing modes:
• Register indirect: LDR r0, [r1]
• Pre-indexed:
• LDR r0, [r1, #4]
• 12 bit offset added to the base register
• LDR r0, [r1, -r2]
• Address calculated using base register and another
register
 LOAD/STORE instructions for
Multiple Register Transfer
 “Load/store multiple (LDM/STM)” instructions transfer multiple
register contents between memory and the processor in a single
instruction
 LDM instruction loads the content of memory in to registers.
 STM instruction stores the content of registers in to memory.
 The base register Rn given in the instruction determines source or
destination address (also called base address from/to which data
transfer starts).
 LDM/STM are More efficient – for moving blocks of memory,
saving and restoring context and stack
 These instructions can increase interrupt latency
o Usually instruction executions are not interrupted in ARM
o Interrupt latency is the time taken for the initiation of
interrupt service after the interrupt request is invoked.
 R0 is incrementing 4-times after
each data transfer since we are
dealing with 32-bit data which
occupies 4-memory locations.

LDM instruction loads the content of memory in to registers. In the

above example, The address of the starting memory location is given in R0.
This starting address is called BASE ADDRESS. From this address, the
content of R0 will be incremented 4-times for every data transfer since IA
is the suffix.
 Stack Processing
• ARM architecture uses the “load store multiple (LDM/STM)”
instructions to carry out stack operations.
• LDM can be used to POP the stack contents in to registers.
• STM can be used to PUSH the contents of the registers in to stack
memory locations.
• Stack is a memory area which is reserved to store temporary data
when interrupt/exception occurs.
• Ascending –stack grows towards higher memory address
• Descending –stack grows towards lower memory address
• Full – Stack pointer register (SP) points to the last item on the
stack (up to which the stack is full).
• Empty - SP points the available empty memory location (after the
last item on the stack) which is ready to occupy.
 Modes of Stack Operation
• ARM Multiple register transfer instructions support
– Full ascending: grows up, SP points to the highest address
containing a valid item
– Empty ascending: grows up, SP points to the first empty
location above stack
– Full descending: grows down, SP points to the lowest address
containing a valid data
– Empty descending: grows down, SP points to the first location
below stack
Addressing Methods for Stack
Operations
Stack Pointer (SP) will update (increment/decrement) 4-times after each
data transfer since we are dealing with 32-bit data which occupies
4-memory locations.
 SWAP Instruction
• Special case of load store instruction
• Swap instructions
– SWP: swap a word between memory and register
– SWPB: swap a byte between memory and register
 Control Flow instructions

• Branch instructions
• Conditional branches
• Conditional execution
• Branch and link instructions
• Subroutine (sub-program) return instructions
 Software Interrupt Instruction (SWI)

• A software interrupt instruction Instruction also forces the

processor to Supervisor (SVC) mode, which allows an operating
system routine to execute

• This provides a mechanism for the processor to move from

application routine to OS routines.

• SWI is typically executed in user mode

• When the processor executes an SWI instruction, it sets the

program counter to the offset 0x08 in the vector table
 SWI

• Instruction: SWI {<cond>} SWI_number

• Each SWI has an associated SWI number which is used to
represent a particular function call or feature
• Parameter passing – through registers; Return value is also
passed using registers
 Program Status Register Instructions

Two instructions to control PSR directly

• MRS – transfers register contents of either Current Program
Status Register (CPSR) or Saved Program Status Register
(SPSR) into a register
• MSR – transfers contents of register to CPSR or SPSR
 Subroutine return instructions
• No specific RET (return) instructions provided in ARM.
• The program counter register (PC) is used to carry the memory
location address of the instruction which is currently under
execution. This will be auto updated when the processor executes
the successive instruction in the program.
• Generally, the content of PC will be preserved in to link register
(r14) while redirecting from main program to sub-program
(subroutine).
• Can return from the subroutine (sub-program) to main program by
retrieving the address of the main program (from where it is
redirected to sub-program) in to PC.
• Example instruction to retrieve the preserved PC content from r14
is as follows.
MOV PC, r14
 Branch instruction
• Unconditional Branch instruction: B label
– Example: B forward
– Address label is stored in the instruction as a signed pc-
relative offset
• Conditional Branch: B <cond> label
– Example: BNE loop
– Branch has a condition associated with it and executed if
condition codes have the correct value
• Branch and Link
• Perform a branch, save the address following the branch in
the link register, r14
– Example: BL subroutine
 Coprocessor Instructions
• Coprocessor can be connected to ARM (main processor) to perform
complex arithmetic operations/image processing/graphics
processing.
• Used to extend the instruction set
– Used by cores with a coprocessor
– Coprocessor specific operations
• Syntax: Coprocessor data processing
– CDP{<cond>} cp, opcode1, Cd, Cn, Cm, {,opcode2}
• Cp represents coprocessor number between p0 to p15
• Opcode fields describes coprocessor operation
• Cd, Cn, Cm coprocessor registers
• Coprocessor register transfer and memory transfer instructions are
also available.
Examples: Assembly language programs of ARM
Example 1: Show the flag bits of status register after the execution of
each instruction in the following code. Identify the addressing mode of
each instruction in the given program.
data R4 carries the address of memory location
LDR R2,[R4] ; R2 [R4] where data is stored.
MOV R3,#0x0FH ; R3 = 0x0FH 0x0FH is a 32-bit data.
ADDS R3,R3,R2 ; R3 = R3+R2
ADD R3,R3,#0x07H ; R3 = R3+0x07H 0x07H is a 32-bit data
MOV R1,R3 ; R1 = R3

Solution:
Instruction 1: No flag will be effected through data transfer. It is in
register indirect addressing mode.
Instruction 2: No flag will be effected through data transfer. It is in
immediate addressing mode.
Examples: Assembly language programs of ARM
Example 1: Show the flag bits of status register after the execution of
each instruction in the following code. Identify the addressing mode of
each instruction in the given program.
data R4 carries the address of memory location where data
LDR R2,[R4] ; R2 [R4] is stored.
MOV R3,#0x0FH ; R3 = 0x0FH 0x0FH is a 32-bit data.
ADDS R3,R3,R2 ; R3 = R3+R2
ADD R3,R3,#0x07H ; R3 = R3+0x07H 0x07H is a 32-bit data
MOV R1,R3 ; R1 = R3

Solution (continued):
Instruction 3: Carry flag will be effected after addition. It is in
Register addressing mode.
S is appended at the end of arithmetic instruction. This will
update/effect the status of corresponding flags after the operation.
Examples: Assembly language programs of ARM
Example 1: Show the flag bits of status register after the execution of
each instruction in the following code. Identify the addressing mode of
each instruction in the given program.
data R4 carries the address of memory location where data
LDR R2,[R4] ; R2 [R4] is stored.
MOV R3,#0x0FH ; R3 = 0x0FH 0x0FH is a 32-bit data.
ADDS R3,R3,R2 ; R3 = R3+R2
ADD R3,R3,#0x07H ; R3 = R3+0x07H 0x07H is a 32-bit data
MOV R1,R3 ; R1 = R3

Solution (continued):
Instruction 4: No flag will be effected after addition. It is in
immediate addressing mode.
Since there is no S appended at the end of arithmetic instruction, this
will not update/effect the status of corresponding flags after the
operation.
Examples: Assembly language programs of ARM
Example 1: Show the flag bits of status register after the execution of
each instruction in the following code. Identify the addressing mode of
each instruction in the given program.
data R4 carries the address of memory location where data
LDR R2,[R4] ; R2 [R4] is stored.
MOV R3,#0x0FH ; R3 = 0x0FH 0x0FH is a 32-bit data.
ADDS R3,R3,R2 ; R3 = R3+R2
ADD R3,R3,#0x07H ; R3 = R3+0x07H 0x07H is a 32-bit data
MOV R1,R3 ; R1 = R3

Solution (continued):
Instruction 5: No flag will be effected through data transfer. It is in
register addressing mode.

Similar arithmetic instructions available in ARM:

ADC (Addition with carry) :Present addition along with previous carry;
SBC (Subtract with carry): Subtract with previous carry (barrow).
Examples: Assembly language programs of ARM
Example 2: Write an ARM assembly language program (ALP) for the
expression z =.(a << 2) | (b & 15H)

Solution:
Examples: Assembly language programs of ARM
Example 3: Optimize the following code which is written using
branching. Hint: Use conditional execution.

Solution:
CMP R0,#0x5H
ADDNE R1,R1,R0
SUBNE R1,R1,R2
------
------ Remaining
------ code continues

NE: Not equal.

Condition will be checked with the
corresponding flags effected from previous
operation to execute the current
instruction. CMP instruction effect the
BEQ: Branch if equal ZERO (Z) flag.
Examples: Assembly language programs of ARM
Example 4: Write an ARM assembly language program (ALP) for the
following expression.
If ((R0 = = R1) & (R2 = = R3)) R4++
Solution:

using branching

BNE: Branch if not equal

Note: In above example, conditional execution resulted in optimized code (higher code
density). However, code optimization is not guaranteed with conditional execution in all cases.
In some applications, both conditional execution and branching may give same code density.
Examples: Assembly language programs of ARM
Example 5: Write an ARM assembly language program (ALP) for the
following expression.
4H+5H-19H
Solution:

MOV R0,#0x04H ; R0 = 0x04H 0x04H is a 32-bit number.

ADD R0,R0,#0x05H ; R0 = R0 + 0x05H 0x05H is a 32-bit number.
SUB R0,R0,#0x19H ; R0 = R0 + 0x19H 0x19H is a 32-bit number.

Note: In above program, No flags will be effected after arithmetic

operations since there is no S appended at the end of the arithmetic
instructions.
S represents flag status update.
Examples: Assembly language programs of ARM
Example 6: Try to write the following assembly language programs
(ALPs) for ARM/8051/8086.
i) Degree Celsius to Fahrenheit conversion.
ii) Fahrenheit to degree Celsius conversion.

Hint: see the following formulas

Degree Celsius to Fahrenheit conversion formula :

F = (C × 9/5) + 32

Fahrenheit to Celsius conversion formula :

C = (F − 32) × 5/9