SYLLABUS

Course Code COURSE NAME L T P C

CS3351 Digital Principles And Computer Organization 3 0 2 4

COURSE OBJECTIVES :

● To analyze and design combinational circuits.

● To analyze and design sequential circuits
● To understand the basic structure and operation of a digital computer.
● To study the design of data path unit, control unit for processor and to familiarize with
the hazards.
● To understand the concept of various memories and I/O interfacing.
UNIT I COMBINATIONAL LOGIC 9
Combinational Circuits – Karnaugh Map - Analysis and Design Procedures – Binary Adder –
Subtractor – Decimal Adder - Magnitude Comparator – Decoder – Encoder – Multiplexers -
Demultiplexers
UNIT II SYNCHRONOUS SEQUENTIAL LOGIC 9
Introduction to Sequential Circuits – Flip-Flops – operation and excitation tables, Triggering of
FF,Analysis and design of clocked sequential circuits – Design – Moore/Mealy models, state
minimization, state assignment, circuit implementation - Registers – Counters
UNIT III COMPUTER FUNDAMENTALS 9
Functional Units of a Digital Computer: Von Neumann Architecture – Operation and
Operands ofComputer Hardware Instruction – Instruction Set Architecture (ISA): Memory
Location, Addressand Operation – Instruction and Instruction Sequencing – Addressing
Modes, Encoding ofMachine Instruction – Interaction between Assembly and High Level
Language.
UNIT IV PROCESSOR 9
Instruction Execution – Building a Data Path – Designing a Control Unit – Hardwired Control,
Microprogrammed Control – Pipelining – Data Hazard – Control Hazards.

UNIT V MEMORY AND I/O 9

Memory Concepts and Hierarchy – Memory Management – Cache Memories: Mapping and
Replacement Techniques – Virtual Memory – DMA – I/O – Accessing I/O: Parallel and Serial
Interface – Interrupt I/O – Interconnection Standards: USB, SATA

TOTAL: 45 Periods
CONTENT BEYOND SYLLABI: Basics of logic gates

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 COURSE OUTCOMES:
After the successful completion of this course, the student will be able to

CO1:Designvariouscombinationaldigitalcircuitsusinglogicgates
CO2:Designsequentialcircuits and analyze the design procedures
CO3:State the fundamentals of computer systems and analyze the execution of an
instruction
CO4:Analyze different types of control design and identify hazards
CO5:Identifythecharacteristicsofvariousmemory systems and I/O communication

TEXT BOOKS:

T1. M. Morris Mano, Michael D. Ciletti, “Digital Design : With an Introduction to the
Verilog HDL,VHDL, and System Verilog”, Sixth Edition, Pearson Education, 2018.

T2. David A. Patterson, John L. Hennessy, “Computer Organization and Design, The
Hardware/Software Interface”, Sixth Edition, Morgan Kaufmann/Elsevier, 2020.

REFERENCE BOOKS/LINKS:

R1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, Naraig Manjikian, “Computer
Organization and Embedded Systems”, Sixth Edition, Tata McGraw-Hill, 2012.

R2. William Stallings, “Computer Organization and Architecture – Designing for

Performance”, Tenth Edition, Pearson Education, 2016.

R3. M. Morris Mano, “Digital Logic and Computer Design”, Pearson Education, 2016.

PLAN OF DELIVERY

Sl. Topic Covered Ref. Page No Hrs Cumul Teaching Teaching

No Book ative Aid Methodology
Code Hours (If any)

UNIT-I COMBINATIONAL LOGIC

1. Combinational Circuits R3 103-127 1 1 BP -

2. Karnaugh Map R3 103-127 1 2 BP -

3. Analysis and Design R3 103-127 1 3 BP -

Procedures
4. Binary Adder Subtractor R3 137-138 1 4 BP -
109-110

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Sl. Topic Covered Ref. Page No Hrs Cumul Teaching Teaching
No Book ative Aid Methodology
Code Hours (If any)

5. Decimal Adder R3 138-142 1 5 BP -

6. Magnitude Comparator R3 145-146 1 6 BP -

7. Decoder – Encoder R3 147-154 1 7 BP -
8. Multiplexers R3 156-160 1 8 BP Think,Pair,
Share
9. Demultiplexers R3 156-160 1 9 BP -
UNIT-II SYNCHRONOUS SEQUENTIAL LOGIC

10. Introduction to Sequential R3 180-184 1 10 BP

Circuits
11. Flip-Flops R3 180-184 1 11 BP Apply and
Solve
12. Operation and excitation R3 185-192 1 12 BP Think,Pair,
tables Share
13. Triggering of FF R3 185-192 1 13 BP
14. Analysis and design of R3 193-197 1 14 BP
clocked sequential circuits
15. Design – Moore/Mealy R3 198-203 1 15 BP
models,
16. State minimization R3 198-203 1 16 BP Think,
Pair,Share
17. State assignment R3 198-203 1 17 BP
18. Circuit implementation, R3 230-234 1 18 BP
Registers Counters 215-217
UNIT-III COMPUTER FUNDAMENTALS
19. Functional Units of a Digital TI 351-355 1 19 BP+PPT
Computer: Von Neumann
Architecture
20. Operation and Operands of TI 351-355 1 20 BP+PPT
Computer Hardware
Instruction
21. Instruction Set Architecture R1 128-140 1 21 BP+PPT
(ISA): Memory Location
22. Address and Operation R1 128-140 1 22 BP+PPT
23. Instruction and Instruction R1 128-140 1 23 BP+PPT
Sequencing
24. Addressing Modes R1 140-145 1 24 BP+PPT
25. Encoding of Machine R1 182-184 1 25 BP+PPT
Instruction
26. Interaction between Assembly R1 148-154 1 26 BP+PPT Substitution,
and High-Level Language. Elimination

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Sl. Topic Covered Ref. Page No Hrs Cumul Teaching Teaching
No Book ative Aid Methodology
Code Hours (If any)

27. Interaction between Assembly R1 148-154 1 27 BP+PPT

and High-Level Language.
UNIT-IV PROCESSOR
28. Introduction Notes 1 28 BP+PPT
29. Instruction Execution R1 155-157 1 29 BP+PPT Substitution,
Elimination
30. Building a Data Path R1 161-163 1 30 BP+PPT Substitution,
Elimination
31. Designing a Control Unit R1 175-177 1 31 BP+PPT Substitution,
Elimination
32. Hardwired Control R1 175-177 1 32 BP+PPT Substitution,
Elimination
33. Microprogrammed Control R1 183-184 1 33 BP+PPT
34. Pipelining R1 194-196 1 34 BP+PPT
35. Data Hazard T1,T2 609-610, 1 35 BP+PPT
363-384
36. Control Hazards T1,T2 609-610, 1 36 BP+PPT
363-384
UNIT-V MEMORY AND I/O
37. Memory Concepts and R1 268-269 1 37 BP+PPT
Hierarchy
38. Memory Management R1 288-289 1 38 BP+PPT
39. Cache Memories R1, R2 310-311, 1 39 BP+PPT
120-131
40. Mapping and Replacement R1 291-297 1 4045 BP+PPT
Techniques
41. Virtual Memory R1 305-306 1 41 BP+PPT
42. DMA, I/O, Accessing I/O R1 96-97 1 42 BP+PPT Substitution,
Elimination
43. Parallel and Serial Interface R1 238-243 1 43 BP+PPT
44. Interrupt I/O R1 247-250 1 44 BP+PPT
45. Interconnection R1 251-258 1 45 BP+PPT
Standards:USB,SATA
Content Beyond Syllabus
46. Digital design using Verilog NPTE - 1 46 BP
L

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 PLAN OF IMPLEMENTATION-Lab Experiments

Number
Sl. of Cumulative
List of Experiments Requirement
No periods periods
planned
Verification of Boolean theorems using logic
1. 2 2
gates.
Design and implementation of combinational
2. 2 4
circuits using gates for arbitrary functions.
Implementation of 4-bit binary
3. 4 8
adder/subtractor circuits.
4. Implementation of code converters. 4 12 As Per
Implementation of BCD adder, encoder and Laboratory
5. 4 16
decoder circuits. Manual
Implementation of functions using
6. 2 18
Multiplexers.
7. Implementation of the synchronous counters. 4 22
8. Implementation of a Universal Shift register. 4 26
Simulator based study of Computer
9. 4 30
Architecture.

ASSESSMENT PLAN

ASSESSMENT SCHEDULE-TEST
TEST DATE
TEST PORTION FOR TEST
NO. PLANNED CONDUCTED
I Unit-I, Unit-II
Internal
Assessment Test
II Unit-III, Unit-IV

I Unit-I
Open Book Test
II Unit-III

ASSESSMENT SCHEDULE-ASSIGNMENT

Group
Assignment No Mode Date of Submission
/Common/Individual
I Written Group

II Seminar Group

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 ASSESSMENT SCHEDULE-LABORATORY

DATE
PLANNED (HAS TO BE
MODEL TEST PORTION FOR TEST FILLED WITH RESPECT
CONDUCTED
TO THE ACADEMIC
CALENDAR)
I All Experiments

ASSESSMENT PATTERN

ITEM Weightage
Internal Assessment I (Theory)
Internal Test -I 60
Assignment -I 40
25
Internal Test -II 60
Assignment -II 40
Internal Assessment II (Laboratory)
Laboratory Model Test 25
25
Laboratory Observation + Record Note 75
End Semester Examination (Theory) 100 35
End Semester Examination
100 15
(Laboratory)
TOTAL 100