1

CMOS Fabrication
Outline 2

• Introduction
• CMOS devices
• CMOS technology
• CMOS logic structures
• CMOS sequential circuits
• CMOS regular structures
CMOS technology 3

• Lithography
• Physical structure
• CMOS fabrication sequence
• Yield
• Design rules
• Other processes
• Advanced CMOS process
• Process enhancements
• Technology scaling
The chip making processes flow 4
Growing the crystal Ingot 5
Czochralski (CZ) method 6
Wafer shaping 7
Wafer shaping 8
CMOS processes at a glance 9
Planarization :Polishing of wafers 10
Photolithography 11
Photolithography processes 12
CMOS technology 13

• An Integrated Circuit is an electronic network fabricated in a

single piece of a semiconductor material
• The semiconductor surface is subjected to various processing
steps in which impurities and other materials are added with
specific geometrical patterns
• The fabrication steps are sequenced to form three dimensional
regions that act as transistors and interconnects that form the
switching or amplification network
Lithography 14

Lithography: process used to transfer patterns to each layer of

the IC
Lithography sequence steps:
• Designer:
• Drawing the layer patterns on a layout editor
• Silicon Foundry:
• Masks generation from the layer patterns in the design data base
• Printing: transfer the mask pattern to the wafer surface
• Process the wafer to physically pattern each layer of the IC
Lithography 15
1 . P h o t o r e s is t c o a tin g
P h o t o r e s is t

Basic sequence
S iO 2
• The surface to be patterned is: S u b s tra te

• spin-coated with photoresist 2 . E x p o s u re

O paque U lt r a v io le t lig h t
• the photoresist is dehydrated in an oven (photo resist:
light-sensitive organic polymer) M ask

• The photoresist is exposed to ultra violet light: U nexposed E xposed

• For a positive photoresist exposed areas become soluble

and non exposed areas remain hard
S u b s tra te

• The soluble photoresist is chemically removed 3 . D e v e lo p m e n t

(development).
• The patterned photoresist will now serve as an etching
mask for the SiO2 S u b s tra te
 Lithography 16
4 . E tc h in g
• The SiO2 is etched away leaving the substrate exposed:
• the patterned resist is used as the etching mask
• Ion Implantation: S u b s tr a te

• the substrate is subjected to highly energized donor or 5 . Io n im p la n t

acceptor atoms
• The atoms impinge on the surface and travel below it
• The patterned silicon SiO2 serves as an implantation mask
S u b s tr a te
• The doping is further driven into the bulk by a thermal
cycle
6 . A ft e r d o p in g

d if f u s io n S u b s tr a te
Lithography 17

• The lithographic sequence is repeated for each physical layer used

to construct the IC. The sequence is always the same:
• Photoresist application
• Printing (exposure)
• Development
• Etching
Lithography 18

Patterning a layer above the silicon surface

1 . P o ly s ilic o n d e p o s itio n 4 . P h o to r e s is t d e v e lo p m e n t
P o ly s il ic o n

S iO 2

S u b s tra te S u b s tra te
2 . P h o to r e s is t c o a tin g 5 . P o ly s ilic o n e tc h in g
p h o t o r e s is t

S u b s tra te S u b s tra te
3 . E x p o s u re U V li g h t
6 . F in a l p o ly s ilic o n p a tte r n

S u b s tra te S u b s tra te
 Lithography 19
• Etching:
a n is o tr o p ic e tc h (id e a l)
• Process of removing unprotected material r e s is t

• Etching occurs in all directions la y e r 1

• Horizontal etching causes an under cut la y e r 2
• “preferential” etching can be used to minimize the
undercut is o tr o p ic e tc h
u n d e rc u t r e s is t
• Etching techniques:
• Wet etching: uses chemicals to remove the unprotected la y e r 1

materials la y e r 2

• Dry or plasma etching: uses ionized gases rendered

chemically active by an rf-generated plasma p re fe r e n tia l e tc h
u n d e rc u t r e s is t

la y e r 1
la y e r 2
 Physical structure 20
Physical structure Layout representation Schematic representation

CVDoxide
Poly gate Metal 1

Source Ldrawn Drain Ldrawn G

NMOS layout representation:
NMOS physical structure:
• p-substrate n+ n+
S D • Implicit layers:
Wdrawn
• n+ source/drain Leffective
B – oxide layers
Gate oxide – substrate (bulk)
• gate oxide (SiO2)
• polysilicon gate p-substrate (bulk) • Drawn layers:
• CVD oxide – n+ regions
• metal 1 – polysilicon gate
• Leff<Ldrawn (lateral doping effects) – oxide contact cuts
– metal layers
 Physical structure 21
Physical structure Layout representation Schematic representation
PMOS physical structure: PMOS layout representation:
CVD oxide
• p-substrate Poly gate Metal 1 • Implicit layers:
• n-well (bulk) Source Drain – oxide layers
Ldrawn Ldrawn G
• p+ source/drain • Drawn layers:
• gate oxide (SiO2) S D – n-well (bulk)
p+ p+ Wdrawn
• polysilicon gate Leffective – n+ regions
B
• CVD oxide Gate oxide – polysilicon gate
n-well (bulk) n-well
• metal 1 – oxide contact cuts
p-substrate
– metal layers
 CMOS fabrication sequence 22
0.Start:
• For an n-well process the starting point is a p-type silicon wafer:
• wafer: typically 75 to 230mm in diameter and less than 1mm thick
1. Epitaxial growth:
• A single p-type single crystal film is grown on the surface of the wafer by:
• subjecting the wafer to high temperature and a source of dopant material
• The epi layer is used as the base layer to build the devices

p-epitaxial layer Diameter = 75 to 230mm

< 1mm
P+ -type wafer
 CMOS fabrication sequence 23
2. N-well Formation:
• PMOS transistors are fabricated in n-well regions
• The first mask defines the n-well regions
• N-well’s are formed by ion implantation or deposition and diffusion
• Lateral diffusion limits the proximity between structures
• Ion implantation results in shallower wells compatible with today’s fine-line processes
Physical structure cross section Mask (top view)
n-well mask
Lateral
diffusion

n-well

p-type epitaxial layer

 CMOS fabrication sequence 24
3. Active area definition:
• Active area:
• planar section of the surface where transistors are build
• defines the gate region (thin oxide)
• defines the n+ or p+ regions
• A thin layer of SiO2 is grown over the active region and covered with silicon nitride

Stress-relief oxide Silicon Nitride Active mask

n-well

p-type
 CMOS fabrication sequence 25
4. Isolation:
• Parasitic (unwanted) FET’s exist between unrelated transistors (Field Oxide FET’s)
• Source and drains are existing source and drains of wanted devices
• Gates are metal and polysilicon interconnects
• The threshold voltage of FOX FET’s are higher than for normal FET’s

P a ra s itic F O X d e v ic e

n+ n+ n+ n+

p -s u b s tra te (b u lk )
 CMOS fabrication sequence 26
• FOX FET’s threshold is made high by:
• introducing a channel-stop diffusion that raises the impurity concentration in the substrate in
areas where transistors are not required
• making the FOX thick
4.1 Channel-stop implant
• The silicon nitride (over n-active) and the photoresist (over n-well) act as masks for the
channel-stop implant
Implant (Boron) channel stop mask = ~(n-well mask)

resit

n-well

p+ channel-stop implant
p-type
CMOS fabrication sequence 27

4.2 Local oxidation of silicon (LOCOS)

• The photoresist mask is removed
• The SiO2/SiN layers will now act as a masks
• The thick field oxide is then grown by:
• exposing the surface of the wafer to a flow of oxygen-rich gas
• The oxide grows in both the vertical and lateral directions
• This results in a active area smaller than patterned

patterned active area

Field oxide (FOX)

n-well
active area after LOCOS

p-type
 CMOS fabrication sequence 28
• Silicon oxidation is obtained by:
• Heating the wafer in a oxidizing atmosphere:
• Wet oxidation: water vapor, T = 900 to 1000ºC (rapid process)
• Dry oxidation: Pure oxygen, T = 1200ºC (high temperature required to achieve an acceptable growth rate)
• Oxidation consumes silicon
• SiO2 has approximately twice the volume of silicon
• The FOX is recedes below the silicon surface by 0.46XFOX

Field oxide

XFOX
0.54 XFOX Silicon surface
0.46 XFOX

Silicon wafer
CMOS fabrication sequence 29
5. Gate oxide growth
• The nitride and stress-relief oxide are removed
• The devices threshold voltage is adjusted by:
• adding charge at the silicon/oxide interface
• The well controlled gate oxide is grown with thickness tox

n - w e ll

p - ty p e

G a t e o x id e
tox tox

n - w e ll

p - ty p e
 CMOS fabrication sequence 30

6. Polysilicon deposition and patterning

• A layer of polysilicon is deposited over the entire wafer surface
• The polysilicon is then patterned by a lithography sequence
• All the MOSFET gates are defined in a single step
• The polysilicon gate can be doped (n+) while is being deposited to lower its parasitic
resistance (important in high speed fine line processes)

P o ly s ilic o n m a s k
P o ly s ilic o n g a te

n -w e ll

p -ty p e
 CMOS fabrication sequence 31
7. PMOS formation
• Photoresist is patterned to cover all but the p+ regions
• A boron ion beam creates the p+ source and drain regions
• The polysilicon serves as a mask to the underlying channel
• This is called a self-aligned process
• It allows precise placement of the source and drain regions
• During this process the gate gets doped with p-type impurities
• Since the gate had been doped n-type during deposition, the final type (n or p) will depend on which dopant is dominant

p+ implant (boron)
p+ mask

n-well
Photoresist
p-type
 CMOS fabrication sequence 32

8. NMOS formation
• Photoresist is patterned to define the n+ regions
• Donors (arsenic or phosphorous) are ion-implanted to dope the n+ source and drain
regions
• The process is self-aligned
• The gate is n-type doped
n+ implant (arsenic or phosphorous)
n+ mask

n-well
Photoresist
p-type
 CMOS fabrication sequence 33
9. Annealing
• After the implants are completed a thermal annealing cycle is executed
• This allows the impurities to diffuse further into the bulk
• After thermal annealing, it is important to keep the remaining process steps at as low
temperature as possible

n - w e ll
n+ p+
p -ty p e
 CMOS fabrication sequence 34
10. Contact cuts
• The surface of the IC is covered by a layer of CVD(Chemical vapour deposition) oxide
• The oxide is deposited at low temperature (LTO) to avoid that underlying doped regions will
undergo diffusive spreading
• Contact cuts are defined by etching SiO2 down to the surface to be contacted
• These allow metal to contact diffusion and/or polysilicon regions

Contact mask

n-well
n+ p+
p-type
 CMOS fabrication sequence 35

11. Metal 1
• A first level of metallization is applied to the wafer surface and selectively etched to
produce the interconnects

metal 1 mask
metal 1

n-well
n+ p+
p-type
 CMOS fabrication sequence 36
12. Metal 2
• Another layer of LTO CVD oxide is added
• Via openings are created
• Metal 2 is deposited and patterned

m e ta l 2
V ia m e ta l 1

n - w e ll
n + p +
p -ty p e
CMOS fabrication sequence 37

13. Over glass and pad openings

• A protective layer is added over the surface:
• The protective layer consists of:
• A layer of SiO2
• Followed by a layer of silicon nitride
• The SiN layer acts as a diffusion barrier against contaminants (passivation)
• Finally, contact cuts are etched, over metal 2, on the passivation to allow for
wire bonding.
Yield 38
Yield tendency
100
• Yield number of good chips on wafer
Y 80
total number of chips
60

40
• The yield is influenced by:

Yield (%)
• the technology
• the chip area
20
• the layout 1.0 defects/cm2
• Scribe cut and packaging also contribute to the final yield 2.5 defects/cm2
5.0 defects/cm2
• Yield can be approximated by: 10
 A D 0 2 4 6 8 10
A - chip area (cm2) Ye Chip edge ( area in mm)
D - defect density (defects/cm2)
Design rules 39

• The limitations of the patterning process give rise to a set of mask

design guidelines called design rules
• Design rules are a set of guidelines that specify the minimum
dimensions and spacings allowed in a layout drawing
• Violating a design rule might result in a non-functional circuit or in a
highly reduced yield
• The design rules can be expressed as:
• A list of minimum feature sizes and spacings for all the masks required in a
given process
• Based on single parameter  that characterize the linear feature (e.g. the
minimum grid dimension).  base rules allow simple scaling
 Design rules 40

Minimum width
• Minimum line-width:
• smallest dimension permitted for any object in the layout drawing
(minimum feature size)
• Minimum spacing:
• smallest distance permitted between the edges of two objects
• This rules originate from the resolution of the optical printing system,
the etching process, or the surface roughness

Minimum spacing
 Design rules 41
• Contacts and vias:
Contact
• minimum size limited by the metal 1
lithography process
• large contacts can result in cracks and n+
voids p

• Dimensions of contact cuts are Contact size

restricted to values that can be d
metal 1
reliably manufactured d
• A minimum distance between the edge n+ diffusion
of the oxide cut and the edge of the Registration tolerance
patterned region must be specified to x2
metal 1
allow for misalignment tolerances
(registration errors) x1
n+ diffusion
 Design rules 42

• MOSFET rules Correct mask sizing

• n+ and p+ regions are formed in two overlap
x
active
steps:
• the active area openings allow the n+

implants to penetrate into the silicon x p-substrate

substrate nselect
• the nselect or pselect provide
photoresist openings over the active Incorrect mask sizing
areas to be implanted
overlap active
• Since the formation of the diffusions x
depend on the overlap of two masks, n+
the nselect and pselect regions must p-substrate
be larger than the corresponding active x nselect

areas to allow for misalignments

 Design rules 43

• Gate overhang: gate overhang

• The gate must overlap the active area

by a minimum amount
• This is done to ensure that a
misaligned gate will still yield a no overhang
structure with separated drain and
source regions
• A modern process has may hundreds of
rules to be verified no overhang
and misalignment
• Programs called Design Rule Checkers Short circuit
assist the designer in that task
Etching 44

• What is Etching
• Steps preceding Etching in IC Fabrication
• Types of Etching
• Simple Idea of Wet Etching
• Plasma Etching
• What is Plasma
• Anisotropy and Selectivity
• Advantage of Plasma Etching over Wet Etching
What is Etching 45

• Simply removing unwanted materials from the surface to form a

required pattern
Steps Preceding Etching in IC Fabrication 46

1.
2.

3. 4.
 Types of Etching 47

• Two types of Etching

• Wet Etching:
• Etching is done by liquid chemicals
• Unmasked areas are etched away by the chemical reactions
(Oxidation and Reduction )

• Plasma Etching (Dry Etching):

• Etching is done exposing the material into bombardment of ions in
Plasma
 Simple idea of Wet Etching 48

• Etchants: KOH, HF, BF6, BCl3

SiO 2  6 HF  H 2 SiF 6  2 H 2 O
 Plasma Etching (Dry Etching) 49
• Faster and Easier way
• Both chemical and ionic species play the roll RF power input
Matching
network

Electrode
RF
generator Plasma
Plasma sheaths

Electrode

G a s in le t Ground Gas outlet,

( A r, C F 4, O 2) pump
What is Plasma 50
• State of mater which consist free electrons and
cations
• Plasma looks similar to the gases
• Plasma is also called as ionised gases
 51

• In Plasma high number of electrons does not

move around in orbits
• Plasma is created when gas is either exposed
to high temp. Or high voltage
 52

• Due to these free electrons and cations Plasma easily

conducts electricity and also produce magnetic field.
• Nature also produces plasma by means of fire and
lightning.
 53

• What happens inside plasma

Dissociation:
CF4 + e-  Ionization:
CF3 + F + e- CF3+ e- CF3+ + 2e-

Excitation:
Dissociative ionization: CF4 + e- CF4* + e-
CF4 + e- 
CF3+ + F + 2e- Recombination:
CF3+ + F + e-  CF4
F + F  F2
 Physical Etching inside the Plasma 54

• Etching species are ions like CF3+ or Ar+ which remove

material by ion-bombardment.
• Ion etching is much more directional (anisotropic) due to
directional acceleration of ions by high E field + Ionic species
+ + + + +

Mask

Film
Anisotropy 55
• Etchant can not distinguishes b/w vertical or
horizontal dimensions (isotropic).
• Anisotropy = 1 – dH/dV
• Wet etching is isotropic and dry etching is anisotropic.
Selectivity 56

• Etchant should distinguish b/w SiO2 and Si wafer.

• Wet Etching is Selective than Dry Etching.
Advantages of Plasma Etching over Wet
Etching 57

• Eliminates handling of dangerous acids and solvents.

• Uses small amounts of chemicals.
• Anisotropic etch profiles.
• High resolution and cleanliness.
• Less undercutting.
• Better process control.