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Unit-III
8255 PPI Architecture
 8255 Internal Architecture
 Operation of Different 8255 Modes
 Control Word of 8255 PPI
 BSR Mode Control Word
 Working Modes of 8255
 The Intel 82C55A is a general purpose programmable I/O device which may be used
with many different microprocessors.
 There are 24 I/O pins which may be individually programmed in 2 groups of 12 and
used in 3major modes of operation.
 The high performance and industry standard configuration of the 82C55A make it
compatible with the 8086.

Functional Block Diagram of 8255:

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Data Bus Buffer

This three-state bi-directional 8-bit buffer is used to interface the 82C55A to the system data
bus. Data is transmitted or received by the buffer upon execution of input or output
instructions by the CPU. Control word and status information are also transferred through the
data bus buffer.

Read/Write and Control Logic

The function of this block is to manage all of the internal and external transfers of both Data
and Control or Status words. It accepts inputs from the CPU Address and Control busses and
in turn, issues commands to both of the Control Groups.

(A0 and A1) Port Select0 and PortSelect1:

These input signals, in conjunction with the RD and WR inputs, control the selection of one
of the three ports or the control word register. They are normally connected to the least
significant bits of the address bus (A1andA2).

(CS)Chip Select: A “low” on this input pin enables the communication between the 82C55A
and the CPU.

(RD) Read : A “low” on this input pin enables 82C55A to send the data or status information
to the CPU on the data bus. In essence, it allows the CPU to “read from” the 82C55A.

(WR) Write : A “low” on this input pin enables the CPU to write data or control words into
the 82C55A.

(RESET) Reset: A “high” on this input initializes the control register to 9Bh and all ports
(A, B, C)are set to the input mode.

Control word Register:

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BSR Control word:

BSR Mode of 8255: Single Bit Set/Reset Feature

Any of the eight bits of PortC can be Set or Reset using a single Output instruction. This
feature reduces software requirements in control-based applications. Operation just as if they
were output ports.When Port C is being used as status/control for Port A or B, these bits can
be set or reset by using the Bit Set/Reset.

I/O Mode of 8255 operating in different modes

There are three basic modes of operation than can be selected by the system
software:
 Mode 0 -Basic Input/Output
 Mode 1 -Strobed Input/Output
 Mode 2 -Bi-directional Bus

Mode 0 (Basic Input/Output ) Basic Functional Definitions:

(i)Two 8-bit ports and two 4-bit ports
(ii)Any Port can be input or output
Mode1-(Strobed Input/Output): Mode1 Basic Function Definitions:
(i) Two Groups (Group A and Group B)
(ii) Each group contains one 8-bit port and one 4-bit control/data port
(iii) The 8-bit data port can be either input or output.
(iv) The 4-bit port is used for control and status of the 8-bit port.
Mode 2 Basic Functional Definitions:
(i) Used in Group A only
(ii) One 8-bit, bi-directional bus Port (Port A) and a 5-bit control Port (Port C)
(iii)The 5-bit control port (Port C) is used for control and status for the 8-bit, bi-directional
bus port (Port A)
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Working modes of 8255:

Interfacing of I/O devices:

INTERFACING LIGHT EMITTING DIODE (LED) WITH 8086

Cathode is connected through a resistor to GND & the Anode is connected to the
Microprocessor pin as shown in Fig.
When the Port Pin is HIGH, the LED is ON &
When the Port Pin is LOW the LED is turned OFF.
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Blinking of LEDs (Turning ON & OFF )

Write explanation about the circuit by own words....

Assembly Program To Turn ON & OFF LEDs Using 8086

MOV AL,80
MOV DX,FFE6
OUT DX,AL
GO: MOV AL,00
MOV DX,FFE0
OUT DX,AL
CALL DELAY
MOV AL,FF
OUT DX,AL
CALL DELAY
JMP GO

DELAY: MOV CX,FFFF

UP: DEC CX
JNZ UP
INT 03
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Interfacing ADC with 8086

Why Analog to Digital?

Signals in the real world are analog: light, sound, temperature, pressure, acceleration or other
phenomenon.
Hence, real-world signals must be converted into digital, using a circuit called ADC (Analog-
to-Digital Converter), before they can be manipulated by digital equipment.
• When you scan a picture with a scanner what the scanner is doing is an analog-to-
digital conversion: it is taking the analog information provided by the picture (light)
and converting into digital.
• When you record your voice on your computer, you are using an analog-to-digital
converter to convert your voice, which is analog, into digital information.

Microprocessor Only Understand Digital Signal, So Real World Analog Signal should
be Converted Into Digital to Process It By Microprocessor

A/D Converter 0804 Family

Features:
• 8-bit successive approximation ADC
• Conversion time 100 us.
• Access time 135 us.
• It has on-chip clock generator.
• It operates on single 5V power supply.
• Output meets TTL voltage level specification.

8 bit ADC, which means we will get digital output 0 to 255. i.e. When the input is 0V, the
digital output will be 0V & when input is 5V (and Vref=5V), we will get the highest digital
output corresponding to 256 steps, which is 5V. ADC has 256 steps and

Step size = 5/256 = 19.53 mV. • Step size with Vref = 5V :

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Timing Diagram
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Interfacing DAC with 8086

The digital to analog converters convert binary numbers into their analog equivalent voltages.
The DAC find applications in areas like digitally controlled gains, motor speed controls,
programmable gain amplifiers, etc.
Features:
To convert the digital signal to analog signal a Digital-to-Analog Converter (DAC) has to be
employed.
• The DAC will accept a digital (binary) input and convert to analog voltage or current.
• Every DAC will have "n" input lines and an analog output.
• The DAC require a reference analog voltage (Vref) or current (Iref) source.
• The smallest possible analog value that can be represented by the n-bit binary code is
called resolution.
• The resolution of DAC with n-bit binary input is 1/2nof reference analog value

Conversion Table:
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DAC Interfacing:

It convert digital pulses into analog signals. Two circuits used are (1. Binary weighted R/2R
ladder network. The vast majority of integrated circuit DACs including MC1408(DAC0808)
use R/2R method because it can achieve a much higher degree of precision. The number of
bits in the digital word is called it’s precision and there are8,10 and 12 bits DACs. The
number of discrete output voltage levels is 2n , where n is the number of bits in the input data.
In DAC0808 (MC1408), the digital inputs are converted to current IOUT and by connecting a
resistor to the IOUT pin, a voltage output is obtained. The total current provided by the IOUT pin
is a function of the binary numbers at the D0 to D7 inputs of the DAC0808 and the Irefcurrent
and it is given by

Generating Analog Wave forms using DAC with 8086:

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Stepper motor interfacing with 8086

A stepper motor is an electric motor that can divide a full rotation into a large number of
steps. It works on the principle of electromagnetism. The most common stepper motors have
four stator windings that are paired with a centre-tapped common. This type of stepper motor
is commonly referred to as four-phase or unipolar stepper motor. The supply voltage is
applied to the common point of the winding and when the other end of the winding is
grounded, current flows into the winding and causing it as an electromagnet. When the
current pulses are applied to the winding in sequence, it rotates in steps.

A stepper motor moves through a small angle when a pulse is applied to its winding. It is
used in disk drive, dot matrix printers, and robotics for position control.

A stepper motor commonly has a permanent magnet rotor surrounded by a stator. There is
also stepper motor called variable reluctance stepper motor which does not have a permanent
magnet rotor.

Rotor alignment Stator winding

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Types of Stepper Motor

 Permanent Magnet Stepper Motor

 Variable Reluctance Stepper Motor
 Hybrid Stepper Motor

Permanent Magnet Stepper Motor:

Two types of Coil Excitation:

Single-Coil Excitation: Two-Coil Excitation - Each successive pair of

Each successive coil is energized in turn. adjacent coils is energized in turn.

Controlling Types:

There are two types of controlling sequence for unipolar stepper motor:
 Half Step Sequence.
 Full Step Sequence.

Step Angle Calculation:

Step Angle, Φ = 360/ No. of steps

Full Sequence:

Step Angle, Φ = 360/4 = 90 degree

Half Sequence:

Step Angle, Φ = 360/8 = 45 degree

Direction for Rotation of Stepper Motor:

Clockwise Rotation,
Anti-Clockwise Rotation

Full Step Sequence:

Here two coils are energized at the same time and motor shaft rotates. The order in which
coils has to be energized is given below.
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STEP Coil-4 Coil-3 Coil-2 Coil-1 Hex

0 1 1 0 0 C
1 0 1 1 0 6
2 0 0 1 1 3
3 1 0 0 1 9

Half Step Sequence:

Here motor's step angle reduces to half the angle than in full mode. So the angular
resolution is also increased i.e., it becomes double the angular resolution than in full mode.
Also in half mode sequence the no. of steps gets double as that of full mode. Half mode is
usually preferred over full mode. The patterns of energizing the coils are:

Step Coil-4 Coil-3 Coil-2 Coil-1 Hex No.

0 1 1 0 0 C
1 0 1 1 0 6
2 0 0 1 1 3
3 1 0 0 1 9
4 0 0 1 1 3
5 0 0 0 1 1
6 1 0 0 1 9
7 1` 0 0 0 8

Drivers
Stepper motor Interfacing needs a Driver Circuit

Types of Driver Circuits:

 Transistor Drivers Usually a Darlington Pair
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INTERFACING OF STEPPER MOTOR WITH 8086

(Rotation in clockwise)

LABEL MNEMONICS COMENTS

MOV AL,80H CWR is copying to accumulator

MOV DX,0FFE6 Initialize the control word register

address
OUT DX,AL Send data to the port [OUT DX ←AL]

MOV AL,88 Initialize the port A address

MOV DX,0FFE0 Initialize the port A address

Up: OUT DX,AL Input data is send to port

MOV CX,0FFF Delay for rotate motor continuously

Here: LOOP Here

ROR AL,1 Initialize of input data to rotate

motor
JMP Up Jump to specified label

(Rotation in anticlockwise)

LABEL MNEMONICS COMENTS

MOV AL,80H CWR is copying to accumulator

MOV DX,0FFE6 Initialize the control word register

address

OUT DX,AL Send data to the port [OUT DX ←AL]

MOV AL,88 Initialize the port A address

MOV DX,0FFE0 Initialize the port A address

Up: OUT DX,AL Input data is send to port

MOV CX,0FFF Delay for rotate motor continuously

Here: LOOP Here

ROL AL,1 Initialize of input data to rotate

motor
JMP Up Jump to specified label
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Architecture of 8259 Interrupt Controller

Programmable Interrupt Controller (8259)

Features:

 It is programmed to work with either 8085 or 8086 processor.

 It manage 8-interrupts according to the instructions written into
its control registers.
 In 8086 processor, it supplies the type number of the interrupt
and the type number is programmable.
 The interrupts can be masked or unmasked individually.
 The 8259s can be cascaded to accept a maximum of 64 interrupts.
FUNCTIONAL BLOCK DIAGRAM OF 8259:

8259 has eight functional blocks. They are,

1. Control logic
2. Read Write logic
3. Data bus buffer
4. Interrupt Request Register (IRR)
5. In-Service Register (ISR)
6. Interrupt Mask Register (IMR)
7. Priority Resolver (PR)
8. Cascade buffer.
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The data bus and its buffer are used for the following activities.
1. The processor sends control word to data bus buffer through D0-D7.
2. The processor read status word from data bus buffer through D0-D7.
3. From the data bus buffer the 8259 send type number (in case of 8086) or the call opcode
and address (in case of 8085) through D0-D7 to the processor.
The processor uses the RD (low), WR (low) and A0 to read or write 8259
• The 8259 is selected by CS (low).
• The IRR has eight input lines (IR0-IR7) for interrupts.
• When these lines go high, the request is stored in IRR.
• It registers a request only if the interrupt is unmasked.
• Normally IR0 has highest priority and IR7 has the lowest priority.
• The priorities of the interrupt request input are also programmable.
First the 8259 should be programmed by sending Initialization Command Word (ICW) and
Operational Command Word (OCW).
These command words will inform 8259 about the following,
• * Type of interrupt signal (Level triggered / Edge triggered).
• Type of processor (8085/8086).
• * Call address and its interval (4 or 8)
• * Masking of interrupts.
• * Priority of interrupts.
• * Type of end of interrupts
• The interrupt mask register (IMR) stores the masking bits of the interrupt lines to be
masked. The relevant information is send by the processor through OCW.
The in-service register keeps track of which interrupt is currently being serviced.
• The priority resolver examines the interrupt request, mask and in-service registers and
determines whether INT signal should be sent to the processor or not.
• The cascade buffer/comparator is used to expand the interrupts of 8259.
• In cascade connection one 8259 will be directly interrupting 8086 and it is called
master 8259.
• To each interrupt request input of master 8259 (IR0-IR7), one slave 8259 can be
connected. The 8259s interrupting the master 8259 are called slave 8259s.
• Each 8259 has its own addresses so that each 8259 can be programmed
independently by sending command words and independently the status bytes can be
read from it.
• The cascade pins (CAS0, CAS1 and CAS2) from the master are connected to the
corresponding pins of the slave.
• For the slave 8259, the SP (low) / EN (low) pin is tied low to let the device know that
it is a slave.
• The SP (low) / EN (low) pin can be used as input or output signal.
• In non-buffered mode it is used as input signal and tied to logic-I in master 8259 and
logic-0 in slave 8259.
• In buffered mode it is used as output signal to disable the data buffers while data is
transferred from 8259A to the CPU.
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Cascade Mode connection of 8259

8257 DMA Controller

Introduction:
DMA stands for Direct Memory Access.
• It is designed by Intel to transfer data at the fastest rate.
• It allows the device to transfer the data directly to/from memory without any
interference of the CPU.
Using a DMA controller, the device requests the CPU to hold its data, address and control
bus, so the device is free to transfer data directly to/from the memory. The DMA data transfer
is initiated only after receiving HLDA signal from the CPU.

How DMA Operations are performed?

Following is the sequence of operations performed by a DMA Initially,

• when any device has to send data between the device and the memory, the device has
to send DMA request (DRQ) to DMA controller.
• The DMA controller sends Hold request (HRQ) to the CPU and waits for the CPU to
assert the HLDA.
• Then the CPU leaves the control over bus and acknowledges the HOLD request
through HLDA signal.
• Now the CPU is in HOLD state and the DMA controller has to manage the operations
over buses between the CPU, memory, and I/O devices.

Features of 8257
• It has four channels which can be used over four I/O devices.
• Each channel has 16-bit address and 14-bit counter.
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• Each channel can transfer data up to 64kb.

• Each channel can be programmed independently.
• Each channel can perform read transfer, write transfer and verify transfer operations.
• It generates MARK signal to the peripheral device that 128 bytes have been
transferred.
• It requires a single phase clock.
• Its frequency ranges from 250Hz to 3MHz.
• It operates in 2 modes, i.e., Master mode and Slave mode.

8257 Architecture

• Each channel of 8257 has two 16-bit registers,

• Address Register
• Terminal Count Register.

There are two common registers for all the channels, namely,
• Mode Set Register
• Status Register.
• Thus there are a total of ten registers.
• Address Register: The function of this register is to store the address of the starting
memory location, which will be accessed by the DMA channel.
• The mode set register is used for programming the 8257 as per the requirements of
the system.
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• The status register: The lower order 4-bits of this register contain the terminal count
status for the four individual channels.
• Terminal Count Register: How many number of DMA cycles transferred.
• The TC pin is activated when the 14-bit content of the terminal count register of the
selected channel becomes equal to zero.
• Register selection

• Terminal Count Register

Description of pins:
• D0-D7:
• it is a bidirectional ,tri state ,Buffered ,Multiplexed data (D0-D7)and (A8-A15).
• In the slave mode it is a bidirectional (Data is moving).
• In the Master mode it is a unidirectional (Address is moving).
• IOR: It is active low ,tristate ,buffered ,Bidirectional lines.
• In the slave mode it function as a input line. IOR signal is generated by
microprocessor to read the contents 8257 registers.
• In the master mode it function as a output line. IOR signal is generated by 8257
during read cycle
• IOW:
• It is active low ,tristate ,buffered ,Bidirectional control lines.
• In the slave mode it function as a input line. IOW signal is generated by
microprocessor to write the contents 8257 registers.
• In the master mode it function as a output line. IOW signal is generated by 8257
during write cycle
• CLK:
• It is the input line ,connected with TTL clock generator.
• This signal is ignored in slave mode.
• RESET:
• Used to clear mode set registers and status registers
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• A0-A3:
• These are the tristate, buffer, bidirectional address lines.
• In slave mode ,these lines are used as address inputs lines and internally decoded to
access the internal registers.
• In master mode, these lines are used as address outputs lines,A0-A3 bits of memory
address on the lines.
• CS:
• It is active low, Chip select input line.
• In the slave mode, it is used to select the chip.
• In the master mode, it is ignored.
• A4-A7:
• These are the tristate, buffer, output address lines.
• In slave mode ,these lines are used as address outputs lines.
• In master mode, these lines are used as address outputs lines,A0-A3 bits of memory
address on the lines.
• READY:
• It is a asynchronous input line.
• In master mode,
• When ready is high it is received the signal.
• When ready is low, it adds wait state between S1 and S3
• In slave mode ,this signal is ignored.
• HRQ:
• It is used to receiving the hold request signal from the output device.
• HLDA:
• It is acknowledgment signal from microprocessor.
• MEMR:
• It is active low ,tristate ,Buffered control output line.
• In slave mode, it is tristated.
• In master mode ,it activated during DMA read cycle.
• MEMW:
• It is active low ,tristate ,Buffered control input line.
• In slave mode, it is tristated.
• In master mode ,it activated during DMA write cycle.
• AEN (Address enable):
• It is a control output line.
• In master mode ,it is high
• In slave mode ,it is low
• Used it isolate the system address ,data ,and control lines.
• ADSTB: (Address Strobe)
• It is a control output line.
• Used to split data and address line.
• It is working in master mode only.
• In slave mode it is ignore.
• TC (Terminal Count):
• It is a status of output line.
• It is activated in master mode only.
• It is high ,it selected the peripheral.
• It is low ,it free and looking for a new peripheral.
•
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• MARK:
• It is a modulo 128 MARK output line.
• It is activated in master mode only.
• It goes high ,after transferring every 128 bytes of data block.
• DRQ0-DRQ3(DMA Request):
• These are the asynchronous peripheral request input signal.
• The request signals is generated by external peripheral device.
• DACK0-DACK3:
• These are the active low DMA acknowledge output lines.
• Low level indicate that ,peripheral is selected for giving the information (DMA
cycle).
• In master mode it is used for chip select.
DATA BUS BUFFER:
• It contain tristate ,8 bit bi-directional buffer.
• Slave mode ,it transfer data between microprocessor and internal data bus.
• Master mode ,the outputs A8-A15 bits of memory address on data lines
(Unidirectional).
READ/CONTROL LOGIC:
• It control all internal Read/Write operation.
• Slave mode ,it accepts address bits and control signal from microprocessor.
• Master mode ,it generate address bits and control signal.
Control logic block:
• It contains ,
1. Control logic
2. Mode set register and
3. Status Register.
CONTROL LOGIC:
• Master mode ,It control the sequence of DMA operation during all DMA cycles.
• It generates address and control signals.
• It increments 16 bit address and decrement 14 bit counter registers.
• It activate a HRQ signal on DMA channel Request.
• Slave ,mode it is disabled.
Application of DMA Controller: