Title: Construction of Logic Gates using various MOS transistors

Objective:
This laboratory experiment targeted the construction of and analysis of MOSFET-based logic
gates; more specifically, NMOS and CMOS logic gates in digital circuits. The focus will be on
the design of NMOS inverter logic gates with both resistive and transistor loads, and then the
construction of a CMOS inverter, NAND, and NOR logic gates will follow. Advantages in the
capability of CMOS technology over NMOS were observed in this experiment, specifically in
power efficiency and logical density. The practical problems that were encountered while
implementing the hardware of CMOS NOR gates were also resolved with the instructor's
assistance, and the experimental results tallied well with the theoretical truth tables as well as the
simulations. The laboratory exercise reinforced the basic concepts of transistor-level design for
logic circuits, emphasizing the power of CMOS technology in modern integrated circuits, since
CMOS transistors offer high noise immunity and very low static power dissipation.

Introduction:
The Metal-Oxide Semiconductor Field-Effect Transistor is broadly utilized in modern electronics
for voltage regulation and switching applications. These transistors are designed in several
different configurations, including both n-channel and p-channel varieties, operating in either
enhancement or depletion modes. The n-channel enhancement mode MOSFETs are commonly
used in digital circuits since they offer high power in switching applications. MOSFETs are
voltage-controlled devices, where a positive voltage at the gate creates an electrostatic field that
forms a conductive channel allowing current to flow between the source and the drain.

CMOS thus combines the use of both n-channel and p-channel MOSFETs in its technology and
is, therefore much more power-efficient compared to NMOS or TTL circuits.
CMOS is known for its high noise immunity and minimal power consumption, as power is only
drawn during switching events, making it ideal for large-scale integrated circuits. CMOS
technology is widely used in microprocessors and other digital logic applications due to its
ability to operate at a wide range of voltages and its low heat dissipation.
In this work, we are going to design and characterize NMOS and CMOS logic gates. From the
structural and principle-of-function analysis, we would attempt to explain increased power
efficiency and performance features of CMOS technology compared to NMOS and TTL circuits
in aspects related to power dissipation and scalability issues in digital logic structures.

Theory and Methodology:

CMOS:
Complementary metal–oxide–semiconductor (CMOS) is a widely used technology for building
integrated circuits. It is commonly found in microprocessors, microcontrollers, static RAM, and
various other digital logic circuits. Beyond digital applications, CMOS technology is also
utilized in analog circuits, including image sensors (known as CMOS sensors), data converters,
and highly integrated transceivers used in diverse communication systems. The CMOS concept
was patented by Frank Wanlass in 1963 (US Patent 3,356,858).
CMOS is sometimes called complementary-symmetry metal–oxide–semiconductor (or COS-
MOS), a name that highlights its use of complementary and symmetrical pairs of p-type and n-
type MOSFETs (metal–oxide–semiconductor field-effect transistors) to implement logic
functions.

CMOS inverter (NOT logic gate)

CMOS devices are known for two key advantages: high noise immunity and low static power
consumption. Because one transistor in each complementary pair is always turned off, the circuit
only draws significant power briefly during switching between on and off states. As a result,
CMOS generates less waste heat compared to other logic families, such as transistor–transistor
logic (TTL) or NMOS logic, which typically consume power continuously, even when not
switching. Additionally, CMOS technology supports a high density of logic functions on a single
chip. This capability played a major role in its widespread adoption for implementing very-large-
scale integration (VLSI) circuits.

Some advantages of CMOS over TTL are:

• CMOS gate inputs draw far less current than TTL inputs, because
MOSFETs are voltage- controlled, not current-controlled, devices.
 • CMOS gates are able to operate on a much wider range of power supply
voltages than TTL: typically 3 to 15 volts versus 4.75 to 5.25 volts for TTL
• CMOS transistors are smaller in size and provide less power dissipation than NMOS
transistors.

In this experiment, we will first look at some logic circuit designs using NMOS. Then we
will implement the same logic circuits using CMOS and try to identify the potential design
advantages of CMOS over NMOS.

CMOS Logic:
CMOS transistors are smaller in size and dissipate less power compared to NMOS transistors,
making them the preferred choice for integrated circuit design across various applications. A
CMOS circuit consists of a pair of MOSFETs—one p-channel (PMOS) and one n-channel
(NMOS). These transistors are engineered to have matching, complementary characteristics.
When a transistor is turned off, it presents an almost infinite resistance; when turned on, its
channel resistance is low, typically around 200 ohms. Since the gate acts as an open circuit, it
draws virtually no current. As a result, the output voltage is either at ground or at the supply
voltage, depending on which transistor is conducting.

CMOS Inverter:
When the input is at ground level (logic 0), the N-channel MOSFET remains off, as no channel
is formed within it, effectively acting as an open circuit and disconnecting the output from
ground. At the same time, the P-channel MOSFET turns on, forming a conductive channel with a
resistance of about 200 ohms, which connects the output to the positive supply voltage (+V).
This causes the output to rise to +V, representing logic 1.
Conversely, when the input is at a high voltage level (logic 1), the P-channel MOSFET turns off,
while the N-channel MOSFET turns on, creating a path to ground and pulling the output down to
0V (logic 0). As a result, the circuit performs logical inversion, while also providing active pull-
up and pull-down capabilities depending on the input state.

Fig.1: CMOS Inverter

Simulation of CMOS Inverter :

CMOS NAND Gate:

Fig.2: CMOS NAND Gate

Simulation of CMOS NAND Gate :

CMOS NOR Gate:

Fig.3: CMOS NOR Gate

Simulation of CMOS NOR Gate :

NMOS Inverter:

Fig.4: NMOS Inverter

Simulation of NMOS Inverter:

NMOS NAND Gate:

Fig.5: NMOS NAND Gate

Simulation of NMOS NAND Gate:

NMOS NOR Gate :

Fig.6: NMOS NOR Gate

Simulation of NMOS NOR Gate :

Designing a Half Adder using CMOS

Introduction:
ADDER:
In electronics, an adder—also known as a summer—is a digital circuit designed to perform
numerical addition. Adders are commonly found not only in the arithmetic logic units (ALUs) of
computers and processors but also in other areas of a processor, where they are used for tasks
such as calculating memory addresses, table indices, and similar functions.
While adders can be designed for various numerical formats like binary-coded decimal or
excess-3, they most commonly operate on binary numbers. When using signed number
representations like two’s complement or one’s complement, converting a basic adder into an
adder-subtractor is relatively straightforward. However, other signed number systems may
require more complex adder designs.

Fig-7: Half adder logic diagram

A half adder is a digital circuit that adds two single-bit binary inputs, labeled A and B. It
produces two outputs: the sum (S) and the carry (C). The carry output indicates an overflow into
the next higher bit position during multi-bit addition. The sum and carry values together
represent the binary result of the addition, with the sum given by the XOR of A and B, and the
carry determined by their AND.
The half adder's basic design uses an XOR gate to produce the sum and an AND gate to generate
the carry. By adding an OR gate to combine carry outputs, two half adders can be connected to
form a full adder. In this context, the two inputs to the half adder are known as the augend and
addend, while the outputs are the sum and carry.

Truth table and equations for the Half adder are :

A B A+B S C
0 0 0 0 0
0 1 1 1 0
1 0 1 1 0
1 1 2 0 1

Theory and Methodology:

To design any logic circuit, the process begins with creating a truth table that outlines all
possible combinations of logic '0' and '1' inputs to determine the desired outputs. Based on
this truth table, a gate-level design is developed. From the gate-level schematic, the circuit is
then translated into a transistor-level design using the appropriate transistors. In this case,
CMOS technology is used to implement the transistor-level design of the half adder.
The whole process is given step wise below:

Half Adder:
Gate Level Design:

Fig-8: Logic diagram of a Half Adder.

Equation of Sum = A (XOR) B

= +
This equation can be rewritten as =
=
Equation of Carry= AB

Apparatus:
(1) PMOS,
(2) NMOS,
(3) IC 7404(Inverter).
(4) Connecting wires.
(5) Trainer Board
(6) 10KΩ resistor (brown-black-orange).
(7) 1N914 diodes or equivalent.
(8) Connecting wires.
(9) Trainer Board.

MOSFET pin configuration:

 Simulation of Half Adder

Question & Answer:

1. For, each of the above set-ups, describe in words what the data means. Did your
results match the expected ideal outputs? If not, explain why?

Inverter: An inverter works with two types of signals: Logic 0 and Logic 1. Logic 0 means the
voltage is low (0V), while Logic 1 means the voltage is high (+5V). From the results of the
simulations, we see that the outputs align with the expected ideal values.

NAND Gate: A NAND gate has four possible combinations of input data, as shown in the truth
table. When both inputs are Logic 0, the inputs are low. When both inputs are Logic 1, the inputs
are high. For combinations like Logic 0/1 and Logic 1/0, one input is low and the other is high.
Just like the inverter, the results of the simulations for the NAND gate matched the expected
ideal outputs.
NOR Gate: The NOR gate also has four possible combinations, shown in the truth table. When
both inputs are Logic 0, at least one input is high. When both inputs are Logic 1, both inputs are
low. For combinations like Logic 0/1 and Logic 1/0, one input is low and the other is high.
Similarly to the inverter, the results of the simulation for the NOR gate matched the expected
ideal outputs.

2. Implement logic function Vout = A+ BC+ DEF using: (a) NMOS (b) CMOS

(a) NMOS
(b) CMOS

3. Document the data acquired from the hardware, from simulation as well as the expected
values for the CarryOut and Sum of the Half Adder.

Expected outputs:

A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Simulation Results:
A B Sum(sim) Carry(sim)
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Hardware Test Results:

A B Sum(HW) Carry(HW)
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Summary
• The expected values, simulation results, and hardware results all match.
• This confirms that the Half Adder is working correctly in both simulated and real
hardware environments.

4. Implementation of CMOS (HW).

Discussion:
In this experiment, we successfully constructed basic logic gates using Metal-Oxide-
Semiconductor (MOS) transistors. The practical implementation of these gates highlighted the
fundamental principles of digital electronics and CMOS (Complementary MOS) technology.
The CMOS inverter (NOT gate) demonstrated how a high input voltage turns off the PMOS and
turns on the NMOS, pulling the output low, and vice versa. For the NAND and NOR gates,
combinations of series and parallel arrangements of NMOS and PMOS transistors were used to
control current paths based on input logic levels. This reinforced the understanding of how logic
functions are physically realized at the transistor level.
One key observation was the significant advantage of CMOS logic in terms of power efficiency,
as current only flows during switching, not in the steady state. Additionally, the experiment
emphasized the importance of correct transistor sizing and layout to ensure proper logic levels
and reliable gate operation.

Conclusion:
The overall outcome was excellent and matched the truth table value. According to the truth
table, all logic gates were behaving perfectly during the simulation period. Finally, the results of
the simulations and our experiment were compared and found to be identical. Due to lack of
time, the CMOS NOR gate was only implemented in the laboratory. However, all the
simulations were done using Multisim.

References:
[1] M. M. Mano, Digital Logic and Computer Design. Englewood Cliffs, NJ: Prentice-Hall,
1979.
[2] R. Jacob Baker, CMOS: Circuit Design, Layout, and Simulation, 3rd ed., Hoboken, NJ:
Wiley-IEEE Press, 2010.
[3] N. Weste and D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective, 4th ed.,
Boston, MA: Addison-Wesley, 2010.
[4] K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, "Leakage current mechanisms and
leakage reduction techniques in deep-submicrometer CMOS circuits," Proceedings of the IEEE,
vol. 91, no. 2, pp. 305–327, Feb. 2003.
[5] S. Borkar, "Design challenges of technology scaling," IEEE Micro, vol. 19, no. 4, pp. 23–29,
Jul. 1999. Available: https://ieeexplore.ieee.org/document/772079