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UNIT 1

8085 PROCESSOR

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CONTENTS

Technical Terms
1.1 Introduction to Microprocessor Based System
1.2 Intel 8085 – Pin Diagram & Description
1.2.1 Classification of signals
1.2.2 Pin Description
1.3 Intel 8085 Architecture
1.4 Intel 8086 – Pin Diagram & Description
1.4.1 Classification of signals
1.4.2 Pin Description
1.4.3 Minimum Mode Signals
1.4.4 Maximum Mode Signals
1.5 Intel 8086 Architecture
1.6 Memory Interfacing
1.6.1 Typical EPROM and Static RAM
1.6.2 Decoder
1.7 Timing Diagram
1.7.1 Machine Cycles of 8085
1.8 I/o ports and Data Transfer Concepts
1.9 8085 Interrupts
1.9.1 Need for Interrupts
1.9.2 Types of Interrupts
1.9.3 Software Interrupts
1.9.4 Hardware Interrupts
1.9.5 Vectored & Non Vectored Interrupts
1.9.6 Maskable & Non Maskable Interrupts
2.0 8086 Interrupts

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Technical terms

1. Microprocessor : It is a program controlled semiconductor device (IC}, which

fetches, Decode and executes instructions
2. Assembly Language: The languages in which the mnemonics (short -hand form of
Instructions) are used to write a program are called assembly language. The
manufacturers of microprocessor give the mnemonics.
3. Bit: A digit of the binary number or code is called bit. Also, the bit is the fundamental
storage unit of computer memory.
4. Byte : The 8-bit (8-digit) binary number or code is called byte
5. Word: 16-bit binary number or code is called word. (Some microprocessor
manufactures refer the basic data size operated by the processor as word).
6. Bus: Bus is a group of conducting lines that carries data, address and control signals.
7. Opcode: Opcode (Operation code) is the part of an instruction / directive that
identifies a specific operation.
8. Operand: Operand is a part of an instruction / directive that represents a value on
which the instruction acts.
9. Interrupt: In the second T -state of the last machine cycle of every instruction, the
8085 processor checks whether an interrupt request is made or not.
10. Software interrupts: The Software interrupts are program instructions. These
instructions are inserted at desired locations in a program. While running a Program,
if software interrupt instruction is encountered then the processor executes an
interrupt service routine.
11. Hardware interrupt: If an interrupt is initiated in a processor by an appropriate
signal at the interrupt pin, then the interrupt is called Hardware interrupt.
12. TRAP: The TRAP is non-mask able interrupt of8085. It is not disabled by processor
reset or after reorganization of interrupt.
13. Flag: Flag is a flip flop used to store the information about the status of the processor
and the status of the instruction executed most recently.
14. ALE: The ALE (Address Latch Enable) is a signal used to demultiplex the address
and data lines, using an external latch. It is used to enable the external latch.

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15. Polling: Polling is a scheme or an algorithm to identify the devices interrupting the
processor. Polling is employed when multiple devices interrupt the processor through
one interrupt pin of the processor.
16. Pipelined Architecture In pipelined architecture the processor will have number of
functional units and the execution time of functional units is overlapped. Each
functional unit works independently most of the time.
17. Segment Registers Programmable registers that allow multitasking and are used to
store program code and data in separate segments
18. Instruction Queue FIFO group of registers

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1.1 Introduction to Microprocessor Based System

The microprocessor is a semiconductor device (Integrated Circuit) manufactured by

the VLSI (Very Large Scale Integration) technique. It includes the ALU, register arrays and
control circuit on a single chip. To perform a function or useful task we have to form a
system by using microprocessor as a CPU and interfacing memory, input and output devices
to it. A system designed using a microprocessor as its CPU is called a microcomputer. The
Microprocessor based system (single board microcomputer) consists of microprocessor as
CPU, semiconductor memories like EPROM and RAM, input device, output device and
interfacing devices. The memories, input device, output device and interfacing devices are
called peripherals. The popular input devices are keyboard and floppy disk and the output
devices are printer, LED/LCD displays, CRT monitor, etc.

Figure 1.1 Microprocessor Based System

In the µP based system, the microprocessor is the master and all other peripherals are
slaves. The master controls all the peripherals and initiates all operations. The work done by
the processor can be classified into the following three groups.
• Work done internal to the processor
• Work done external to the processor
• Operations initiated by the slaves or peripherals.

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The works done internal to the processors are addition, subtraction, logical operations,
data transfer operations, etc. The work done external to the processor are reading/writing the
memory and reading/writing the J/O devices or the peripherals. If the peripheral requires the
attention of the master then it can interrupt the master and initiate an operation.
The microprocessor is the master, which controls all the activities of the system. To
perform a specific job or task, the microprocessor has to execute a program stored in
memory. The program consists of a set of instructions. It issues address and control signals
and fetches the instruction and data from memory. The instruction is executed one by one
internal to the processor and based on the result it takes appropriate action.
Buses
The buses are group of lines that carries data, address or control signals.
• The CPU Bus has multiplexed lines, i.e., same line is used to carry different signals.
• The CPU interface is provided to demultiplex the multiplexed lines, to generate chip
select signals and additional control signals.
• The system bus has separate lines for each signal. All the slaves in the system are
connected to the same system bus. At any time instant communication takes place
between the master and one of the slaves. All the slaves have tri-state logic and hence
normally remain in high impedance state. Only when the slave is selected it comes to
the normal logic.
Peripheral devices
• The EPROM memory is used to store permanent programs and data.
• The RAM memory is used to store temporary programs and data.
• The input device is used to enter the program, data and to operate the system.
• The output device is used for examining the results.
Since the speed of I/O devices does not match with the speed of microprocessor, an interface
device is provided between system bus and I/O devices. Generally I/O devices are slow
devices.
Advantages of Microprocessor based system
• Computational/processing speed is high.
• Intelligence has been brought to systems.
• Automation of industrial processes and office administration.

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• Since the devices are programmable, there is flexibility to alter the system by
changing the software alone.
• Less number of components, compact in size and cost less. Also it is more reliable.
• Operation and maintenance are easier.
Disadvantages of Microprocessor based System
• It has limitations on the size of data.
• The applications are limited by the physical address space.
• The analog signals cannot be processed directly and digitizing the analog signals
• Introduces errors.
• The speed of execution is slow and so real time applications are not possible.
• Most of the microprocessors does not support floating point operations.
• General 8-bit microprocessor and its architecture

INTEL 8085 – Features

• The INTEL 8085 is an 8-bit microprocessor.

• It is a 40-pin DIP chip designed using NMOS.
• It operates with a power supply of +5 volts
• It operates on 8-bit data and uses 16-bit address to access the memory.
• With the help of 16-bit address, 8085 can access 216 = 65536 = 64K memory
locations.
• 8085 generates a clock frequency of 5 MHz and is internally divided by 2
• The device can use 28 (256) I/O devices
• 8085 has 5 hardware interrupts and 8 software interrupts
• 8085 has 74 instructions

1.2 Pin Description of 8085

1.2.1 Classification of Signals
The various signals in a microprocessor can be classified as
Power supply and Frequency signals: Signals which aids in supplying power and
generating frequency are associated with this type. Pins like Vcc and ground are classified
under this type.

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Address signals: Signals associated with the lower order address bus and time multiplexed
higher order address bus comes under this type of signals.
Data Signals: Signals associated with data bus comes under this type.
Control and Status Signals: Signals which are associated with timing and control unit such
HOLD, RW’, WR’ etc. comes under this type of signals.
Interrupt Signals: We know that signals like TRAP, RST 5.5 etc. are interrupt signals. Such
signals come under this category.
Serial I/O signals: These signals are used for giving serial input and output data. Signals like
SID, SOD come under this category.
Acknowledgement Signals: Signals like INTA’, HLDA acts as acknowledgement signal for
8085 microprocessor.

Fig1.2 Pin Diagram of 8085

1.2.2 Pin Description
Address Bus: The pins A8-A15 denote the address bus. They are used for the most
significant bit of memory address.

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Address/Data Bus: AD0-AD7 constitutes the Address/Data bus. They are time multiplexed.
These pins are used for least significant bits of address bus in the first machine clock cycle
and used as data bus for second and third clock cycle.
ALE: Address Latch Enable: ALE helps in demultiplexing the lower order address and
data bus. This signal goes high during the first clock cycle and enables the lower order
address bits. The lower order address bus is added to memory or an external latch.
IO/M’: This is a status signal called IO/M’ is used. This distinguishes whether the address is
for memory or IO. When this pin goes high, the address is for an I/O device. While the pin
goes low, the address is assigned for the memory.
S0-S1:S0 and S1 are status signals which provides different status and functions depending
on their status.
Table 1.1 S0-S1:

RD: This is an active low signal. That is, an operation is performed when the signal goes low.
This signal is used to control READ operation of the microprocessor. When this pin goes low
the microprocessor reads the data from memory or I/O device.
WR’: This is also an active low signal which controls the write operations of the
microprocessor. When this pin goes low, the data is written to the memory or I/O device.
READY: READY is used by the microprocessor to check whether a peripheral is ready to
accept or transfer data. A peripheral may be a LCD display or analog to digital converter or
any other. These peripherals are connected to microprocessor using the READY pin. If
READY is high then the periphery is ready for data transfer. If not the microprocessor waits
until READY goes high.
HOLD: This indicates if any other device is requesting the use of address and data bus.
Consider two peripheral devices. One is the LCD and the other Analog to Digital converter.
Suppose if analog to digital converter is using the address and data bus and if LCD requests
the use of address and data bus by giving HOLD signal, then the microprocessor transfers the

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control to the LCD as soon as the current cycle is over. After the LCD process is over, the
control is transferred back to analog and digital converter.
HLDA: HLDA is the acknowledgment signal for HOLD. It indicates whether the HOLD
signal is received or not. After the execution of HOLD request, HLDA goes low.
INTR: INTR is an interrupt request signal. It has the lowest priority among the interrupts.
INTR can be enabled or disabled by using software. Whenever INTR goes high the
microprocessor completes the current instruction which is being executed and then
acknowledges the INTR signal and processes it.
INTA: Whenever the microprocessor receives interrupt signal. It has to be acknowledged.
This acknowledgement is done by INTA’. So whenever the interrupt is received INTA’ goes
high.
RST 5.5, 6.5, 7.5: These are nothing but the restart interrupts. They insert an internal restart
function automatically. All the above mentioned interrupts are maskable interrupts. That is,
they can be enabled or disabled using programs.
TRAP: Among the interrupts of 8085 microprocessor, TRAP is the only non-maskable
interrupt. It cannot be enabled or disabled using a program. It has the highest priority among
the interrupts.
PRIORITY ORDER (From highest to lowest)
TRAP
RST 7.5
RST 6.5
RST 5.5
INTR
RESET IN: This pin resets the program counter to 0 and resets interrupt enable and HLDA
flip-flops. The CPU is held in reset condition until this pin is high. However the flags and
registers won’t get affected except for instruction register.
RESET OUT: This pin indicates that the CPU has been reset by RESET IN’.
X1 X2: These are the terminals which are connected to external oscillator to produce the
necessary and suitable clock operation.
CLK: Sometimes it is necessary for generating clock outputs from microprocessors so that
they can be used for other peripherals or other digital IC’s. This is provided by CLK pin. Its
frequency is always same as the frequency at which the microprocessor operates.

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SID: This pin provides serial input data. The serial data on this pin is loaded into the seventh
bit of the accumulator when RIM instruction is executed.RIM stands for READ
INTERRUPT MASK, which checks whether the interrupt is masked or not.
SOD: This pin provides the serial output data. The serial data on this pin delivers its output to
the seventh bit of the accumulator when SIM instruction is executed.
Vcc and Vss: Vcc is +5v pin and Vss is ground pin.

Table 1.2 Operations performed by 8085

1.3 INTEL 8085 Architecture

The architecture of.8085 is shown in figure given below. The internal architecture of 8085
includes the ALU, timing and control unit, instruction register and decoder, register array,
interrupt control and serial I/O control.

Fig 1.3 8085 architecture

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Operations Performed By 8085

The ALU performs the arithmetic and logical operations. The operations performed
by ALU of 8085 are addition, subtraction, increment, decrement, logical AND, OR, exclusive
-or, compare, complement and left / right shift. The accumulator and temporary register are
used to hold the data during an arithmetic / logical operation. After an operation the result is
stored in the accumulator and the flags are set or reset according to the result of the operation.
Flag register:
There are five flags in 8085, which are sign flag (8), zero flag (Z), auxiliary carry flag
(AC), parity flag (P) and carry flag (CY). The bit positions reserved for these flags in the flag
register are as follows
S Z - AC - P - C

After an ALU operation, if the most significant bit of the result is 1, then sign flag is set. The
zero flag is set, if the ALU operation results in zero and it is reset if the result is non-zero. In
an arithmetic operation, when a carry is generated by the lower nibble, the auxiliary carry
flag is set. After an arithmetic or logical operation, if the result has an even number of 1’s the
parity flag is set, otherwise it is reset.
If an arithmetic operation results in a carry, the carry flag is set otherwise it is reset.
Among the five flags, the AC flag is used internally for BCD arithmetic and other four flags
can be used by the programmer to check the conditions of the result of an operation.
Timing & Control unit:
The timing and control unit synchronizes all the microprocessor operations with the clock
and generates the control signals necessary for communication between the microprocessor
and peripherals.
Instruction Register & Decoder:
When an instruction is fetched from memory it is placed in instruction register. Then
it is decoded and encoded into various machine cycles.
Register Array:
• Apart from Accumulator (A-register), there are six general-purpose programmable
registers B, C, D, E, H and L.
• They can be used as 8-bit registers or paired to store l6-bit data. The allowed pairs are
B-C, D-E and H-L.

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• The temporary registers W and Z are intended for internal use of the processor and it
cannot be used by the programmer.
Stack Pointer (SP):
The stack pointer SP holds the address of the stack top. The stack is a sequence of RAM
memory locations defined by the programmer. The stack is used to save the content of
registers during the execution of a program.
Program Counter (PC):
The program counter (PC) keeps track of program execution. To execute a program
the starting address of the program is loaded in program counter. The PC sends out an
address to fetch a byte of instruction from memory and increment its content automatically.
Hence, when a byte of instruction is fetched, the PC holds the address of the next byte of the
instruction or next instruction.
1.4 Intel 8086
Signal Description of 8086
The Microprocessor 8086 is a 16-bit CPU available in different clock rates and
packaged in a 40 pin CERDIP or plastic package. The 8086 operates in single processor or
multiprocessor configuration to achieve high performance. The pins serve a particular
function in minimum mode (single processor mode) and other function in maximum mode
configuration (multiprocessor mode ).
1.4.1 Classification of Signals
The 8086 signals can be categorized in three groups
• Signals with common functions in minimum as well as maximum mode.
• Signals with special functions for minimum mode
• Signals with special functions for maximum mode.
1.4.2 Pin Description
The following signal descriptions are common for both modes.

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Figure 1.4 Pin Diagram of 8086

AD15-AD0:
These are the time multiplexed memory I/O address and data lines.
• Address remains on the lines during T1 state, while the data is available on the data
bus during T2, T3, T3 and T4.
• These lines are active high and float to a tristate during interrupt acknowledge and
local bus hold acknowledge cycles.
A19/S6, A18/S5, A17/S4, A16/S3:
These are the time multiplexed address and status lines.
• During T1 these are the most significant address lines for memory operations.
• During I/O operations, these lines are low. During memory or I/O operations, status
information is available on those lines for T2, T3, Tw and T4.
• The status of the interrupt enable flag bit is updated at the beginning of each clock
cycle.

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• The S4 and S3 combined together indicate which segment register is presently being
used for memory accesses
• These lines float to tri-state off during the local bus hold acknowledge. The status line
S6 is always low.
• The address bit is separated from the status bit using latches controlled by the ALE
signal.
BHE /S7:
The bus high enable is used to indicate the transfer of data over the higher order (D15-D8)
data bus as shown in table. It goes low for the data transfer over D15-D8 and is used to derive
chip selects of odd address memory bank or peripherals. BHE is low during T1 for read, write
and interrupt acknowledge cycles, whenever a byte is to be transferred on higher byte of data
bus. The status information is available during T2, T3 and T4. The signal is active low and
tristated during hold. It is low during T1 for the first pulse of the interrupt acknowledges
cycle.
RD Read: This signal on low indicates the peripheral that the processor is performing s
memory or I/O read operation. RD is active low and shows the state for T2, T3, and T3 of
any read cycle. The signal remains tristated during the hold acknowledge.

READY:
This is the acknowledgement from the slow device or memory that they have completed the
data transfer. The signal made available by the devices is synchronized by the 8284A clock
generator to provide ready input to the 8086. The signal is active high.
INTR-Interrupt Request:
This is a triggered input. This is sampled during the last clock cycles of each instruction to
determine the availability of the request. If any interrupt request is pending, the processor
enters the interrupt acknowledge cycle. This can be internally masked by resulting the
interrupt enable flag. This signal is active high and internally synchronized.
TEST This input is examined by a WAIT instruction. If the TEST pin goes low, execution
will continue, else the processor remains in an idle state. The input is synchronized internally
during each clock cycle on leading edge of clock.
CLK- Clock Input:

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The clock input provides the basic timing for processor operation and bus control activity. Its
an asymmetric square wave with 33% duty cycle.
MN/ MX:
The logic level at this pin decides whether the processor is to operate in either minimum or
maximum mode. The following pin functions are for the minimum mode operation of 8086.
M/ IO – Memory/IO:
This is a status line logically equivalent to S2 in maximum mode. When it is low, it indicates
the CPU is having an I/O operation, and when it is high, it indicates that the CPU is having a
memory operation. This line becomes active high in the previous T4 and remains active till
final T4 of the current cycle. It is tristated during local bus hold acknowledge.
INTA Interrupt Acknowledge:
This signal is used as a read strobe for interrupt acknowledge cycles. i.e. when it goes low,
the processor has accepted the interrupt.
ALE – Address Latch Enable:
This output signal indicates the availability of the valid address on the address/data lines, and
is connected to latch enable input of latches. This signal is active high and is never tristated.
DT/ R – Data Transmit/Receive:
This output is used to decide the direction of data flow through the Trans receivers
(bidirectional buffers). When the processor sends out data, this signal is high and when the
processor is receiving data, this signal is low.
DEN – Data Enable:
This signal indicates the availability of valid data over the address/data lines. It is used to
enable the transreceivers (bidirectional buffers) to separate the data from the multiplexed
address/data signal. It is active from the middle of T2 until the middle of T4. This is tristated
during hold acknowledge cycle.
HOLD, HLDA- Acknowledge:
When the HOLD line goes high, it indicates to the processor that another master is requesting
the bus access.
• The processor, after receiving the HOLD request, issues the hold acknowledge signal
on HLDA pin, in the middle of the next clock cycle after completing the current bus
cycle.

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• At the same time, the processor floats the local bus and control lines. When the
processor detects the HOLD line low, it lowers the HLDA signal. HOLD is an
asynchronous input, and is should be externally synchronized.
• If the DMA request is made while the CPU is performing a memory or I/O cycle, it
will release the local bus during T4 provided:
▪ 1. The request occurs on or before T2 state of the current cycle.
▪ 2. The current cycle is not operating over the lower byte of a word.
▪ 3. The current cycle is not the first acknowledge of an interrupt
acknowledge sequence.
▪ 4. A Lock instruction is not being executed.
The following pin function is applicable for maximum mode operation of 8086.
S2, S 1, S0 – Status Lines:
These are the status lines which reflect the type of operation, being carried out by the
processor. These become activity during T4 of the previous cycle and active during T1 and
T2 of the current bus cycles.

Table 1.3 Operations performed by 8086

LOCK: This output pin indicates that other system bus master will be prevented from
gaining the system bus, while the LOCK signal is low.
• The LOCK signal is activated by the LOCK prefix instruction and remains active
until the completion of the next instruction. When the CPU is executing a critical

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instruction which requires the system bus, the LOCK prefix instruction ensures that
other processors connected in the system will not gain the control of the bus.
• The 8086, while executing the prefixed instruction, asserts the bus lock signal output,
which may be connected to an external bus controller.
QS1, QS0 – Queue Status:
These lines give information about the status of the code
Pre fetch queue. These are active during the CLK cycle after while the queue operation is
performed.
• This modification in a simple fetch and execute architecture of a conventional
microprocessor offers an added advantage of pipelined processing of the instructions.
• The 8086 architecture has 6-byte instruction pre fetch queue. Thus even the largest (6
- bytes) instruction can be pre fetched from the memory and stored in the pre fetch.
This results in a faster execution of the instructions.
• In 8085 an instruction is fetched, decoded and executed and only after the execution
of this instruction, the next one is fetched.
• By prefetching the instruction, there is a considerable speeding up in instruction
execution in 8086. This is known as instruction pipelining.

Table 1.4 QS1, QSo indication

RQ / GT0 ,/ GT1– Request/Grant:

These pins are used by the other local bus master RQin maximum mode, to force the
processor to release the local bus at the end of the processor current bus cycle.
• Each of the pin is bidirectional with RQ/GT0 having higher priority than RQ/GT1.
• RQ/GT pins have internal pull-up resistors and may be left unconnected.
Request/Grant sequence is as follows:

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• A pulse of one clock wide from another bus master requests the bus access to 8086.
2.During T4(current) or T1(next) clock cycle, a pulse one clock wide from 8086 to the
requesting master, indicates that the 8086 has allowed the local bus to float and that it
will enter the „hold acknowledge‟ state at next cycle. The CPU bus interface unit is
likely to be disconnected from the local bus of the system.
• A one clock wide pulse from another master indicates to the 8086 that the hold
request is about to end and the 8086 may regain control of the local bus at the next
clock cycle. Thus each master to master exchange of the local bus is a sequence of 3
pulses. There must be at least one dead clock cycle after each bus exchange.
• The request and grant pulses are active low.
• For the bus request those are received while 8086 is performing memory or I/O cycle,
the granting of the bus is governed by the rules as in case of HOLD and HLDA in
minimum mode.
General Bus Operation:
• The 8086 has a combined address and data bus commonly referred as a time
multiplexed address and data bus.
• The main reason behind multiplexing address and data over the same pins is the
maximum utilization of processor pins and it facilitates the use of 40 pin standard DIP
package.
• The bus can be demultiplexed using a few latches and transreceivers, when ever
required.
• Basically, all the processor bus cycles consist of at least four clock cycles. These are
referred to as T1, T2, T3, and T4. The address is transmitted by the processor during
T1. It is present on the bus only for one cycle.
• The negative edge of this ALE pulse is used to separate the address and the data or
status information. In maximum mode, the status lines S0, S1 and S2 are used to
indicate the type of operation.
• Status bits S3 to S7 are multiplexed with higher order address bits and the BHE
signal. Address is valid during T1 while status bits S3 to S7 are valid during T2
through T4.
1.4.3 Minimum Mode Signals

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In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum mode by
strapping its MN/MX pin to logic 1. In this mode, all the control signals are given out by the
microprocessor chip itself. There is a single microprocessor in the minimum mode system.
The remaining components in the system are latches, transreceivers, clock generator, memory
and I/O devices. Some type of chip selection logic may be required for selecting memory or
I/O devices, depending upon the address map of the system.
• Trans receivers are the bidirectional buffers and sometimes they are called as data
amplifiers. They are required to separate the valid data from the time multiplexed
address/data signals. They are controlled by two signals namely, DEN and DT/R.
• The DEN signal indicates the direction of data, i.e. from or to the processor. The
system contains memory for the monitor and users program storage.
• The read cycle begins in T1 with the assertion of address latch enable (ALE) signal
and also M / IO signal. During the negative going edge of this signal, the valid
address is latched on the local bus.
• The BHE and A0 signals address low, high or both bytes. From T1 to T4, the M/IO
Signal indicates a memory or I/O operation.
• At T2, the address is removed from the local bus and is sent to the output. The bus is
then tristated. The read (RD) control signal is also activated in T2.
• The read (RD) signal causes the address device to enable its data bus drivers. After
RD goes low, the valid data is available on the data bus.
• The addressed device will drive the READY line high. When the processor returns
the read signal to high level, the addressed device will again tristate its bus drivers.
1.4.4 Maximum Mode Signals
In the maximum mode, the 8086 is operated by strapping the MN/MX pin to ground. In this
mode, the processor derives the status signal S2, S1, S0. Another chip called bus controller
derives the control signal using this status information. In the maximum mode, there may be
more than one microprocessor in the system configuration. The components in the system are
same as in the minimum mode system.
• S0, S1, S2 – These are status signals and they are used by the 8288 bus controller to
generate bus timing and control signals
• RQ/GT0, RQ/GT1 – (Bus Request/ Bus Grant) These request are used by the other
local bus masters to force the processor to release the local bus at the end of the

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processor’s current bus cycle. These pins are bidirectional. The request on GT0 will
have highest priority
• LOCK – It is an output signal, activated by the LOCK prefix instruction and remains
active until the completion of the instruction prefixed by LOCK.
• QS1, QS0 - (Queue Status) The processor provides the status of queue on these lines.
The queue status can be used by external device to track the internal status of the
queue in 8086.
1.5 Intel 8086 Architecture
The 8086 processor is divided into two independent functional units. They are,
• The bus interface unit (BIU).
• The Execution Unit (EU).
• These two units are linked using an internal data bus.

Fig 1.5 8086 Architecture

Bus Interface Unit:

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• The Bus interface unit (BIU) fetches instruction, reads data from memory and
peripherals and writes data into memory and peripherals.
• It contains segment registers, instruction pointer, instruction queue and address
generation / bus control circuit to provide functions such as fetching and queuing of
instruction and bus control.
• The BIU’s instruction queue is a First in First out (FIFO) group of registers in which
up to six bytes of instruction code are projected from memory ahead of time. This is
done to speed up program execution by overlapping instruction fetch with execution.
This mechanism is referred to as pipe lining.
• If queue is full, the BIU does not perform any bus cycle i.e., BIU does not prefetch
any instructions. Therefore, BIU may prefetch the instructions from memory until
queue is full.
• While fetching the instruction from memory, of the Execution Unit (EU) interrupts
the BIU for memory access, the BIU first complete fetching and then services the EU.
• If a subroutine call or Jump instructions are encountered, the BIU will reset the queue
and begin refilling after passing the new instruction to the EU
• BIU contains an adder, which is used to produce the 20-bit address. The bus control
logic of the BIU generates all the bus control signals such as read and write signals for
memory and I/O.
It has four, 16 bit registers. These are
Code segment (CS) registers,
Data segment (DS) registers
Stack segment (SS) registers
Extra segment (ES) registers
• 8086 processor consists of I Mega Byte memory and is divided into segments of up to
64 Kbytes each.
This microprocessor is capable of addressing four segments directly at a time.
Code segment (CS)
All program instructions must be located in main memory pointed to by the 16 bit CS
register with a 16 bit offset in the segment contained in the 16 bit Instruction pointer. The
BIU computes the 20 bit physical address. Therefore the CS contains the start of the current

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code segment and IP contains the offset from this address to the next instruction byte to be
fetched.
Eg : If CS = 456A16 and IP = 162016 , then the 20bit physical
address is calculated by adding the IP with one position
shifted value of CS.
20 bit address = 456A016 + 162016 = 46CC016
Stack segment (SS)
The SS register points to the current stack. The 20-bit physical stack address is
calculated from SS & SPP for stack instructions. The programmer can use the BP registers
instead of SP for accessing the stack using the based addressing mode. In this case, the 20-bit
physical stack address is calculated from SS & BP.
Data segment (DS)
The DS register points to current data segment, i.e. operands for most instructions are
fetched from this segment. The 16 bit contents of Source Index (SI) or Destination Index (DI)
are used as offset for calculating the 20 bit physical address.
Extra segment (ES)
This register points to the extra segment, which excess data, is stored. The DI is used
as offset for calculating the 20-bit physical address. String instruction always use instruction
always uses ES and DI to calculate the 20-bit address for the destination. The segment can be
continuous, partially overlapped, fully overlapped, dis-joint or continuous
Execution Unit:
• The EU decodes and executes instructions.
• A decoder in the EU translates the instructions.
• It has a 16 bit ALU to perform arithmetic and logic operations.
• It has eight 16 bit registers (AX, BX, CX, DX, SP, BP, SI & DI).
• These 16 bit registers are used to store 16 bit/S8 bit data.
• Each 16 bit register (AX, BX, CX, DX) is combination of two 8 bit register i.e., AH
(Higher byte) and AL (lower byte) combines together to store a 16 bit data in (AX).
• AX acts as the 16 bit accumulator in which the Arithmetic & Logical operation are
carried out.
• AL is the 8-bit accumulator.
• BX is the only general-purpose register, which is used for addressing 8086 memory.

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• CX register is the counter register in which the contents always be decremented by 1.

• DX is the data register is used to hold excess 16 bit result while performing
multiplication, division, etc.
• SP & BP are point registers, which are used to access data in stack segment. These are
used as offset for SS.
• The EU also contains a 16-bit flag register which holds the status flags typically after
an ALU operation.
The flag register of 8086 micro processor is,
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
X X X X O D I T S Z X AC X P X CY

O – Overflow flag
D – Direction flag
I – Interrupt flag
S – Sign flag
Z – Zero flag
AC – Auxiliary carry flag
P – Parity flag
• The flags are divided into two classifications. They are,(A) Condition code Flags
• These flags reflect the result of Operations Performed by ALU. They are,
Over flow flag (O): This flag is set, if an overflow occurs during the arithmetic operation of
two signed numbers.
Sign flag (S): This flag is set, if an MSB of the accumulator is set after any computation.
Zero flag (Z): This flag is set, if the result of any computation is zero.
Auxiliary carry flag (AC): This flag is set, if there is a carry from the third bit, during
addition or borrow.
Parity flag (P): The flag is set, if the lower byte result contains even number of 1’s.
Carry flag (CY): This flag is set, if any computation result contains a carry.
(B) Machine control flags
Direction Flag: This flag is set, if the string is processed from higher address towards lower
address. Otherwise, the flag is reset. This is used only in string manipulation instructions.
Interrupt flag: This flag is set, only when maskable interrupts are recognized.

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Trap flag: When a trap interrupt is received by the processor, this flag is set, which indicates,
the processor to execute the current instruction and to transfer the control to trap service
routine. In Other words, When 8086 enters in Program, data and stack memories occupy the
same memory space. The total addressable memory size is 1MB KB. As the most of the
processor instructions use 16-bit pointers the processor can effectively address only 64 KB of
memory. To access memory outside of 64 KB the CPU uses special segment registers to
specify where the code, stack and data 64 KB segments are positioned within 1 MB of
memory (see the "Registers" section below).
16-bit pointers and data are stored as:
address: low-order byte
address+1: high-order byte
32-bit addresses are stored in "segment: offset" format as:
address: low-order byte of segment
address+1: high-order byte of segment
address+2: low-order byte of offset
address+3: high-order byte of offset
Physical memory address pointed by segment: offset pair is calculated as:
Address = (<segment> * 16) + <offset>
Program memory - program can be located anywhere in memory. Jump and call instructions
can be used for short jumps within currently selected 64 KB code segment, as well as for far
jumps anywhere within 1 MB of memory. All conditional jump instructions can be used to
jump within approximately +127 - -127 bytes from current instruction.
Data memory - the 8086 processor can access data in any one out of 4 available segments,
which limits the size of accessible memory to 256 KB (if all four segments point to different
64 KB blocks). Accessing data from the Data, Code, Stack or Extra segments can be usually
done by prefixing instructions with the DS:, CS:, SS: or ES: (some registers and instructions
by default may use the ES or SS segments instead of DS segment).
Word data can be located at odd or even byte boundaries. The processor uses two
memory accesses to read 16-bit word located at odd byte boundaries. Reading word data
from even byte boundaries requires only one memory access. Stack memory can be placed
anywhere in memory. The stack can be located at odd memory addresses, but it is not
recommended for performance reasons (see "Data Memory" above).

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Reserved locations:
• 0000h - 03FFh are reserved for interrupt vectors. Each interrupt vector is a 32-bit
pointer in format segment: offset.
• FFFF0h - FFFFFh - after RESET the processor always starts program execution at the
FFFF0h address.
Interrupts
The processor has the following interrupts:
INTR is a maskable hardware interrupt. The interrupt can be enabled/disabled using
STI/CLI instructions or using more complicated method of updating the FLAGS register with
the help of the POPF instruction. When an interrupt occurs, the processor stores FLAGS
register into stack, disables further interrupts, fetches from the bus one byte representing
interrupt type, and jumps to interrupt processing routine address of which is stored in location
4 * <interrupt type>. Interrupt processing routine should return with the IRET instruction.
NMI is a non-maskable interrupt. Interrupt is processed in the same way as the INTR
interrupt. Interrupt type of the NMI is 2, i.e. the address of the NMI processing routine is
stored in location 0008h. This interrupt has higher priority than the maskable interrupt.
Software interrupts can be caused by:
• INT instruction - breakpoint interrupt. This is a type 3 interrupt.
• INT <interrupt number> instruction - any one interrupt from available 256 interrupts.
• INTO instruction - interrupt on overflow
• Single-step interrupt - generated if the TF flag is set. This is a type 1 interrupt. When
the CPU processes this interrupt it clears TF flag before calling the interrupt
processing routine.
• Processor exceptions: divide error (type 0), unused opcode (type 6) and escape
opcode (type 7).
Software interrupt processing is the same as for the hardware interrupts. All general registers
of the 8086 microprocessor can be used for arithmetic and logic operations.
General Purpose Registers:
Accumulator register consists of 2 8-bit registers AL and AH, which can be combined
together and used as a 16-bit register AX. AL in this case contains the low-order byte of the
word, and AH contains the high-order byte. Accumulator can be used for I/O operations and
string manipulation. Base register consists of 2 8-bit registers BL and BH, which can be

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combined together and used as a 16-bit register BX. BL in this case contains the low-order
byte of the word, and BH contains the high-order byte. BX register usually contains a data
pointer used for based, based indexed or register indirect addressing. Count register consists
of 2 8-bit registers CL and CH, which can be combined together and used as a 16-bit register
CX. When combined, CL register contains the low-order byte of the word, and CH contains
the high-order byte. Count register can be used as a counter in string manipulation and
shift/rotate instructions.
Data register consists of 2 8-bit registers DL and DH, which can be combined
together and used as a 16-bit register DX. When combined, DL register contains the low-
order byte of the word, and DH contains the high-order byte. Data register can be used as a
port number in I/O operations. In integer 32-bit multiply and divide instruction the DX
register contains high-order word of the initial or resulting number.
The following registers are both general and index registers:
Stack Pointer (SP) is a 16-bit register pointing to program stack.
Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP register is usually
used for based, based indexed or register indirect addressing.
Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register
indirect addressing, as well as a source data addresses in string manipulation instructions.
Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and
register indirect addressing, as well as a destination data addresses in string manipulation
instructions.
Other registers:
Instruction Pointer (IP) is a 16-bit register.

1.6 Memory Interfacing

The memory is made up of semiconductor material used to store the programs and
data. Three types of memory is,
• Process memory
• Primary or main memory
• Secondary memory
1.6.1 Typical EPROM and Static RAM
A typical semiconductor memory IC will have n address pins, m data pins (or

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output pins).
• Having two power supply pins (one for connecting required supply voltage (V and the
other for connecting ground).
• The control signals needed for static RAM are chip select (chip enable), read control
(output enable) and write control (write enable).
• The control signals needed for read operation in EPROM are chip select (chip enable)
and read control (output enable).
1.6.2 Decoder
It is used to select the memory chip of processor during the execution of a program. No of
IC's used for decoder is,
• 2-4 decoder (74LS139)
• 3-8 decoder (74LS138)

1.6 Static RAM and EPROM

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a) b)
1.7 Block diagram of a) 2-4 &b) 3-8 decoder

1.8 Memory Interfacing

1.7 Timing Diagram

• The sequence of operations that a processor has to carry out while executing the
instruction is called Instruction Cycle.
• Each instruction cycle of a processor in turn consists of a number of machine cycles.
The machine cycles are the basic operations performed by the processor.
• To execute an instruction, the processor executes one or more machine cycles in a
particular order. The machine cycles of a processor are also called Processor Cycles.
• The manufacturer of microprocessors defines the timings and status of various signals
during the processor cycles.
• In general, the instruction cycle of an instruction can be divided into two as Fetch and
Execute. The fetch cycle is executed to fetch the opcode from memory and the
execute cycle is executed to decode the instruction and to perform the work instructed
by the instruction.
1.7.1 Machine Cycles of 8085

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The 8085 microprocessor has 7 (seven ) basic machine cycles. They are
1. Opcode fetch cycle (4 T or 6 T )
2. Memory read cycle (3 T)
3. Memory write cycle (3 T)
4. I/O read cycle (3 T)
5. I/O write cycle (3 T)
6. Interrupt acknowledge cycle (6 Tor 12 T)
7. Bus idle cycle. ( 2 T or 3 T )
Each instruction of the 8085 processor consists of one to five machine cycles. When
the 8085 processor executes an instruction, it will execute some of the machine cycles in a
specific order. The processor takes a definite time to execute the machine cycles.

Figure 1.9 T State

The time taken by the processor to execute a machine cycle is expressed in T -states. One T -
state is equal to the time period of the internal clock signal of the processor. The T -state
starts at the falling edge of a clock.

Opcode Fetch Machine Cycle

Each instruction of the processor has one byte opcode. The opcodes are stored in
memory. The opcode fetch machine cycle is executed by the processor to fetch the opcode
from memory. Hence, every instruction starts with opcode fetch machine cycle.

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Figure 1.10 Opcode Fetch Machine Cycle

The time taken by the processor to execute the opcode fetch cycle is either 4T or 6T. In
this time, the first 3T states are used for fetching the opcode from memory and the remaining
T-states are used for internal operations by the processor.
• At the falling edge of first T-state ( ), the microprocessor output the low byte
address on - lines and high byte address on lines. ALE is asserted high
to enable the external address latch. The other control signals are asserted as follows.
(IO/ is asserted low to indicate memory access)
• At the middle of , the ALE is asserted low and this enables the external address
latch to take low byte of the address and keep on the address and keep on its output
lines.
• In the second T-states ( ), the memory is requested for read by assorting read line
low. When read is asserted low, the memory is enabled for placing the opcode on the
data bus. The time allowed for memory to output the opcode is the time during which
read remains low.
• In the third T-state ( ), the read signal is asserted high. On the rising edge of read
signal the opcode is latched into microprocessor. Other control signals remains in the
same state until the next machine cycle.
• The fourth T-state( ) is used by the processor for internal operations to decode the
instruction and encode into various machine cycles, and also for completing the task
specified by 1 byte instruction. During this state ( ) the address and data bus will be
in high impedance state.

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Memory Read Machine Cycle of 8085

The memory read machine cycle is executed by the processor to read a data byte from
memory. The processor takes 3T states to execute this cycle. The timings of various
signals during memory read cycle are shown
• At the falling edge of the microprocessor output the low byte address on
lines and high byte address on - lines. ALE is asserted high to enable the
external address latch. The other control signals are asserted as follows.
IO/ =0, .(IO/ is asserted low to indicate memory access)

• At the middle of , the ALE is asserted low and this enables the external address
latch to take low byte of address and keep on its output lines.

Figure 1.11 Memory Read Cycle

• In the second T-state ( ) the memory is requested for read by asserting read line low.
When read is asserted low, the memory is enabled for placing the data on the data bus.
The time allowed for memory to output the data is the time during which read remains
low.
• At the end of , the read signal is asserted high. On the rising edge of read signal the
data is latched into microprocessor. Other control signals remains in the same state
until the next machine cycle.

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Memory Write Machine Cycle of 8085

The memory write machine cycle is executed by the processor to write a data byte in a
memory location. The processor takes 3T-states to execute this machine cycle. The
timings of various signals during memory write cycle are shown.
• At the falling edge of , the microprocessor output the low byte address on -
lines and high byte address on lines. ALE is asserted high to enable the
external address latch. The other control signals are asserted as follows.
• At the middle of , the ALE is asserted low and this enables the external address
latch for latching the low byte address into its output lines.
• In the falling edge of , the processor output data on lines and then request memory
for write operation by asserting the write control signal to low.
• At the end of , the processor asserts high. This enables the memory to latch the
data into it. Other control signals remains in the same state until the next machine
cycle.

Figure 1.12 Memory Write Cycle

I/O Read Cycle of 8085
The I/O read cycle is executed by the processor to read a data byte from I/O port or
from the peripheral which is I/O mapped in the system. The processor takes 3T states to
execute this machine cycle. The timings of various signals during this machine cycle are
shown.

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Figure 1.13 I/O Read Cycle

• At the falling edge of ,the microprocessor output the 8-bit port address on both the
low order address lines ( - ) and high order address lines( - ).ALE is
asserted HIGH to enable the external address latch. The other control signal are
asserted as follows.
• IO/ =1, =0 and =1.(IO/ ) is asserted high to indicate I/O access

• At the middle of ,the ALE is asserted LOW and this enables the external address
latch to take the port address and keep on its output lines.
• In the second T-state ( ) the I/O device is requested for read by asserting read line
low. When read is asserted low, the I/O port is enabled for placing the data on the data
bus. The time allowed for I/O port to output the data is the time during which read
remains LOW.
• At the end of , the read signal is asserted HIGH. On the rising edge of read signal
the data is latched into microprocessor. Other control signals remains in the same
state until the next machine cycle.
I/O Write cycle of 8085
The I/O write machine cycle is executed by the processor to write a data byte in an
I/O port or to a peripheral which is I/O mapped in the system. The processor takes 3T-states

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to execute this machine cycle. The timings of the various signals of I/O write cycle are

shown.
Figure 1.14 I/O Write Cycle
• At the falling edge of , microprocessor output the 8-bit port address on both the
low order address lines ( - ) and high order address lines ( to ).ALE is
asserted HIGH to enables the external address latch. The other control signals are
asserted as follows.
• At the middle of , the ALE is asserted LOW and this enables the external address
latch for latching the port address into its output lines.
• In the falling edge of , the processor output data on AD0-AD7 lines and then request
I/O port for write operation by asserting the write control signal to low.
• At the end of , processor asserts high. This enables the I/O port to latch the data
into it. The I/O port should prepare itself to accept the data within the time duration
in which write control signal remains in the same state until the next machine cycle.
Interrupt Acknowledge Machine Cycle of 8085
The interrupt acknowledge machine cycle is executed by the processor to service an
interrupt when an interrupt request is made through INTR pin of the processor.
The 8085 processor checks for an interrupt at the second T-state of the last machine
cycle of every instruction. If there is a valid interrupt request and if INTR is enabled then the
processor completes the current instruction execution and then executes an interrupt

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acknowledge machine cycle. The interrupt acknowledge machine cycle is executed to get
either a RST n instruction from the interrupting device or to get a CALL instruction with
CALL address from the interrupting device. It also stores the content program counter
(return address) in stack.
Bus Idle Machine Cycle
The bus idle machine cycle is executed, when extra time or more time is needed for
an internal operation of the processor. During this cycle the status signals and are
asserted low. The data, address and control pins are driven to high impedance state. The
READY signal will not be sampled by the processor during this cycle.

1.8 I/o ports and data transfer concepts

1.9 8085 Interrupts
1.9.1 Need for Interrupts
Interrupt is a signal send by an external device to the processor, to the processor to
perform a particular task or work. Mainly in the microprocessor based system the interrupts
are used for data transfer between the peripheral and the microprocessor.
When a peripheral is ready for data transfer, it interrupts the processor by sending an
appropriate signal to the interrupt pin of the processor. If the processor accepts the interrupt
then the processor suspends its current activity and executes an interrupt service subroutine to
complete the data transfer between the peripheral and processor. After executing the interrupt
service routine the processor resumes its current activity. This type of data transfer scheme is
called interrupt driven data transfer scheme.
1.9.2 Types of Interrupts
The interrupts are classified into software interrupts and hardware interrupts.
• The software interrupts are program instructions. These instructions are inserted at
desired locations in a program. While running a program, lf a software interrupt instruction is
encountered, then the processor executes an interrupt service routine (ISR).
• The hardware interrupts are initiated by an external device by placing an appropriate
signal at the interrupt pin of the processor. If the interrupt is accepted, then the processor
executes an interrupt service routine (ISR).

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1.9.3 Software Interrupts Of 8085

The software interrupts are program instructions. When the instruction is executed,
the processor executes an interrupt service routine stored in the vector address of the software
interrupt instruction. The software interrupt instructions are included at the appropriate (or
required) place in the main program. When the processor encounters the software instruction,
it pushes the content of PC (Program Counter) to stack. The software interrupts of 8085 are
RST 0, RST 1, RST 2, RST 3, RST 4, RST 5, RST 6 and RST 7. The vector addresses of
software interrupts are given in table below.

Table 1.5 Interrupts & Vector Address

Then loads the Vector address in PC and starts executing the Interrupt Service
Routine (ISR) stored in this vector address. At the end of ISR, a return instruction - RET will
be placed. When the RET instruction is executed, the processor POP the content of stack to
PC. Hence the processor control returns to the main program after servicing the interrupt.
Execution of ISR is referred to as servicing of interrupt.
All software interrupts of 8085 are vectored interrupts. The software interrupts cannot be
masked and they cannot be disabled. The software interrupts are RST0, RST1etc to RST7 (8
Nos).
1.9.4 Hardware Interrupts Of 8085
An external device, initiates the hardware interrupts of 8O85 by placing an
appropriate signal at the interrupt pin of the processor. The processor keeps on checking the
interrupt pins at the second T -state of last machine cycle of every instruction. If the

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processor finds a valid interrupt signal and if the interrupt is unmasked and enabled, then the
processor accepts the interrupt. The acceptance of the interrupt is acknowledged by sending
an INTA signal to the interrupted device.
The processor saves the content of PC (program Counter) in stack and then loads the
vector address of the interrupt in PC. (If the interrupt is non-vectored, then the interrupting
device has to supply the address of ISR when it receives INTA signal). It starts executing ISR
in this address. At the end of ISR, a return instruction, RET will be placed. When the
processor executes the RET instruction, it POP the content of top of stack to PC. Thus the
processor control returns to main program after servicing interrupt. The hardware interrupts
of 8085 are TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR.
Further the interrupts may be classified into vectored / non-vectored and maskable /
non-maskable interrupts.
1.9.5 Vectored & Non Vectored Interrupts
• In vectored interrupts, the processor automatically branches to the specific address in
response to an interrupt.
• But in non-vectored interrupts the interrupted device should give the address of the
interrupt service routine (ISR). In vectored interrupts, the manufacturer fixes the
address of the ISR to which the program control is to be transferred. The vector
addresses of hardware interrupts are given in table above in previous page.
• The TRAP, RST 7.5, RST 6.5 and RST 5.5 are vectored interrupts.
• The INTR is a non-vectored interrupt. Hence when a device interrupts through INTR,
it has to supply the address of ISR after receiving interrupt acknowledge signal.
1.9.6 Maskable & Non-maskable inetrrupts:
The hardware vectored interrupts are classified into maskable and non-maskable interrupts.
• TRAP is non-maskable interrupt
• RST 7.5, RST 6.5 and RST 5.5 are maskable interrupt.
Masking is preventing the interrupt from disturbing the main program. When an interrupt
is masked the processor will not accept the interrupt signal. The interrupts can be masked by
moving an appropriate data (or code) to accumulator and then executing SIM instruction.
(SIM - Set Interrupt Mask). The status of maskable interrupts can be read into accumulator by
executing RIM instruction (RIM - Read Interrupt Mask).

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All the hardware interrupts, except TRAP are disabled, when the processor is resetted. They
can also be disabled by executing Dl instruction. (Dl-Disable Interrupt).
• When an interrupt is disabled, it will not be accepted by the processor. (i.e., INTR,
RST 5.5, RST 6.5 and RST 7.5 are disabled by DI instruction and upon hardware
reset).
• To enable (to allow) the disabled interrupt, the processor has to execute El instruction
(El-Enable Interrupt). The type of signal that has to be placed on the interrupt pin of
hardware interrupts of 8085 are defined by INTEL. The TRAP interrupt is edge and
level sensitive. Hence, to initiate TRAP, the interrupt signal has to make a low to high
transition and then it has to remain high until the interrupt is recognized.
• The RST 7.5 interrupt is edge sensitive (positive edge). To initiate the RST 7.5, the
interrupt signal has to make a low to high transition an it need not remain high until it
is recognized.
• The RST 6.5, RST 5.5 and INTR are level sensitive interrupts. Hence for these
interrupts the interrupting signal should remain high, until it is recognized.
2.0 8086 Interrupts
Interrupts provide a mechanism of transferring control from a foreground process (the
current executing program) to an Interrupt Service Routine. When such a transfer is initiated
by the hardware in response to special internal or external conditions, a hardware interrupt is
said to have occurred. External hardware interrupts are generated by peripheral devices and
are the main mechanism used by these devices to get the attention of the processor.
Certain external hardware interrupts are maskable in that they may be disabled by
clearing the Interrupt enable flag (IF) in the flags register. External hardware interrupts that
cannot be disabled by clearing IF are called non-maskable interrupts. Typically, non-
maskable interrupts are hardware events that must be responded to immediately by the CPU.
An example of such an event is the occurrence of a memory or I/O parity error.
Internal hardware interrupts are hardware interrupts that are generated internally to
the processor, generally on the occurrence of an error condition. A software interrupt occurs
when an INT instruction is executed. With a software interrupt, the type of the interrupt is
specified in the INT instruction. With hardware interrupts, the type of the interrupt is supplied
by the interrupting hardware. In both cases, when an interrupt occurs, the addresses specified
in the related interrupt vector are used to set the CS and IP registers with the starting

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segment: offset address of the associated interrupt service routine. It is this routine which
performs whatever functions necessary is servicing the interrupt. The same sequence of
events as was explained for the mechanism of the INT instruction happens in the case of
hardware interrupts.
There are 256 possible interrupt types available on the IBM PC with certain of these reserved
for various system purposes, and certain available for user-defined interrupt service routine.
External Interrupts
The external interrupt facility is used in the IBM PC to alert the processor that a peripheral
device requires the CPU’s attention. The 8086/8088 microprocessor has two control lines that
can signal interrupts. The lines are designated as INTR (Interrupt Request) and NMI (Non-
maskable Interrupt). Maskable interrupts use the INTR signal line, and non-maskable
interrupts use the NMI signal line.
Maskable Interrupts (INT 08H to INT 0FH)
All I/O devices are connected indirectly to the INTR control line, through the 8259A
Interrupt Controller chip. The 8259A has eight interrupt lines leading into it, labeled IR0 to
IR7. Each line is connected to the interrupt request pins of a particular I/O device. The
following table shows the interrupts controlled by the 8259A:
Interrupt Device
IRQ0 08H Timer chip
IRQ1 09H Keyboard
IRQ2 0AH Reserved
IRQ3 0BH communications
IRQ4 0CH Serial interface (communications)
IRQ5 0DH Disk
IRQ6 0EH Diskette
IRQ7 0FH Printer
When an I/O device generates an interrupt, it asserts its IRi input to the 8259A. The
8259A in turn asserts the control line INTR on behalf of the I/O device. This arrangement
allows the 8259A to enforce priorities if several I/O devices generate interrupts at the same
time. Device 0, the timer, is given the highest priority. Device 7, the printer, if one is present,
is given the lowest priority. The numbers 0, 1, 2, 3, 4, 5, 6, and 7 are called the interrupt
levels of the I/O devices.

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After the 8259A asserts the INTR line and the CPU notices this assertion, the CPU, if
the Interrupt enable flag is set, asserts the interrupt acknowledge line (INTA) in the control
bus. This signal informs the 8259A that the CPU is willing to accept the interrupt. After
receiving the signal, the 8259A will send to the CPU the interrupt level of whichever device
has requested the interrupt (or, if there were several such devices, whichever device the
8259A decided should be given priority). The CPU determines the location of the Interrupt
Service Routine of the hardware interrupt it is servicing from the interrupt level number.
When an I/O device interrupt arrives while another is being serviced, the 8259A holds
the interrupt until completion of the current interrupt. The 8086/8088 signals the 8259A that
it has finished servicing an interrupt by placing an end of interrupt (EOI) character (20H) in
the 8259A’s interrupt command register (located at Port 20H). After receiving the EOI signal,
the 8259A can request the servicing of another interrupt, if any is pending. The 8259A is
designed such that once it sends an interrupt request to the CPU, by asserting the INTR line
in the control bus, it will not send an interrupt of lower or equal priority until it receives the
EOI code.
Disabling maskable interrupts
Maskable interrupts can be disabled by clearing the Interrupt Enable Flag. This can be
done by the instruction CLI (Clear Interrupt enable flag). To enable maskable interrupts, the
instruction STI (Set Interrupt enable flag) can be used. It is also possible to disable interrupts
associated with individual I/O devices by accessing the interrupt mask register in the 8259A.
This register is accessed through port 21H. The interrupt mask register allows enabling or
disabling of interrupts in each of the eight lines labeled IRQ0 to IRQ7. A bit value 0 indicates
that an interrupt line is enabled, whereas a bit value 1 indicates the line is disabled.

Question Bank
PART-A
1. What is a microprocessor?
2. What is tristate logic? Why is it needed in microprocessor system? ( May /June 2009)
3. How the address and data lines are demultiplexed in 8085?
4. List the use of ALE signal in 8085. (Apr/May 2010) ( May /June 2013,2014) Nov
/Dec 2013
5. Define interrupt (May/June 2006, 2007)
6. How the READY signal is used in microprocessor system? ( May /June 2013)

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7. Mention the difference between auxiliary carry flag and carry flag in 8085? Nov /Dec
2013
8. What is meant by Non Maskable interrupt? Nov /Dec 2013
9. Mention the register pairs available in 8085 microprocessor. Nov/ Dec 2013
10. Mention the names of various registers in 8085 with its size. (May/June 2014)
11. Show the bit positions of various flags in flag register of 8085 and explain. (May/June
2012)
12. Mention the hardware interrupts of 8085. (Nov/Dec 2007) (Apr/May 2010)
13. List the interrupt signals of 8085.(NOV/DEC 2013)
14. What are the control signals of 8085? (Nov/Dec 2007)
15. Name the vectored and non vectored interrupt of 8085 system (April/May 2005)
16. If a 5 MHz crystal is connected with 8085, what is the value of system clock
frequency and one T state?(April/May 2007)
17. What is stack? and what is the function of stack pointer? (April/May 2007, 2004)
18. What are software and hardware interrupts in 8086? ( May /June 2009)
19. Compare memory mapped I/O and peripheral mapped I/O (May/June 2006, Nov/Dec
2003)
20. What is pipelined architecture? (May/June 2006)
21. List the segment registers of 8086. (Nov/Dec 2003)
22. How 20 bit physical address is generated from 16 bit internal registers in 8086?
(April/May 2004)
23. Write interrupts present in 8086 with interrupt vector table. (May/June 2014)
24. What is exceptional condition in 8086? Give example.

25. Write the purpose of segment registers. (Nov/Dec 2007)

26. Why interface is needed in a microprocessor based system? (Nov/Dec 2007,
(May/June 2006)
27. Calculate how many devices can be addressed by 8086 (Nov/Dec 2007)
28. State the disadvantages of memory mapped I/O scheme (Nov/Dec 2005)
29. What are the differences between 8085 and 8086 (Nov/Dec 2004)
30. Which instruction is used to perform BCD arithmetic operation?
31. What is meant by opcode fetch cycle?
32. What is the significance of I/O ports?(April/May 2008)
33. What is the difference between machine cycles in 8085 microprocessor?(April/May
2008)
34. To obtain a 320 ns clock, what should be the input clock frequency? What is the
frequency of clock signal at CLK OUT?(May/June 2014)
35. What is meant by level triggered interrupt? Which of the interrupts in 8085 are level
triggered?(May/June 2014)
36. What are the different machine cycles in 8085 Microprocessor? (APRIL MAY 2008)
37. What does a program counter do in an 8085 processor? (May/June 2012)

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38. Identify the type of addressing, number of T states in each of the instruction given (a)
STA 2500H (b) JC 4100H. (May/June 2013)
39. What is the use of CLKOUT and RESET OUT signals of 8085 processor? NOV/DEC
2013
40. What is the maximum memory size that can be addressed by 8086? NOV/DEC 2013
41. Specify the four control signals commonly used by the 8085 MPU. NOV/DEC 2013
42. If the memory chip size is 2048*8 bits, how many chips are required to make up 16k
bytes memory? (Nov /Dec 2012)
43. What is the difference between CPU bus and system bus?
44. What is HOLD and HLDA? How is it used?
45. Explain the function of IO / M.
46. List the various machine cycles in 8085.
47. What is T state?
48. Give example for bus idle condition.
49. Specify the functions of S1 and S0.
50. Specify the functions of X1 and X2.
51. What are maskable and non maskable interrupts?
52. What is TRAP?
53. Draw the timing diagram for IO read cycle.
54. How many address lines are needed for 4K memory?
55. List some features of 8086.
56. What is the data and address size in 8086?
57. Write the bit pattern of 8086 flag register.
58. Explain the function of M / IO pin in 8086.(Any signal can be asked)
59. What are the operating modes of 8086?
60. List out the minimum mode signals.
61. List out the maximum mode signals.
62. How clock signal is generated in 8086? What is the maximum internal clock
frequency?
63. Which signals are responsible for selecting the memory?
64. Why the memory bank is divided into odd and even memory banks in 8086?
PART B
1. Explain the functional block diagram and explain architectural features of 8085.
(April/May 2004,2010, Nov/Dec 2007,12,13, May/June 2006, 2007,2012,2013,2014)
2. Draw the pin diagram of 8085 and explain the various pin details. (Apr/May
2009,2010) (May/June 2013,14)
3. Explain the 8085 interrupt system in detail. (April/May 2004,2009)(NOV/DEC 2013)
4. Design a memory system for the 8085 processor such that it contains 16Kb of
EPROM and 4Kb of RAM.
5. Design a memory system for the 8085 processor such that it contains 8Kb of EPROM
and 4Kb of RAM with starting addresses 0000H and A000H.
6. Compare memory mapped IO and IO mapped IO. (Nov/Dec 2004) (Nov /Dec 2012)

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7. Distinguish b/w the memory mapped IO and peripheral IO Nov /Dec 2013
8. Explain the timing diagram of memory read and memory write cycle of 8085
(Nov/Dec 2004)
9. Explain the timing diagram of interrupt acknowledge cycle of 8086
10. Explain the timing diagram of interrupt acknowledge cycle of 8085
11. Explain the timing diagram of IO read and write cycle of 8086
12. Explain the timing diagram of IO read of 8085 (April/May 2004)
13. Interface 8KX8 EPROM and 8KX8 RAM with 8086 and 8085 (Nov/Dec 2005)
14. Difference between minimum and maximum mode of operation of 8086.(NOV/DEC
2013)
15. Explain the interrupt structure of 8086
16. Write short notes on memory segmentation of 8086.
17. Explain the function of storing and retrieving of 16 bit at an odd and even addressed
bank with necessary diagram (May/June 2007)
18. Draw and explain the architectural block diagram of 8086 (Nov/Dec 2004,
2003,2007)
19. Explain the functions of software and hardware interrupt structure in 8085 with
suitable diagram(May/June 2013)(Apr/May 2010)
20. Explain about registers with suitable diagram.(May/June 2013)
21. Draw the schematic of latching the lower-order address bus and explain(Nov /Dec
2012)
22. Explain with a suitable diagram about address latch enable (May/June 2013).
23. Draw and explain timing diagram of the following instructions of 8085
microprocessor i)LDA 2050H ii) RET (April/May2008)
24. With necessary diagrams ,write a short note on the following)RAM memory
interfacing, ii)ROM memory interfacing, iii)interrupt structure of
8085(April/May2008)
25. Explain how pipelined architecture is implemented in 8086. (May/June 2006,14)
Nov/Dec 2013
26. Write a 8085 based program to multiple two 8 bit data(NOV/DEC 2013)
27. Explain the interfacing of memory with 8085 microprocessor and explain memory
read and write operations with timing diagrams.
28. Draw the timing diagram for PUSH instruction with appropriate examples.
29. Draw the timing diagram for CALL instruction with appropriate examples.
30. Draw the timing diagram for SHLD instruction with appropriate examples.
31. draw the timing diagram of OUT instruction and explain.(8) (May/June 2012)
32. Draw the timing diagram for LXI instruction with appropriate examples.
33. Draw the timing diagram for CMP M instruction with appropriate examples.
34. Draw and explain the timing diagram of any one ‘three byte instruction’. May /June
2009)
35. Draw the 8085 timing diagram for execution of the instruction “MV1 A, 32h” and
explain. (Nov /Dec 2012)

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36. How the memory is classified? Tabulate the characteristics of memory mapped I/O
and peripheral I/O. (Nov /Dec 2012)
37. Explain in detail about the minimum and maximum mode operation of 8086 system with
their respective timing diagram (Nov/Dec 2007)
38. Explain the functions of various registers and the use of instruction queue in 8086
microprocessor(NOV/DEC 2013)
39. Draw the timing diagram for the instruction “STA 4500” and explain. (NOV/DEC
2012)
40. Draw and explain the timing diagram of the following 8085 instructions: STA 4000H.
NOV/DEC 2013
41. Describe the functions of 8086 queue. How does queue speeds up the processing?
(NOV/DEC 2012)
42. Draw the schematic and explain how address and data are de-multiplexed in 8085.
(May/June 2013)
43. design a 8085 microprocessor system such that 2k byte of EEPROM and 4k byte of
RAM 0000H and 6000H respectively. (May/June 2014)
44. Explain the priority of 8086 interrupts with an example. (Nov/Dec 2012)

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