Paavai Institutions Department of EEE

UNIT II

PROGRAMMING OF 8085
PROCESSOR

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CONTENTS
Technical Terms
2.1 Instruction Format
2.2 Addressing Modes
2.3 Instruction Set
2.3.1 Data Transfer Instructions
2.3.2 Arithmetic Instructions:
2.3.3 Logical Instructions
2.3.4 Branching Instructions
2.3.5 Machine Control Instructions
2.4 .Assembly Language Programming Examples
2.5 Programming using Look Up Table

Question Bank

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Technical terms

1. Assembly Language: The languages in which the mnemonics (short -hand form of
Instructions) are used to write a program are called assembly language. The
manufacturers of microprocessor give the mnemonics.
2. Bit: A digit of the binary number or code is called bit. Also, the bit is the fundamental
storage unit of computer memory.
3. Byte : The 8-bit (8-digit) binary number or code is called byte
4. Word: 16-bit binary number or code is called word. (Some microprocessor
manufactures refer the basic data size operated by the processor as word).
5. Opcode: Opcode (Operation code) is the part of an instruction / directive that
identifies a specific operation.
6. Operand: Operand is a part of an instruction / directive that represents a value on
which the instruction acts.

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2.1 Instruction Format

An instruction is a command to the microprocessor to perform a given task on a
specified data. Each instruction has two parts: one is task to be performed, called the
operation code (opcode), and the second is the data to be operated on, called the operand. The
operand (or data) can be specified in various ways. It may include 8-bit (or 16-bit ) data, an
internal register, a memory location, or 8-bit (or 16-bit) address. In some instructions, the
operand is implicit. Instruction word size .
The 8085 instruction set is classified into the following three groups according to
word size: 1. One-word or 1-byte instructions 2. Two-word or 2-byte instructions 3. Three-
word or 3-byte instructions In the 8085, "byte" and "word" are synonymous because it is an
8-bit microprocessor. However, instructions are commonly referred to in terms of bytes rather
than words. One-Byte Instructions A 1-byte instruction includes the opcode and operand in
the same byte. Operand(s) are internal register and are coded into the instruction.
Task Op code Operand Binary Code Hex Code
Copy the contents of the
MOV C,A 0100 1111 4FH
accumulator in the register C.
Add the contents of
register B to the contents of ADD B 1000 0000 80H
the accumulator
Invert (compliment) each bit
CMA 0010 1111 2FH
in the accumulator.
these instructions are 1-byte instructions performing three different tasks. In the first
instruction, both operand registers are specified. In the second instruction, the operand B is
specified and the accumulator is assumed. Similarly, in the third instruction, the accumulator
is assumed to be the implicit operand. These instructions are stored in 8- bit binary format in
memory; each requires one memory location. MOV rd, rs rd <-- rs copies contents of rs into
rd. Coded as 01 ddd sss where ddd is a code for one of the 7 general registers which is the
destination of the data, sss is the code of the source register.

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Two-Byte Instructions In a two-byte instruction, the first byte specifies the operation
code and the second byte specifies the operand. Source operand is a data byte immediately
following the opcode
Three-Byte Instructions In a three-byte instruction, the first byte specifies the
opcode, and the following two bytes specify the 16-bit address. Note that the second byte is
the low-order address and the third byte is the high-order address. opcode + data byte + data
byte
Instruction Execution and Data Flow In 8085
The program instructions are stored in memory, which is an external device. To
execute a program in 8085, the starting address of the program should be loaded in program
counter. The 8085 output the content of program counter in address bus and asserts read
control signal low. Also, the program counter is incremented.
The address and the read control signal enable the memory to output the content of
memory location on the data bus. Now the content of data bus is the opcode of an instruction.
The read control signal is made high by timing and control unit after a specified time. At the
rising edge of read control signals, the opcode is latched into microprocessor internal bus and
placed in instruction register. The instruction-decoding unit, decodes the instructions and
provides information to timing and control unit to take further actions.

2.2 Addressing Modes

Every instruction of a program has to operate on a data. The method of specifying the
data to be operated by the instruction is called Addressing. The 8085 has the following 5
different types of addressing.
1. Immediate Addressing
2. Direct Addressing
3. Register Addressing
4. Register Indirect Addressing
5. Implied Addressing
Immediate Addressing
In immediate addressing mode, the data is specified in the instruction itself. The data
will be apart of the program instruction. All instructions that have ‘I’ in their mnemonics are
of immediate addressing type.

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Eg. MVI B, 3EH - Move the data 3EH given in the instruction to B register.
Direct Addressing
In direct addressing mode, the address of the data is specified in the instruction. The
data will be in memory. In this addressing mode, the program instructions and data can be
stored in different memory blocks. This type of addressing can be identified by 16-bit address
present in the instruction.
Eg. LDA 1050H - Load the data available in memory location 1050H in accumulator.
Register Addressing
In register addressing mode, the instruction specifies the name of the register in which
the data is available. This type of addressing can be identified by register names (such as A,
B, C, D, E, H, L ) in the instruction.
Eg. MOV A, B -Move the content of B register to A register.
Register Indirect Addressing
In register indirect addressing mode, the instruction specifies the name of the register
in which the address of the data is available. Here the data will be in memory and the address
will be in the register pair. This type of addressing can be identified by letter ‘M’ present in
the instruction.
Eg. MOV A, M - The memory data addressed by HL pair is moved to A register.
Implied Addressing
In implied addressing mode, the instruction itself specifies the type of operation and
location of data to be operated. This type of instruction does not have any address, register
name, immediate data specified along with it.
Eg. CMA - Complement the content of accumulator.

2.3 Instruction Set

An Instruction is a command given to the computer to perform a specified operation on given

data. The instruction set of a microprocessor is the collection of the instructions that the
microprocessor is designed to execute. The instructions described here are of Intel 8085.
These instructions are of Intel Corporation. They cannot be used by other microprocessor
manufactures. The programmer can write a program in assembly language using these
instructions. These instructions have been classified into the following groups:

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1. Data Transfer Group

2. Arithmetic Group
3. Logical Group
4. Branch Control Group
5. I/O and Machine Control Group

Data Transfer Group

Instructions, which are used to transfer data from one register to another register, from
memory to register or register to memory, come under this group. Examples are: MOV, MVI,
LXI, LDA, STA etc. When an instruction of data transfer group is executed, data is
transferred from the source to the destination without altering the contents of the source. For
example, when MOV A, B is executed the content of the register B is copied into the register
A, and the content of register B remains unaltered. Similarly, when LDA 2500 is executed the
content of the memory location 2500 is loaded into the accumulator. But the content of the
memory location 2500 remains unaltered.

Arithmetic Group

The instructions of this group perform arithmetic operations such as addition, subtraction;
increment or decrement of the content of a register or memory. Examples are: ADD, SUB,
INR, DAD etc.

Logical Group

The Instructions under this group perform logical operation such as AND, OR, compare,
rotate etc. Examples are: ANA, XRA, ORA, CMP, and RAL etc.

Branch Control Group

This group includes the instructions for conditional and unconditional jump, subroutine call
and return, and restart. Examples are: JMP, JC, JZ, CALL, CZ, RST etc.

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I/O and Machine Control Group

This group includes the instructions for input/output ports, stack and machine control.
Examples are: IN, OUT, PUSH, POP, and HLT etc.

2.3.1 Data Transfer Instructions: Includes the instructions that moves (copies) data
between registers or between memory location and register. In all data transfer operations the
content of source register/memory is not altered Hence the data transfer is copying operation.
1. MOV
The content of source register ( ) is copied to destination register ( ). The registers
and can be anyone of the purpose registers A, B, C, D, E, H and L. No flags are
affected.
MOV A, A MOV B, A MOV C, A MOV D, A
MOV A, B MOV B, B MOV C, B MOV D, B
2. MOV
The content of memory (M) addressed by HL pair is moved to destination register
( ). The register can be any one of the general purpose registers A, B, C, D, E, H and L.
No flags are affected.
3. MOV
The content of source register ( ) is moved to memory location addressed by HL
pair. The
register can be any one of the general purpose registers A, B, C, D, E, H and L. No flags
are affected.
MOV M,A MOV M,C
4. MVI
The 8-bit data ( ) given in the instruction is moved to destination register ( ). The
register can be any one of the general purpose registers A B, C, D, E, H and L. No flags
are affected.
MVI A,
MVI C,
5. MVI M,

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The 8-bit data ( ) given in the instruction is moved to memory location addressed by
HL pair. No flags are affected.
6. LDA addr16
The content of memory location whose address is given in the instruction, is moved to
accumulator. No flags are affected.
7. LHLD addr16
The content of memory location whose address is given in the instruction, is moved to
L register. The content o next memory location is moved to H-register. No flags are affected.
8. LXI

The 16-bit data given in the instruction is moved to register pair ). The register pair

can be BC, DE, HL and SP.

LXI B,
9. LDAX

The content of memory addressed by register pair ( is moved to accumulator. (The

content of register pair is the memory address). The register pair can be either BC or DE.
Total number of instructions=2
LDAX B
10. STA addr16
The content of accumulator is moved to memory. The address of the memory location
is given in the instruction. No flags are affected.
Total number of instruction=1
11. STAX

The content of accumulator is moved to memory addressed by register pair ( ). (/the

content of register pair is the memory address). The register pair can be either BC or DE.
Total number of instruction=2
STAX B STAX D
12. SHLD addr16
The content of L register is stored in memory location, whose address is given in the
instruction. The content of H register is stored in next memory location. No flags are affected.
Total number of instruction=1
13. SPHL

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The content of HL pair is moved to stack pointer (SP). No flags are affected.
The total number of instruction=1
14. XCHG
The content of HL pair is exchanged with DE pair. No flags are affected.
Total number of instruction=1
15. XTHL
The content of top of stack is exchanged with HL pair. Stack is a portion of memory
(RAM memory). The content of stack pointer (SP) is the address of top of stack. No flags are
affected.
Total number of instruction=1
16. PUSH

The content of register pair ( ) is pushed to stack. After execution of this instruction

the content of stack pointer (SP) will be 02 less than the earlier value. The register pairs can
be BC, DE, HL and PSW. No flags are affected.
Total number of instruction=4
PUSH PSW PUSH D
17. POP

The content of top of stack memory is moved to register pair. After execution of this
instruction the content of stack pointer (SP) will be 02 greater than the earlier value. The
register pairs can be BC, DE, HL and PSW. No flags are affected.[PSW program status
word): Accumulator and flag register together Called PSW. Accumulator is high order
register and flag register is low order register.]
Total number of instructions=4
POS PSW POP D
18. IN addr8
The content of port is moved to A-register. The 8-bit port address will be given in the
instruction. No flags are affected.
19. OUT addr8
The content of A-register is moved to pot. The 8-bit port address will be given in the
instruction. No flags are affected.
Total number of instruction=1

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2.3.2 Arithmetic Instructions:

Includes the instructions which performs addition, subtraction, increment or decrement
operations. The flag conditions are altered after execution of an instruction in this group.
1. ADD reg
The content of the register is added to the content of accumulator (A-register0). After
addition the result is stored in accumulator. All flags are affected. The register can be any one
of the general purpose register A, B, C, D, E, H and L.
Total number of instructions=7
ADD A ADDC
2. ADI
The 8-bit data given in the instruction is added to the content of A-register (Accumulator).
After addition the result is stored in accumulator. All flags are affected.
Total number of instruction=1
3. ADD M
The content of memory addressed by HL pair is added to the content of A-register. After
addition the result is stored in A-register. All flags are affected.
Total number of instruction=1
4. ACI
The 8-bit data given in the instruction and the carry flag (the value of carry flag before
executing this instruction) are added to the content of A-register (Accumulator). After
addition the result is stored in accumulator. All flags are affected.
Total number of instruction=1
5. ADC reg
The content of the register and the carry flag are added to the content of the A-register. After
addition the result is stored in A-register. All flags are affected. The register can be any one
of the general purpose register A, B, C, D, E, H and L.
Total number of instruction=7
6. ADC M
The content of memory addressed by HL pair and the value of carry flag (before execution
this instruction) are added to the content of A-register. After addition the result is stored in A-
register. All flags are affected.
Total number of instruction=1

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7. SUB reg
The content of the register is subtracted from the content of the accumulator (A-register).
After subtraction the result is stored in A-register in A- register. All flags are affected. The
register can be anyone of the general purpose register A, B, C, D, E, H and L.
Total number of instruction=7
SUB A SUB C
8. SUI d8
The 8-bit data given in the instruction is subtracted from A-register (accumulator0. After
subtraction the result is stored in A-register. All flags are affected.
Total number of instruction=1
9. SUB M
The content of memory addressed by HL pair is subtracted from A-register. After subtraction
the result is stored in A-register. All flags are affected.
Total number of instruction=1
10. SUB reg
The content of register and the value of carry (before executing his instruction) are subtracted
from accumulator (A-register). After subtraction the result is stored in accumulator. All flags
are affected. The register can be anyone of the general purpose register A, B, C, D, E, H and
L.
Total number of instruction=7
11. SBI d8
The 8-bit data given in the instruction and the value of carry (before executing this
instruction) are subtracted from accumulator. After subtraction the result is stored in
accumulator. All flags are affected
Total number of instruction=1
12. SBB M
The content of memory addressed by HL and the value of carry (before executing this
instruction) are subtracted from accumulator (A –register. All flags are affected.
Total number of instruction=1
13. DAA (Decimal Adjust Accumulator)

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After BCD addition, the DAA instruction is executed to get the result in BCD. When DAA
instruction is executed the content of the accumulator is altered or adjusted as explained
below.
i) If the sum of lower nibbles exceeds or auxiliary carry is set, then a
correction is added to sum of lower nibbles.
ii) If the sum of upper nibbles exceeds or carry is set, then a correction
(0110) is added to sum of upper nibble.
After executing this instruction all flags are modified to indicate the status of result.
Total number of instruction=1
14. DAD (DOUBLE ADDITION)

The content of register pair is added to the content of HL pair. After addition the result is
stored in HL pair. Only carry flag is affected. The register pair can be BC, DE, HL or SP.
Total number of instructions=4
DAD B DAD H
15. INR reg
The content of the register is incremented by one. Except carry flag, all other flags are
affected. The register can be any one of the general purpose register A, B, C, D, E, H and L.
Total number of instruction=7
16. INR M
The content of memory addressed by HL pair is incremented by one. Except carry, all other
flags are affected.
Total number of instruction=1
17. DCR reg
The content of the register is decremented by one. Except carry, all other flags are affected.
The register can be A, B, C, D, E, H and L.
Total number of instructions=7
DCR A DCR C
18. DCR M
The content of memory addressed by HL pair is decremented by one. Except carry, all other
flags are affected.
Total number of instruction=1
19. INX

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The content of register pair is incremented by one. The register pair can be BC, DE, HL or
SP. No flags are affected.
Total number of instruction=4
INX 4 INX D
20. DCX

The content of register pair is decremented by one. The register pair can be BC, DE, HL or
SP. No flags are affected.
Total number o f instructions=4
DCX B DCX H

2.3.3 Logical Instructions:

The instructions which performs the logical operations like AND, OR EXCLUSIVEOR,
complement, compare and rotate instructions are grouped under this heading. The flag
conditions are altered after execution o an instruction in this group.
1. ANA reg
(& is the symbol used for logical AND operation)
The content o the register is logically ANDed bit by bit with the content of accumulator. I bit
by bit AND operation, the bit of register is ANDed with bit of A-register, the bit of
register is ANDed with bit of A-register, and so on. The register can be any one of the
general purpose register A,B,C,D,E,H and L. After execution of the instruction carry flag is
always reset and auxiliary carry flag is always sed. Other flags are altered(according to the
results). After AND operation result is stored in accumulator.
Total number of instructions=7
ANA A ANA C
2. ANI d8
The 8=bit data given in the instruction is logically ANDed bit by bit with the content of
accumulator. The result is stored in accumulator. After execution of this instruction CY=0
and AC=1. Other flags are affected.
Total number of instruction=1
3. ANA M
The content of memory addressed by HL pair is logically ANDed bit by bit with the content
of accumulator. The result is stored in accumulator. After execution CY=0 and AC=1. Other

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flags are affected.

Total number of instruction=1
4. ORA reg
(l is the symbol used for logical OR operation)
The content of the register is logically ORed bit by bit with the content of accumulator. In bit
by bit OR operation, the bit of the register is ORed with bit of A-register, the bit of
the register is ORed with bit of A-register, and so aon. The register can be any one of the
general purpose register A,B,C,D,E,H and L. After execution of the instruction both the carry
and auxiliary flags are always reset (AC=0, CY=0). Other flags are modified (according to
the result). After OR operation the result is stored in accumulator.
Total number of instruction=7
5. ORA M
The content of memory addressed by Hl pair is logically ORed bit by bit with the content of
accumulator. The result is stored in accumulator. After execution, CY=AY=0. Other flags are
affected.
Total number of instruction=1
6. ORI d8
The 8-bit data given in the instruction is logically ORed bit by bit with the content of
accumulator. The result is stored in accumulator. After execution of this instruction,
CY=AY=0. Other flags are affected.
Total number of instruction=1
7. XRA reg
(^ is the symbol used for logical XCLUSIVE-OR operation).
The content o the register is logically EXCLUSIVE-ORed bit by bit with the content of
accumulator. In bit by bit EXCLUSIVE-OR operation, the bit of register is EXCLUSIVE-
ORed with bit of register, THE BIT of register is EXCLUSIVE-ORed with bit of A-
register, and so on. The result is stored in accumulator. The register can be anyone of the
general purpose register A, B, C, D, E, H and L. After execution AC=CY=O=0. Other flags are
modified (according to the result).
Total number of instructions=7
8. XRI d8

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The 8-bit data given in the instruction is logically EXCLUSIVE-ORed bit by bit with the
content of accumulator. The result is stored in accumulator. After execution of this instruction,
CY=AF=0. Other flags are affected.
Total number of instructions=1
9. XRA M
The content of memory addressed by Hl pair is logically EXCLUSIVE –Ored bit by bit with
the content of accumulator. The result is stored in accumulator. After execution, CY=AC=0.
Other flags are affected.
10. CMP reg
The content of the register is compared with accumulator. The comparison is performed by
subtracting the content of register from A-register. The subtraction is performed I ALU, and the
result is used to modify flags and then the result is discarded i.e., it is not stored in any register
After execution of this instruction the content of accumulator and the register are not altered.
All flags are affected by this instruction. The register can be one of the general purpose
register A,B,C,D,E,H and L.
Total number of instructions=7
CMP A CMP C
11. CPI d8
The 8-bit data given in the instruction is compared with accumulator. The comparison is
comparison is performed by subtraction the 8-bit data from A-register. The subtraction is
performed in ALU and the result is used to modify flags and then discarded. After execution
of the instruction the content of accumulator is not altered. All flags are affected.
The number of instruction=1
12. CMP M
The content of memory addressed by HL pair is compared with accumulator. The comparison
is performed by subtracting the content of memory from A-register. The subtraction is
performed in ALU and the result is used to modify flags and then discarded. After execution of
the instruction the content of the accumulator and the memory are not altered. All flags are
affected by this instruction.
The number of instruction=1
13. CMA (Complement Accumulator)
The content of accumulator is complemented. No flags are affected. One byte instruction.

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14. STC (Set Carry)

The carry flag is set to 1. Only carry flag is affected by this instruction.
15. CMC (Complement Carry)
The carry flag is complemented. Only carry flag is affected by this instruction.
16. RLC (Rotate Accumulator Left to carry)
The content of A-register is rotated left by one bit and the left most bit of A-register is rotated
to carry. [The let most bit is most significant bit]. Only carry flag is affected.
17. RRC (Rotate Accumulator Right to Carry)
The content of A-register is rotated right by one bit and the right most bit of A-register is
rotated to carry. [The right most bit is least significant bit]. Only carry flag is affected.
18. RAR (Rotate Accumulator Right through carry)
The content of A-register along with carry is rotated right by one bit. Here the carry is moved
to most significant bit ( ) position and the least significant bit ( ) is moved to carry. Only
carry flag is affected.
19. RAL (Rotate Accumulator Left through carry)
The content of A-register along with carry is rotated left by one bit. Here the carry is moved to
least significant bit ( ) position and the most significant bit ( ) is moved to carry. Only carry
flag is affected.
2.3.4 Branching Instructions:
The instructions that are used to transfer the program control from one memory location to
another memory location are grouped under this heading.
1. JMP addr16
It is unconditional jump instruction. When this instruction is executed, the address given in the
instruction is moved to program counter. Now the processor starts executing the instructions
stored in this address
Three byte instruction. Immediate addressing.
2. J<condition> addr16
It is conditional jump instruction. The conditional jump instruction will check a flag condition.
If the flag condition is true then the address given in the instruction is moved to program
counter. Thus the program control is branched to jump address. If the flag condition is false,
then the next instruction is executed. There are eight conditional jump instructions.
3. CALL addr16

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It is unconditional CALL used to call a subroutine program. When this instruction Is executed
the address of the next instruction in the program counter is pushed to stack. The 16-bit address
(which is the address of subroutine program) given in the instruction is loaded in program
counter. Now the processor will start executing the instructions stored in this call address.
4. C<condition> addr16
It is conditional subroutine call instruction. The conditional CALL instruction will check for a
flag condition is true, then the address of the next instruction is pushed to stack and the call
address (address given in the instruction) is loaded in program counter. Now the processor will
start executing the instructions stored in this address. If the flag condition is false, then the next
instruction is executed.
5. RET (Return to main program)
It is unconditional return instruction. This instruction is placed at the end of subroutine
program, in order to return to the main program. When this instruction is executed the top of
stack is poped to (loaded into0 program counter.
6. R<condition>
If <condition> is TRUE then,
It is conditional return instruction.
In a conditional return instruction a flag condition is tested. If the flag condition is true then the
program control return to main program by poping the top of stack to program counter. If the
flag condition is false then the next instruction is executed.
7. RST n
It is restart instruction. The restart instructions are also called as software interrupts. Each
restart instruction has a vector address. The vector address is fixed by the manufacturer
When a restart instruction is executed, the content of program counter is pushed to stack and
the vector address is loaded in the program counter. The vector address is internally generated
(computed) by the processor. The vector address for RST n is obtained by multiplying n by 8.
Thus the program control is branched to a subroutine program stored in this vector address.
8. PCHL
The content of HL register pair is moved to program counter. Since this instruction alters the
content of program counter, the program control is transferred to new address. This instruction
is used by the system designer to implement the system subroutine to execute a program.

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2.3.5 Machine Control Instructions: Includes the instruction related to interrupts and the
instruction used to halt program execution.
1. DI (Disable Interrupts)
When this instruction is executed all the interrupts except TRAP are disabled. [When the
interrupts are disabled the processor will not accept or recognize the interrupt request made by
the external devices through the interrupt pins. When the processor is doing an emergency
work, it can execute DI instruction to prevent the interrupts from interrupting the processor. ]
2. EI (Enable Interrupts)
This instruction is used to allow the interrupts after disabling.(the interrupts except TRAP are
disabled after processor reset or after execution of DI instruction. When we want to allow the
interrupts, we have to execute EI instructions).
3. SIM (Set Interrupt Mask)
The SIM instruction is used to mask the hardware interrupts RST 7.5, RST 6.5 and RST 5.5. It
is also used to send data through SOD line. The execution of SIM instruction uses the content
of the accumulator to perform the functions.
4. RIM (Read Interrupt Mask)
The RIM instruction is used to check whether an interrupt is masked or not. It is also used to
read data from SID line. (SID: Serial Input Data pin of 8085 processor). When RIM instruction
is executed the accumulator is loaded with 8-bit data. The 8-bit data in the accumulator can be
interpreted.
5. HLT (Half Program Execution)
This instruction is placed at the end of the program. When this instruction is executed
the processor suspends program execution and bus will be in idle state.
6. NOP (No Operation)
The NOP is a dummy instruction, it neither achieves any result nor affects any CPU registers.
This is a useful instruction for producing software delay and reserve memory spaces for future
software modifications.

2.4 .Assembly Language Programming Examples

Addition of Two 8-Bit Numbers
MVI C, 00H
LXI H, 9000

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MOV A, M
INX H
ADD M
JNC Result
INR C
Result MOV A, C
STA 9501
HLT
Subtraction of Two 8-Bit Numbers
MVI C, 00H
LXI H, 9000
MOV A, M
INX H
SUB M
JNC Result
CMA
INR A
INR C
Result STA 9500
MOV A, C
STA 9501
HLT

Multiplication of two 8-bit numbers

MVI A, 00
MVI C, 00
MVI B, data#1
MVI D, data#2
Loop: ADD B
JNC next
INR C
Next: DCR D

UNIT-II 2.20
Paavai Institutions Department of EEE

JNZ loop
STA 4200H
MOV A, C
STA 4201H
BCD to Binary Conversion
LDA 4200
MOV B, A
ANI 0F
RLC
RLC
RLC
RLC
MOV B, A
XRA A
MVI C, 0AH
REP ADD B
DCR C
JNZ REP
MOV B, A
MOV A, E
ANI 0FH
ADD B
STA 4250
HLT
Binary to ASCII Code Conversion
LDA 4200
MOV B, A
ANI 0F
CALL ACODE
STA 4201
MOV A, B
ANI F0H

UNIT-II 2.21
Paavai Institutions Department of EEE

RLC
RLC
RLC
RLC
CALL ACODE
STA4202
HLT
Subroutine ACODE
ACODE: CPI 0A
JC SKIP
ADI 07
SKIP ADI 30
RET

ASCII Code to Binary Code

LXI H, 4200
MOV D, M
LXI B, 4300
LOOP: INX H
MOV A, M
CALL BIN
STAX B
INX B
DCR D
JNZ LOOP
HLT
Subroutine BIN
BIN: SUI 30
CPI 0A
RC
SUI 07
RET

UNIT-II 2.22
Paavai Institutions Department of EEE

2.5 Programming using Look Up Table

MVI B,08
MVI A,00(DISPLAY MODE
SETUP)
OUT C2
MVI A,CC(CLEAR DISPLAY)
OUT C2
MVI A,90(WRITE DISPLAY
RAM)
OUT C2
MVI A, FF(CLEAR DISPLAY
RAM)
OUT C0
DCR B
JNZ L1
IN C2
L2 : ANI 07
JZ L2
MVI A, 40(SET TO READ
FIFO
RAM)
OUT C2
IN C0
ANI 0F
MOV L, A
MVI H, 42
MOV A, M
OUT C0
JMP L2
LOOKUP TABLE

4200 0C 9F 4A 0B

4204 99 29 28 8F

4208 08 09 88 38

420C 6C 1A 68 E8

UNIT-II 2.23
Paavai Institutions Department of EEE

Question Bank
UNIT 2
PART A
1. How the instruction sets are grouped? May /June 2009) (May/June 2012)
2. How many machine cycles are needed to execute LHLD and XCHG instructions?
(April/May 2005)
3. To execute MVI A, 80H instruction, it takes ___________ T states. The type of
addressing is
________ addressing. (April/May 2004)
4. How many machine cycles are needed to execute STA 1800 (Nov/Dec 2005)
5. Which instruction can be used to find the status of pending interrupts (Nov/Dec 2005)
6. What are the 2 compare instructions available in 8085? (Nov/Dec 2004)
7. Explain the execution of the instruction CMA M in 8085 (Nov/Dec 2003)
8. Give two examples for two byte instruction and three byte instruction. (May/June
2012)
9. What are the addressing modes available in 8085?
10. Differentiate the register addressing mode and register indirect addressing mode with
an example? (MAY/JUNE2013)
11. What happens when the RET instructions at the end of a subroutine is executed? (Nov
/Dec 2012)
12. Write the logical steps to add the following hex numbers. Both the numbers should be
saved for future use. Save the sum in the accumulator.
a. Numbers: A2H and 18 H (Nov /Dec 2012)
13. Mention the difference between the DCR H, AND DCX H. Nov /Dec 2013
14. If the 8085 adds 87H and 79H,specify the content of the accumulator and the status of
S,Z,CY flags ( NOV/DEC 2012)
15. Calculate the number of T states required to generate a delay of 0.5 sec if the crystal
frequency is 4MHZ.(MAY/JUNE 2013)
16. Specify any 4 instructions to perform logical operation(May/June 2013)
17. Difference between OPCODE and OPERAND(April/May2008)
18. Write the stack related instruction in 8085 micro processor(April/May2008)
19. State the purpose and importance of NOP instructions.(May/June 2014)
20. Mention the instructions used for data transfer with I/O ports. (Apr/May 2010)
21. Differentiate CALL instruction from JUMP instruction. (Apr/May 2010)
22. Write an assembly program to multiply a number by 8 program using the rotate
instruction. May /June 2009)
23. List the instructions that affect only carry flag.
24. What is the similarity and difference between subtract and compare
instructions?(May/June 2014)
25. What is DAA?
26. What is DAD and what are the flags affected by this instruction?
27. List the various instructions used to clear the accumulator

UNIT-II 2.24
Paavai Institutions Department of EEE

28. List the I/O instruction in 8085

29. Explain DI and EI
30. What is PSW?
31. Explain PUSH instruction
32. Explain POP instruction
33. What is the function performed by SIM instruction?
34. What is the function performed by RIM instruction?
35. Give the instruction format of 8085 microprocessor?
36. Mention the 8085 instruction used for subroutine?

PART B
1. List and explain any four data transfer instruction and logical instruction. (May/June
2012)
2. Write an 8085 ALP to find the largest numbers. (May/June 2014)
3. Explain the SIM and RIM instruction of 8085 microprocessor. (May/June 2012)
(Nov/Dec 2012).
4. Write an assembly language program with algorithm in 8085 to convert the given
binary number into a BCD number. (Nov /Dec 2013)
5. Write an 8085 assembly language program, which checks to see if the number is even
or odd and if it is odd returns a ‘0’ in B register else returns a ‘1’. Nov/Dec 2013
6. Compare the similarities and difference of CALL and RET instruction with PUSH and
POP instruction. (May/June 2012) (Nov /Dec 2012)
7. Differentiate between (1) CALL instruction and JUMP instruction (2) CMP M and
SUB M instruction. (May/June 2013)
8. Classify the various instruction formats of INTEL 8085 microprocessor and explain
them with suitable examples. (Nov/Dec 2007)
9. Discuss in detail the classification of 8085 instruction set. Explain the instructions
under each
Category. Also explain the classification based on the word size with relevant
examples (Nov/Dec 2007)
10. Write a program to check a set of 6 signed numbers and add the positive numbers
(Nov/Dec 2007)
11. Explain the addressing modes of 8085 with examples (May/June 2006,
April/May2008) (Nov/Dec 2012).
12. Explain in detail about the indirect addressing mode in 8085. (May /June 2009)
13. Write 8085 assembly language program to divide 8 bit number and store the quotient
and reminder at the corresponding memory location. (May/June 2012)
14. Write a program to arrange N numbers in ascending order (Nov/Dec 2005,2012)
15. Write a program to arrange N numbers in descending order
16. Write an assembly language program to search a smallest data from an array of
numbers
17. Write an assembly language program to search a largest data from an array of numbers

UNIT-II 2.25
Paavai Institutions Department of EEE

18. With examples explain the loop structure with counting and indexing
19. Explain about all the JUMP instruction in detail.(May/June 2013)
20. Write the coding and draw the flowchart to calculate the area of a circle for the given
radius using 8085.
21. Explain about the stack structure and its instructions in detail.
22. Write 8085 assembly language program to perform the following, ab+ac, where a, b
and c are 8 bit binary numbers. Explain the algorithm and flowchart(April/May2008)
23. Describe the interrupts structure of 8085 microprocessor and compare same with 8086
microprocessor.(May/June 2014)
24. Write an 8085 assembly language program to generate a time delay of 1ms.show the
calculations.(May/June 2014)
25. Write a program to calculate and store in the results as mentioned. Five memory
locations 2401H,2402H,2403H,2404H,2405H have data called X1,X2,X3,X4,X5.
(2405H)=X1+X2+X3+X4,
(2403H)=X5-X3-X2-X1. (May/june 2014)
26. With example explain the conditional and unconditional instruction in 8085(Nov/Dec
2013)
27. Give the example for the instruction RLC, RRC, RAL and RAR. (May/June 2012)
28. Write an 8085 assembly language program to add the following five data bytes stored
in memory locations starting from 2060H, and display the sum. Data: 1A, 3, 4F,12,27.
(Nov /Dec 2012)
29. 16 bytes of data are stored in memory location at XC50h to XX5Fh. Transfer the entire
block of data to new memory locations starting at XX70h. (Nov /Dec 2012)
30. Write a 8085 assembly program to add the contents of mode locations 2000H to
2009H and place the result in the mode locations 2010H and 2011H. Nov/Dec 2013

UNIT-II 2.26