Unit-4

Memorv Management Strategies

approach to paging and
management algorithms vary from a primitive bare-machine
The memnory Selection of a
strategies. Each approach has its own advantages and disadvantages.
segmentation
factors, especially on the hardware
memory-management method for a specific systemn depends on many
design of the system.

Logical versus Physical Address Space

referred to as a Logical Address.
An address generated by the CPUis commonly
commonly referred to as a Phvsical Address.
An address seen by the memory unit is
a logical address space.
* The set of all logical addresses generated by a program is
to these logical addresses is a physical address
* The set of all physical addresses corresponding
space.
run-time mapping from virtual to physical addresses
is done by ahardware device called
* The
Memory Management Unit (MMU).

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Fragmentation
External Fragmentation: External fragmentation exists when there is enough total menmory
space to satisfy a request but the available spaces are not contiguous; storage is fragmented into a ge
umher of small hole This frnntatic. Droblem can be severe In toe worst c3

in one big free bloc. slead, we might be able o run several more processes.

Internal Fragmentation: The memory allocated to 4process may be slightly larger than the
requested memory. The difference between these two numbers is internal memory that is inter al to a
partition.
Compaction: One solution to the problem of external fragmentation is Compaction. The goal is to
shuftle the memory contents so as to place allfree memory together in one large block. Compaction is not
always possible. The simplest compaction algorithm is to move allprocesses toward one end of memory:
all holes move in the other direction, producing one large hole of available memory but this scheme can
be expensive. Another possible solution to the extenal-fragmentation problem is to permit the logical
address space of the processes to be noncontiguous.

ContiguOus memory allocation

* In contiguous menmory allocation, each process is contained in a single contiguous section of
memory.
Accessing memory incontiguous memory allocation is faster.
Managing contiguous memory allocation is easier.
External fragmentation may occur in contiguous memory allocation.
* Contiguous memory allocation can be classified in following two categories:
1. MFT (Multiprogramming with Fixed number of tasks).
2. MVT (Multiprogramming with variable number of tasks).

MET (Multiprogramming with Fixed number of tasks)

In this method memory is divided into fixed sized partitions. Each partition may contain exactly
one process. Thus, the degree of multiprogramming is bound by the number of partitions. In this
multiple partition method when a partition is free, a process is selected from the input queue and
is loaded into the free partition. When the process terminates, the partition becomes available for
another process. MFT suffers from following problems
VInternal fragmentation may occur in this method.
External fragmentation may occur in this method.
Deciding most appropriate value of Number of partitions and size of partition is difficult.
MVT (Multiprogramming wvith variable number of tasks)
In the scheme, the operating systenm keeps a table indicating which parts of memory are available and
which are occupied. Initially, all memory is available for user processes and is considered one large block
of available memory, a hole.
As processes enter the system, they are put into an input queue. The operat1ng
system takes into account the memory requirements of each process and the amount of available memory
space in determining which processes are allocated memory. When a process is allocated space, it is
loaded into memory, and it can then compete or CPU tne. When a process terminates. it releases its
memory which the operating system unay dhen fill with another process tron the input queue.
This mnethodsolves the problem of internal fragmentation.
External fragmentation may occur in this method.

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 Algorithms used in contiguous memory allocation
techniques
can start cither at the beginning of the set of
First fit: Allocate the first hole that is big enough. Scarching soon as we
holes or at the location where the previous first-fit search ended. We can stop searching as
find a free hole that is large enough.
We must search the entire list, unless the list is
Best fit: Allocate the smallest hole that is big enough.
leftover hole.
ordered by size. This strategy produces the smallest
search the entire list, unless it is sorted by size. This
Worst fit: Allocate the largest hole. Again, we must hole from
produces the largest leftover hole, which may be more useful than the smaller leftover
strategy
a best-fit approach.

allocation
Memory Protection in contiguous memory
space, we need the ability to determine the
To nake sure thateach process has a separate memory the process can access
and to ensure that
range of legal addresses that the process may access
by using two registers, usually a base
only these legal addresses. We can provide this protection
and a limit or relocation.
memory address. The limit register specifies
* The base register holds the smallest legal physical and the limit register is 100, then
holds 300
the size of the range. For example, if the base register
from 300through 400.
the program can legally access alladdresses
Protection of memory space is accomplished by having the
CPU hardware compare every address
program executing in user mode to
generated in user mode with the registers. Any attempt by a
results in a trap to the operating system.
access operating-system memory or other users' memory

Eirit reocation
rogister registcr

physical
logica addresS
andresS
memory
CPU

trap addressing error

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 Paging
address space a process to be
* Paging is a memory-management scheme that permits the physical
non-contiguous.
* Paging avoids external fragmentation but not internal fragmentation.

iogca pysical
addess address f0000 . . 0000

CPU

f1111.. 1111

ohysta
page tabe

Pagng hardware

* Paging involves breaking physical memory into fixed-sized blocks called frames and breaking
logical memory into blocks of the same size called pages.
* When a process is to be executed, its pages are loaded into any available memory frames from
their source
Every address generated the CPU(Logical address) is divided into two parts: a page number p and
a page offset d. The page number is used as an index into a page table. The page table contains the
base address of each page in physical memory. This base address is combined with the page offset
to define the physical memory address that is sent to the memory unit.
The size of apage is typically a power of 2, varying between 512 bytes and 16 MB per page,
depending on the computer architecture. The selection of a power of 2 as apage size makes the
translation of a logical address into a page number and page offset particularly easy.

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 Example:
frarne

page 0

page 1 1 page 0

page 2 23 2
37
page 3 page tabie 3 page 2
log ca 4 Dage 1
memony

7 page 3
phrysical
memory

Pagirg odel of log cal and ptrysical mernory

Page Table
Page table is a data structure maintained by OS.
In paging OS creates page table for every process separately.
Page table contains frame number, corresponding to Page number.
Page table resides in physical memory; it wastes large space in physical memory because
generally its size is large.
 Paging with TLB
table.
memory access, TLB is used with page
* To increase thespeed of hardwarecache. called atranslation
look aside buffer.
small. fast, lookup
TLB is a special,
following way.
The TLB is usedwith page tables in the address is generated
contains only a few of the page-table entries. When a logical
V The TLB (known as
number is presented to the TLB. If the page number is found
by the CPU, its page memory.
immediately available and is used to access
a TLB Hit). its frame number is reference to the page
number is not in the TLB (known as a TLB Miss), a memory
V If the page access memory.
be made. When the frame number is obtained. we can use it to
table must

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CPU pd
page trame
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prysicel
addess

TLB

TIB SS

pysical
fremony

fage tatie

Pag ng hardware witth TLB

Hit Ratio p =Ni/(NHt NMiss)

Effective Memory Access time = (NH *(TLg + Tp) + Nyiss *(TLB + 2*Tp))/( N + NMs)
Where:
NMjs > Total number of Miss in TLB
Ni. ’ Number of Hit in TLB
TrB>access tine of TLB
Tpy > access time of PM
Protection in Paging
Memory protection in a paged environ1nent is accomplished by protection bits associated
with each frame. Normally, these bits are kept in the page table.
One bit can define a page to be read-write or read-only. Every reference to memory goes
through the page table to find the correct frame number. At the same time that the physical
address is being computed, the protection bitscan be checked to verify that no writes are
being made to aread-only page. An attempt to write to a read-only page causes a hardware
trap to thc operating system.
One additional bit is generally attached to each entry in the page table called valid-invalid bit.
When this bit is set to "valid." the associated page is in the process's logical address space and
is thus a legal (or valid) page. When the bit is set to "invalid." the page is not in the process's
logical address space. Illegal addresses are trapped by use of the valid -invalid bit. The
operating system sets this bit for each page to allow or disallow access to the page.

2 paçe 0
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page 0 3 page1

page 1 4 page 2
2
page 2
37
pago 3 48

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10 468 70 i
page 5 8 pace 4
12 287 page tatie
9 paçe5

page n

Vald or invalid 9 bit in a page tatle

 Segmentation
Segnentation is a memory-management scheme
that supports User view of memory.
3 has
variable size segments. Each segment
collection of
In segmentation logical address space isa
a name and a length.
external fragmentation both.
Segmentation avoids internal fragmentation and
Segment table takes lesser space in physical mnemory
than page table.

Imit ASe

Segment
tabe
CPU

Ves

trap: addressing error physica mency

Each entry in the segment table has a segment base and a segment limit. The segment base
contains the starting physical address where the segment resides in memory, and the segment
limit specifies the length of the segment.

In segmentation logical address consists of two parts: a segment number, s, and an offset into that
segment, d. the segment number are used as an index to the segment table. The offset
d of the
logical address must be between 0 and the segment limit. If it is not, we trap to the operating
system (logical addressing attempt beyond end of segment). When an offset is legal, it is added to
the segment base to produce the address in physical memory of the desired byte. The segment
table is thus essentially an array of base-limitregister pairs.
Example: segment 2 is 400 bytes long and begins at location 4300. Thus, a reference to byte 53
of segment 2is mapped onto location 4300 +53- 4353. Areference to segment 3, byte 852, is
mapned to 3200 (the base of segment 3) + 852 = 4052 Areference to byte 1222 of segment 0
would result in a trap to the operating system, as this segment is only 1,000 bytes long.
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Virtual memory
processes that are not completely in
3 Virtual memory is a technique that allows the execution of
programs can be larger than physical
memory. One major advantage of this scheme is that
memory.
and to implement shared memory.
* Virtual memory also allows processes to share files easily performance
easy to implement, however, and may substantially decrease
Virtual memory is not
if it is used carelessly.

Demand Paging
loaded when they are demanded during
$ Indemand-paged virtual memory, pages are only
never loaded into physical memory.
program execution. Pages that are never accessed are thus
This technique is commonly used in virtual memory systems.
Indemand paging lazy swapper is used. It never swaps a
page into memory unless that page will
*
be needed.
Objective of Demand paging is to increase degree of multi-programming.

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measured by
Paging: Performance of demand paging is generally
Performance of Demand (0<p<1). We would expect pto
be close to
probability of apage fault
effective access time. Let pbe the page faults. The effective access time
is then
have only a few
zero-that is, we would expect to

Effectiveaccess time= (1 - p) *
ma tp* page fault time.

Page Replacement Policies

1. FIFO Page Replacement: first-in, first-out (FIFO) algorithm. AFIF0

The simplest page-replacement algorithm is a time when that page was brought into
replacemnent algorithm associates with each
page the
memory. When a page must be replaced,
the oldest page is chosen.
understand and progran.
$ FIFOpage-replacement algorithm is casy to
like 1,2,3,4,1,2,5, 1,2,3,4,5 number of faults
Belady's anomaly may occurs for some sequence
faults for three frames (nine).
for four frames (ten)is greater than the number of

Example:
reterence string
701 2 0 3 0 4 2 30 3 2 1 2
77
7 7
3

page rames

2. Optimal Page Replacement:

I has the lowest page-fault rate of all algorithms and will never suffer from Belady's
anomaly.
* ItReplace the page that will not be used for the longest period of time.
 Use of this page-replacement algorithm guarantees the lowest possible page fauit rate for a
fixed number of
frames. requires future
The optimal because it
page-replacement
knowledge of the reference algorithm is difficultto
d
implement.

string.
Example:
refterence string 0
017
7 0 1 2 0 3 0 A 2 3 03 2 1 2
77 z
4

pagetrames

3. LRUPage Replacement: renlace the nage that has not been used for the
longest
we can
* In least recently algorithm
period of time. page-replacement
how to implement LRU replacement. An LRU
is
** The major problem substantial hardware assistance.
algorithm may require

Example:

reference string
2 1 2 O 701
Þ 4 2 3 0 3
2 0 3
1
4

page frames

Thrashing
swap-in andswap-out than executing. Thrashing occurs
if it spending more time in
Aprocess is thrashing muliprogramming
much. too
when we increase degree of

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Thrashing
As the degree of multiprogramming increases, CPU utilization also increases, although more slowly, until
a maximum
is reached,. If the increased even further. thrashing sets in, and
CPU utilization drops sharply. degree of point,
At this to increase isCPU utilization and stop thrashing. we must
multiprogramming
decrease the degree of
multiprogramm1ng.

Locality of Reference
Locanty ot Reference refers to the tendency of the computer program to access instructions whose
addresses are near one another. The property of locality of 1eference is mainly shown by loops and
subroutine calls in a program.
"In case of loops in program control procegsing unit repeatedly refers to the set of instructions that
constitutethe loop.
" In case of subroutine calls, every time the set of instructions are fetched from memory.
" References to data items also get localized that means same data item is referenced again and
again.

Temporal Locality- Temporal locality means current data or instruction that is being fetched may be
needed soon. So we should store that data or instruction in the cache memory so that we can avoid again
searching in main memory for the same data.

Spatial Locality - Spatial locality means instruction or data near to the current memory location that is
being fetched, may be needed soon inthe near future. This is slihtly different from the temporal locality.
Here we are talking about nearly located memory locations while in temporal locality we were talking
about the actual memory location that was being fetched.

Bare Machine
In computer science, bare machine refers to a computer executing instructions directly on logic hardware
without an intervening operating system. prior to the development of operating systems, sequential
instructions were executed on the computer hardware directly using machine language without any

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