Test & Reliability Challenges in Advance Semiconductor Geometries
Test & Reliability Challenges in Advance Semiconductor Geometries
Yervant Zorian
Fellow & Chief Architect
6/9/13
Contents
Multi-media
Device Convergence
Digital TV
Multi-media
Access Wireless Connectivity
Anytime, Anywhere
Smart Automotive
Phone Infotainment
High Definition
Imaging Anywhere
Multi-functional
Picture Printer
Gaming Multi-media
PC
Convergence
Products: SMART Everything
Product Complexity / Capabilities
“SMART”
Data Center / Cloud Computing Trends
Application Framework
Software
Infrastructure Libraries O/S Runtimes
O/S
8
Integration
• Before 32nm, new process was introduced every other year
Since then, a new process every year
180nm HK/MG
130nm
90nm
65nm
p‐SiON
45nm
32nm
28nm
20nm
14nm
Timing Closure!
180nm
Signal Integrity
Power 130nm
Verification
90nm
Power !
Verification! 65nm
TestYield ! !
& Yield
45/40nm
Clocks
32/28nm
Power !!
22/20nm
Verification !! 14nm
3D
Power !!!
Verification !!! Power !!!
Software Verification !!! Power !!!
& Yield Software !! Verification !!!
TestYield
Variability
TestYield
Software !!!
Variability
! ! TestYield
& Yield &Yield
!! !!
!!!
3D! 3D!!
IC Design Expensive and Difficult
Memory
• Exploding digital logic size
Hard IP
– Global design teams
UDL
Scan
Memory
BIST Wrapper
• Increasing test & yield impact
Memory
– Quality – DPPM Scan Wrapper
– Total memory bit count
UDL UDL
– Yield Optimization Scan Scan
Variation from overlay shift Local variation with Voltage Global and local Vth variation
IIP
MIPI DigRF,
Ethernet SATA SD/MMC
CSI, DSI Embedded
controller controller controller controller Embedded
Memories
Memories
(SRAM,
XAUI SATA MIPI D-PHY ROM, NVM)
I2C GPIO UART PHYII PHY M-PHY
IIP IIP
P
Datapath
Logic Libraries
Infrastructure
Digital IP Physical IP
IP
SOC Test Solution
Accelerate Higher Quality, Lower Cost Test
®
• Easy integration and • High-speed SERDES • Physical-aware
• Pin-limited compression verification of self-test IP interfaces (PCI Express®, diagnostics
USB 3.0, etc.)
• Advanced fault models • High defect coverage • Fast identification of
• Verification IP for systematic yield loss
• Power-aware test
integration test mechanisms
Hierarchical Design & Verification
Embedded Memory Is Growing
Key Driver Of Design Success
40
100
35 CPU/DSP/Ctrlr ARM® Processor Cache Size 90
% Area Memory
70 80
30 All Other IP Blocks,
% Area Reused Logic
Combined 70
60 % Area New Logic
25 60
50
50
0
0 ARM3
ARM2 ARM7 ARM9 Cortex
2005 2006 2007 2008 2009 2010 2011 2012 2013 2014
Source: Semico, October 2011 Source: Wikipedia Source: Semico, June 2010
$1,000 0.1
$100 0.01
$10 0.001
$1 0.0001
1970 1980 1990 2000 2010 2020
• Cheating with physics induces more process variability at each nanometer node
• Some layout features react strongly to variability causing systematic yield issues
• Each successive nanometer node faces more systematic yield loss
**Chart data source - IBS
Embedded Test & Diagnosis
High Manufacturing Test Quality
Vth ↑
Vth ↓
Vth ↓
Vth ↑
-40
25 X
125 X X X
1 Mb 2 Mb 4 Mb 8 Mb 16 Mb 24 Mb 32 Mb
Embedded
100 Test & Repair
90
80
Memory Yield (%)
70
60
50 Memory
40 without
30 Repair
20
10
0 3 5 11 22 43 65 86
IP Designers
Foundries Standard cells, memory compilers
Significantly impacted. and custom design are impacted.
FinFETs in SRAMs
• Traditional faults
− stuck-at fault, stuck-open fault, transition fault,
address decoder fault, coupling fault, etc.
• Process variation faults
− Transistor threshold voltage is affected by
gate length (L) and fin thickness (Tfin).
• FinFET specific faults
− Opens in FinFET transistor back gate cause
delay and leakage faults (transistor threshold
voltage is affected by back gate voltage)
Detection Programmable
TAP
STAR processor
tck STAR processor
JPC TBOX
tms STAR processor
TBOX
tdi p1500
p1500
tdo TBOX
p1500
trstn p1500
R(~P)…… TBOX_SEL
Load alternative test algorithm
Load generated
TEST algorithm
Continue with
test flow
Automated Rapid Fault Isolation and
Identification
Tester
Identity
folder
Coordinate Identification
SoC with
ET&R
Silicon
Debugger
WGL/ Vector
STIL Generator
Multi-level Precision Diagnostics
Identity
folder
Fail Identity
Data Folder Visualizations Correlations
Bitmap
Coordinates
Statistical Prioritization of Failure Modes
Silicon Debugger Yield Optimization
Identifying Dominant Failure Mechanism
How to get the largest yield improvement
• 100x10x10 = 10k sites for FA • FA cycle time per site: 4-8 hours
– For each silicon lot during ramp
– Can manage <10 sites only
How Does Volume Diagnostics Help?
• Volume Diagnostics
– Statistical Analysis of Diagnostics results from multiple failing
chips
– Identifies systematic, yield-limiting issues by using design data
– Produce outputs for Physical Failure Analysis (PFA)
Defect Type
Low Yield Cell Fail By Failing Cell Spatial Failing Cells Failing Nets PFA Sites
Lot Test Map Trends and Nets On Layout Low Probability
Memory
Processor
DRAM,
Flash
Digital Stud Bump Flip Chip
Baseband
Source:
Prismark
Beyond SoC: SiP Alternatives
Limitations Benefits
Peripheral bonds only Area placement
Long wire bonds (high Excellent electrical
inductance, high crosstalk, low characteristics
speed interconnect) High densities
Limited to low-density Orders of magnitude higher
interconnects and with specific I/O interconnect densities between
pad routing dies
Through Silicon Via Pros and Cons
• Pros
– Allow even smaller package outline
– No pad extension needed
– Lower sensitivity to foreign material at
Camera assembly
– Wire bonding compatible layout
– Reflow process compatible
– Better interconnect routing capability
• Cons
– More complex technology
– Glass
– Silicon
– Back-end processes
Through via contacts
– Cost From top to bottom
3D Stacking is Not New…But TSVs Are!
Chip 1 Chip 2
• Multi-Chip Packaging
– Dense integration
board
– Heterogeneous technologies
Printed Circuit Board (PCB)
• Vertical Stacking
board
– Denser integration
Multi-Chip Package (MCP)
– Smaller footprint
• Through-Silicon Vias (TSVs)
board
– Even denser integration
System-in-Package (SiP) – Increased bandwidth
– Increased performance
– Lower power dissipation
board
– Lower manufacturing cost
TSV-Based 3D-SIC
Yield Implication Due to 3D Levels
Tests for 3D Induced Effects
KGD requires
Extra stress during probe, carriers, or WLBI
52
2D Test Flow vs. 3D Test Flow
Conventional 2D 3D-SIC
wafer fab wafer fab 1 wafer fab 2 … wafer fab n
• Terminology
– KGD : Known-Good Die test Test access is distinctly different!
– KGS : Known-Good Stack test Test contents might be different.
• Better name would have been “Known-Bad Die/Stack” test
Required Infrastructure
• In addition:
1. Tests for new intra-die defects
2. TSV interconnect tests
Advanced TSV-Interconnect Test
• Advanced fault models for TSV interconnects
– Delay faults
SO SO
G G
PI 1 PI 1
PO PO
1 1
G G
1 1D Q 1D Q 1 1D Q
1 1
SI SI
The Role of Advanced DfT Techniques
• RPCT – Reduced Pad-Count Testing
Reduce width of scan-test interface
– Useful to limit additional probe pads for KGD testing
– Same test data volume: smaller interface longer test length
• Example: DRAM-on-Logic
1. MBIST in DRAM Die
– “3D-Prepared” DRAM
– Proprietary memory content does not need to be released
• Intermittent Faults:
– unstable hardware activated by environmental changes
(lower voltage, temperature)
– often become permanent faults
– identifying requires characterization
– process variation – main cause of IF
• Transient Faults:
– occur because of temporary environmental conditions
– neutrons and -particles
– power supply and interconnect noise
– electromagnetic interference
– electrostatic discharge
Reliability Faults (cont)
• Infant Mortality
– rate worsens due to transistor scaling effects and new process
technology and material
• Aging Induced Hard Failures
– performance degradation over time (burn-in shows)
– degradation varies over chip-chip and core-core
• Soft Errors
– Random logic still at risk
– RAM decreasing SEU per bit
• Low Vmin increases bit failures in memories
• Transient Errors, such as timing faults, crosstalk are major
signal integrity problems
Field Reliability Challenge
100000
1
1997
0.1
0 0.05 0.1 0.15 0.2 0.25
1400
1200
0
400 300 200 100 0
Source: iRoC
SER Growth at SOC Level
1000
100
10
Memory SER
Logic SER (Seq + Comb)
1
1000 800 600 400 200 0 Expon. (Memory SER)
Expon. (Logic SER (Seq + Comb))
0
Source: iRoC
Robustness IP for ECC
Memory
code IP code
ECC Error Error
Syndrome
generator bits Logic Indication
bits Generator