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Seven Segment

The document describes a VHDL implementation of a seven-segment display controller, which utilizes a 100 MHz oscillator for timing. It includes various components for edge detection and display logic, as well as processes for clock division and LED control. The architecture manages the display of time in seconds and minutes, along with controlling multiple LEDs based on input signals.

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0% found this document useful (0 votes)
2 views7 pages

Seven Segment

The document describes a VHDL implementation of a seven-segment display controller, which utilizes a 100 MHz oscillator for timing. It includes various components for edge detection and display logic, as well as processes for clock division and LED control. The architecture manages the display of time in seconds and minutes, along with controlling multiple LEDs based on input signals.

Uploaded by

yashas.g8867
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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--Seven Segment Display------

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity seven_segment is
port(clk : in std_logic; --- 100 MHz oscillator on the board
reset : in std_logic;
Anode : out std_logic_vector(7 downto 0);
CA, CB, CC, CD, CE, CF, CG, DP : out std_logic;
led_green1, led_green2 : out std_logic;
led_red1, led_red2 : out std_logic;
led_blue1, led_blue2 : out std_logic;
led_en : in std_logic_vector(15 downto 0);
led_out : out std_logic_vector(15 downto 0)
);
end entity;

architecture seven_segment_a of seven_segment is

component rise_edge_det
port(clk : in std_logic; --- 100 MHz oscillator on the board
reset : in std_logic;
d_in : in std_logic;
rise_edge : out std_logic);
end component;

component display_logic
port(digit_in : in std_logic_vector(3 downto 0); --- 100 MHz oscillator on
the board
CA, CB, CC, CD, CE, CF, CG, DP : out std_logic
);
end component;

signal clk_div_1ms : integer range 0 to 25000;


signal clk_div_10ms : integer range 0 to 10;
signal clk_div_100ms : integer range 0 to 10;
signal clk_div_1s : integer range 0 to 1000;
signal clk_div_10s : integer range 0 to 10;
signal clk_div_1min : integer range 0 to 60;
signal clk_div_10min : integer range 0 to 10;

signal count_1ms : std_logic_vector(7 downto 0);


signal count_10ms : std_logic_vector(3 downto 0);
signal count_100ms : std_logic_vector(3 downto 0);
signal count_1s : std_logic_vector(3 downto 0);
signal count_10s : std_logic_vector(3 downto 0);
signal count_1min : std_logic_vector(3 downto 0);
signal count_10min : std_logic_vector(3 downto 0);

signal clk_1ms : std_logic;


signal clk_10ms : std_logic;
signal clk_100ms : std_logic;
signal clk_1s : std_logic;
signal clk_10s : std_logic;
signal clk_1min : std_logic;
signal clk_10min : std_logic;
signal tick_1ms : std_logic;
signal tick_10ms : std_logic;
signal tick_100ms : std_logic;
signal tick_1s : std_logic;
signal tick_10s : std_logic;
signal tick_1min : std_logic;
signal tick_10min : std_logic;

signal sel_digit : std_logic_vector(3 downto 0);


signal led_s : std_logic_vector(15 downto 0);

signal flag_1, flag_2 : std_logic;

begin

led_out <= led_s;

u1_tick_1ms: rise_edge_det port map


(clk => clk, reset => reset,
d_in => clk_1ms, rise_edge => tick_1ms);

u2_tick_10ms: rise_edge_det port map


(clk => clk, reset => reset,
d_in => clk_10ms, rise_edge => tick_10ms);

u3_tick_100ms: rise_edge_det port map


(clk => clk, reset => reset,
d_in => clk_100ms, rise_edge => tick_100ms);

-------For the first digit(seconds )in the Display------


u4_tick_1s: rise_edge_det port map
(clk => clk, reset => reset,
d_in => clk_1s, rise_edge => tick_1s);

-------For the second digit (seconds) in the Display------


u5_tick_10sec: rise_edge_det port map
(clk => clk, reset => reset,
d_in => clk_10s, rise_edge => tick_10s);

-------For the third digit (minutes) in the Display------


u6_tick_1min: rise_edge_det port map
(clk => clk, reset => reset,
d_in => clk_1min, rise_edge => tick_1min);

-------For the fourth digit (minutes) in the Display------


u7_tick_10min: rise_edge_det port map
(clk => clk, reset => reset,
d_in => clk_10min, rise_edge => tick_10min);

u8_display_1sec: display_logic port map(digit_in => sel_digit,


CA => CA, CB => CB,
CC => CC, CD => CD,
CE => CE, CF => CF,
CG => CG, DP => DP);

------Divide by 100000 (to make it milli seconds clock)--------


clk_div_p: process(clk, reset)
begin
if(reset = '1') then
clk_div_1ms <= 0;
clk_1ms <= '0';
clk_div_10ms <= 0;
clk_10ms <= '0';
clk_div_100ms <= 0;
clk_100ms <= '0';
clk_div_1s <= 0;
clk_1s <= '0';
clk_div_10s <= 0;
clk_10s <= '0';
clk_div_1min <= 0;
clk_1min <= '0';
clk_div_10min <= 0;
clk_10min <= '0';
count_1s <= "0000";
count_10s <= "0000";
count_1min <= "0000";
count_10min <= "0000";
count_1ms <= (others => '0');
count_10ms <= (others => '0');
count_100ms <= (others => '0');

led_s <= x"0001";

elsif(rising_edge(clk)) then

if(clk_div_1ms >= 24999) then


clk_div_1ms <= 0;
clk_1ms <= not clk_1ms;
else
clk_div_1ms <= clk_div_1ms + 1;
end if;

if(tick_1ms = '1') then


if(clk_div_1s >= 999) then
clk_div_1s <= 0;
clk_1s <= not clk_1s;
else
clk_div_1s <= clk_div_1s + 1;
end if;
end if;

if(tick_1ms = '1') then


if(clk_div_10ms >= 4) then
clk_div_10ms <= 0;
clk_10ms <= not clk_10ms;
else
clk_div_10ms <= clk_div_10ms + 1;
end if;
end if;

if(tick_10ms = '1') then


if(clk_div_100ms >= 4) then
clk_div_100ms <= 0;
clk_100ms <= not clk_100ms;
else
clk_div_100ms <= clk_div_100ms + 1;
end if;
end if;

if(tick_1s = '1') then


if(clk_div_10s >= 4) then
clk_div_10s <= 0;
clk_10s <= not clk_10s;
else
clk_div_10s <= clk_div_10s + 1;
end if;
end if;

if(tick_10s = '1') then


if(clk_div_1min >= 2) then
clk_div_1min <= 0;
clk_1min <= not clk_1min;
else
clk_div_1min <= clk_div_1min + 1;
end if;
end if;

if(tick_1min = '1') then


if(clk_div_10min >= 4) then
clk_div_10min <= 0;
clk_10min <= not clk_10min;
else
clk_div_10min <= clk_div_10min + 1;
end if;
end if;

if(tick_1s = '1') then


if(count_1s >= 9) then
count_1s <= "0000";
else
count_1s <= count_1s + 1;
end if;
end if;

if(tick_10s = '1') then


if(count_10s >= 5) then
count_10s <= "0000";
else
count_10s <= count_10s + 1;
end if;
end if;

if(tick_1min = '1') then


if(count_1min >= 9) then
count_1min <= "0000";
else
count_1min <= count_1min + 1;
end if;
end if;

if(tick_10min = '1') then


if(count_10min >= 5) then
count_10min <= "0000";
else
count_10min <= count_10min + 1;
end if;
end if;

if(tick_10ms = '1') then


if(count_10ms >= 9) then
count_10ms <= (others => '0');
else
count_10ms <= count_10ms + 1;
end if;
end if;

if(tick_100ms = '1') then


if(count_100ms >= 9) then
count_100ms <= (others => '0');
else
count_100ms <= count_100ms + 1;
end if;
end if;

if(tick_1ms = '1') then


if(count_1ms >= 15) then
count_1ms <= (others => '0');
else
count_1ms <= count_1ms + 1;
end if;
end if;

if(tick_1s = '1') then


if(led_en(0) = '1') then
if(flag_1 = '1') then
led_s <= x"0001";
flag_1 <= '0';
else
led_s <= led_s(14 downto 0) & led_s(15);
end if;

elsif(led_en(1) = '1') then


if(flag_2 = '1') then
led_s <= x"8000";
flag_2 <= '0';
else
led_s <= led_s(0) & led_s(15 downto 1);
end if;

elsif(led_en(2) = '1') then


led_s <= led_s + 1;
flag_1 <= '1';
flag_2 <= '1';

elsif(led_en(3) = '1') then


led_s <= led_s - 1;
flag_1 <= '1';
flag_2 <= '1';

elsif(led_en(4) = '1') then


led_s(15 downto 4) <= led_en(15 downto 4);
led_s(3 downto 0) <= "1111";
flag_1 <= '1';
flag_2 <= '1';
elsif(led_en(5) = '1') then
led_s(15 downto 5) <= not led_en(15 downto 5);
led_s(4 downto 0) <= "00000";
flag_1 <= '1';
flag_2 <= '1';

elsif(led_en(6) = '1') then


led_s <= x"ffff";
flag_1 <= '1';
flag_2 <= '1';

else
led_s <= x"0000";
flag_1 <= '1';
flag_2 <= '1';

end if;
end if;

end if;

end process;
--------------------------------------------------------

mux_sel: process(count_1ms, count_1s, count_10s, count_1min, count_10min,


count_100ms, count_10ms)
begin
if(count_1ms <= 1) then
sel_digit <= count_1s;
Anode <= "11111110";
elsif(count_1ms <= 3) then
sel_digit <= count_10s;
Anode <= "11111101";
elsif(count_1ms <= 5) then
sel_digit <= count_1min;
Anode <= "11111011";
elsif(count_1ms <= 7) then
sel_digit <= count_10min;
Anode <= "11110111";
elsif(count_1ms <= 9) then
sel_digit <= "0111";
Anode <= "11101111";
elsif(count_1ms <= 11) then
sel_digit <= "0000";
Anode <= "11011111";
elsif(count_1ms <= 13) then
sel_digit <= "1000";
Anode <= "10111111";
else
sel_digit <= "0010";
Anode <= "01111111";
end if;

end process;

led_green1 <= led_en(15);


led_red1 <= led_en(14);
led_blue1 <= led_en(13);
led_green2 <= led_en(12);
led_red2 <= led_en(11);
led_blue2 <= led_en(10);

end seven_segment_a;

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