Seven Segment
Seven Segment
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity seven_segment is
port(clk : in std_logic; --- 100 MHz oscillator on the board
reset : in std_logic;
Anode : out std_logic_vector(7 downto 0);
CA, CB, CC, CD, CE, CF, CG, DP : out std_logic;
led_green1, led_green2 : out std_logic;
led_red1, led_red2 : out std_logic;
led_blue1, led_blue2 : out std_logic;
led_en : in std_logic_vector(15 downto 0);
led_out : out std_logic_vector(15 downto 0)
);
end entity;
component rise_edge_det
port(clk : in std_logic; --- 100 MHz oscillator on the board
reset : in std_logic;
d_in : in std_logic;
rise_edge : out std_logic);
end component;
component display_logic
port(digit_in : in std_logic_vector(3 downto 0); --- 100 MHz oscillator on
the board
CA, CB, CC, CD, CE, CF, CG, DP : out std_logic
);
end component;
begin
elsif(rising_edge(clk)) then
else
led_s <= x"0000";
flag_1 <= '1';
flag_2 <= '1';
end if;
end if;
end if;
end process;
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end process;
end seven_segment_a;