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Sequence Detector Verilog

This Verilog code implements a sequence detector that identifies the sequence '1011'. It defines states for the detection process and uses a state machine to transition between them based on input signals. The output is activated when the detector reaches the final state corresponding to the detected sequence.

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22l141
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6 views2 pages

Sequence Detector Verilog

This Verilog code implements a sequence detector that identifies the sequence '1011'. It defines states for the detection process and uses a state machine to transition between them based on input signals. The output is activated when the detector reaches the final state corresponding to the detected sequence.

Uploaded by

22l141
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Verilog Code - Sequence Detector (Detects 1011)

`timescale 1ns / 1ns


module seq (
input clk,
input rst_n,
input in,
output out
);

parameter IDLE = 0,
S1 = 1,
S10 = 2,
S101 = 3,
S1011 = 4;

reg [2:0] cur_state, next_state;

// Output logic
assign out = (cur_state == S1011) ? 1 : 0;

// State register
always @(posedge clk) begin
if (!rst_n)
cur_state <= IDLE;
else
cur_state <= next_state;
end

// Next-state logic
always @(cur_state or in) begin
case (cur_state)
IDLE: begin
if (in)
next_state = S1;
else
next_state = IDLE;
end
S1: begin
if (in)
next_state = IDLE;
else
next_state = S10;
end
S10: begin
if (in)
next_state = S101;
else
next_state = IDLE;
end
S101: begin
if (in)
next_state = S1011;
else
next_state = IDLE;
end
S1011: begin
if (in)
next_state = S1; // Supports overlapping
sequences
else
next_state = S10; // Checks for potential new
start
end
default: next_state = IDLE;
endcase
end

endmodule

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